1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ 18 #define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 23 24 #define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 25 26 27 struct phyrx_other_receive_info_ru_details { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t ru_details_channel_0 : 32; // [31:0] 30 uint32_t ru_details_channel_1 : 32; // [31:0] 31 uint32_t spare : 32; // [31:0] 32 uint32_t tlv64_padding : 32; // [31:0] 33 #else 34 uint32_t ru_details_channel_0 : 32; // [31:0] 35 uint32_t ru_details_channel_1 : 32; // [31:0] 36 uint32_t spare : 32; // [31:0] 37 uint32_t tlv64_padding : 32; // [31:0] 38 #endif 39 }; 40 41 42 /* Description RU_DETAILS_CHANNEL_0 43 44 Ru_allocation from content channel 0 45 [7:0] for 20/40 MHz 46 [15:0] for 80 MHz 47 [31:0] for 160 MHz 48 <legal all> 49 */ 50 51 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 52 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 53 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 54 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff 55 56 57 /* Description RU_DETAILS_CHANNEL_1 58 59 Ru_allocation from content channel 1 60 [7:0] for 40 MHz 61 [15:0] for 80 MHz 62 [31:0] for 160 MHz 63 <legal all> 64 */ 65 66 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 67 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 68 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 69 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 70 71 72 /* Description SPARE 73 74 Extra spare bits added to convey additional information 75 <legal all> 76 */ 77 78 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 79 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 80 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 81 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff 82 83 84 /* Description TLV64_PADDING 85 86 Automatic DWORD padding inserted while converting TLV32 87 to TLV64 for 64 bit ARCH 88 <legal 0> 89 */ 90 91 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 92 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 93 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 94 #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 95 96 97 98 #endif // PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 99