1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ 18*5113495bSYour Name #define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ 19*5113495bSYour Name #if !defined(__ASSEMBLER__) 20*5113495bSYour Name #endif 21*5113495bSYour Name 22*5113495bSYour Name #define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 23*5113495bSYour Name 24*5113495bSYour Name #define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 25*5113495bSYour Name 26*5113495bSYour Name 27*5113495bSYour Name struct phyrx_other_receive_info_ru_details { 28*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29*5113495bSYour Name uint32_t ru_details_channel_0 : 32; // [31:0] 30*5113495bSYour Name uint32_t ru_details_channel_1 : 32; // [31:0] 31*5113495bSYour Name uint32_t spare : 32; // [31:0] 32*5113495bSYour Name uint32_t tlv64_padding : 32; // [31:0] 33*5113495bSYour Name #else 34*5113495bSYour Name uint32_t ru_details_channel_0 : 32; // [31:0] 35*5113495bSYour Name uint32_t ru_details_channel_1 : 32; // [31:0] 36*5113495bSYour Name uint32_t spare : 32; // [31:0] 37*5113495bSYour Name uint32_t tlv64_padding : 32; // [31:0] 38*5113495bSYour Name #endif 39*5113495bSYour Name }; 40*5113495bSYour Name 41*5113495bSYour Name 42*5113495bSYour Name /* Description RU_DETAILS_CHANNEL_0 43*5113495bSYour Name 44*5113495bSYour Name Ru_allocation from content channel 0 45*5113495bSYour Name [7:0] for 20/40 MHz 46*5113495bSYour Name [15:0] for 80 MHz 47*5113495bSYour Name [31:0] for 160 MHz 48*5113495bSYour Name <legal all> 49*5113495bSYour Name */ 50*5113495bSYour Name 51*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 52*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 53*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 54*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff 55*5113495bSYour Name 56*5113495bSYour Name 57*5113495bSYour Name /* Description RU_DETAILS_CHANNEL_1 58*5113495bSYour Name 59*5113495bSYour Name Ru_allocation from content channel 1 60*5113495bSYour Name [7:0] for 40 MHz 61*5113495bSYour Name [15:0] for 80 MHz 62*5113495bSYour Name [31:0] for 160 MHz 63*5113495bSYour Name <legal all> 64*5113495bSYour Name */ 65*5113495bSYour Name 66*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 67*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 68*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 69*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 70*5113495bSYour Name 71*5113495bSYour Name 72*5113495bSYour Name /* Description SPARE 73*5113495bSYour Name 74*5113495bSYour Name Extra spare bits added to convey additional information 75*5113495bSYour Name <legal all> 76*5113495bSYour Name */ 77*5113495bSYour Name 78*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 79*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 80*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 81*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff 82*5113495bSYour Name 83*5113495bSYour Name 84*5113495bSYour Name /* Description TLV64_PADDING 85*5113495bSYour Name 86*5113495bSYour Name Automatic DWORD padding inserted while converting TLV32 87*5113495bSYour Name to TLV64 for 64 bit ARCH 88*5113495bSYour Name <legal 0> 89*5113495bSYour Name */ 90*5113495bSYour Name 91*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 92*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 93*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 94*5113495bSYour Name #define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 95*5113495bSYour Name 96*5113495bSYour Name 97*5113495bSYour Name 98*5113495bSYour Name #endif // PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 99