1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_PKT_END_H_ 18 #define _PHYRX_PKT_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phyrx_pkt_end_info.h" 23 #define NUM_OF_DWORDS_PHYRX_PKT_END 24 24 25 #define NUM_OF_QWORDS_PHYRX_PKT_END 12 26 27 28 struct phyrx_pkt_end { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct phyrx_pkt_end_info rx_pkt_end_details; 31 #else 32 struct phyrx_pkt_end_info rx_pkt_end_details; 33 #endif 34 }; 35 36 37 /* Description RX_PKT_END_DETAILS 38 39 Overview of the final receive related parameters from the 40 PHY RX 41 */ 42 43 44 /* Description PHY_INTERNAL_NAP 45 46 When set, PHY RX entered an internal NAP state, as PHY determined 47 that this reception was not destined to this device 48 */ 49 50 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000 51 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 52 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0 53 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001 54 55 56 /* Description LOCATION_INFO_VALID 57 58 Indicates that the RX_LOCATION_INFO structure later on in 59 the TLV contains valid info 60 */ 61 62 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 63 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 64 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 65 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 66 67 68 /* Description TIMING_INFO_VALID 69 70 Indicates that the RX_TIMING_OFFSET_INFO structure later 71 on in the TLV contains valid info 72 */ 73 74 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 75 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 76 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 77 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 78 79 80 /* Description RSSI_INFO_VALID 81 82 Indicates that the RECEIVE_RSSI_INFO structure later on 83 in the TLV contains valid info 84 */ 85 86 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 87 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 88 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 89 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 90 91 92 /* Description RESERVED_0A 93 94 <legal 0> 95 */ 96 97 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 98 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 99 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 100 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 101 102 103 /* Description FRAMELESS_FRAME_RECEIVED 104 105 When set, PHY has received the 'frameless frame' . Can be 106 used in the 'MU-RTS -CTS exchange where CTS reception can 107 be problematic. 108 <legal all> 109 */ 110 111 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 112 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 113 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 114 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 115 116 117 /* Description RESERVED_0B 118 119 <legal 0> 120 */ 121 122 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 123 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 124 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 125 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 126 127 128 /* Description RSSI_COMB 129 130 Combined rssi of all chains. Based on primary channel RSSI. 131 132 133 This can be used by SW for cases, e.g. Ack/BlockAck responses, 134 where 'PHYRX_RSSI_LEGACY' is not available to SW. 135 136 RSSI is reported as 8b signed values. Nominally value is 137 in dB units above or below the noisefloor(minCCApwr). 138 139 The resolution can be: 140 1dB or 0.5dB. This is statically configured within the PHY 141 and MAC 142 143 In case of 1dB, the Range is: 144 -128dB to 127dB 145 146 In case of 0.5dB, the Range is: 147 -64dB to 63.5dB 148 149 <legal all> 150 */ 151 152 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 153 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 154 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 155 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 156 157 158 /* Description RESERVED_0C 159 160 <legal 0> 161 */ 162 163 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 164 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 165 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 166 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 167 168 169 /* Description PHY_TIMESTAMP_1_LOWER_32 170 171 TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI 172 of the first rising edge of rx_clear_pri after TX_PHY_DESC. . 173 This field should set to 0 by the PHY and should be updated 174 by the AMPI before being forwarded to the rest of the MAC. 175 This field indicates the lower 32 bits of the timestamp 176 */ 177 178 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 179 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 180 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 181 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 182 183 184 /* Description PHY_TIMESTAMP_1_UPPER_32 185 186 TODO PHY: cleanup description 187 The PHY timestamp in the AMPI of the first rising edge of 188 rx_clear_pri after TX_PHY_DESC. This field should set 189 to 0 by the PHY and should be updated by the AMPI before 190 being forwarded to the rest of the MAC. This field indicates 191 the upper 32 bits of the timestamp 192 */ 193 194 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 195 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 196 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 197 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff 198 199 200 /* Description PHY_TIMESTAMP_2_LOWER_32 201 202 TODO PHY: cleanup description 203 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 204 after RX_RSSI_LEGACY. This field should set to 0 by the 205 PHY and should be updated by the AMPI before being forwarded 206 to the rest of the MAC. This field indicates the lower 207 32 bits of the timestamp 208 */ 209 210 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 211 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 212 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 213 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 214 215 216 /* Description PHY_TIMESTAMP_2_UPPER_32 217 218 TODO PHY: cleanup description 219 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 220 after RX_RSSI_LEGACY. This field should set to 0 by the 221 PHY and should be updated by the AMPI before being forwarded 222 to the rest of the MAC. This field indicates the upper 223 32 bits of the timestamp 224 */ 225 226 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 227 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 228 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 229 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff 230 231 232 /* Description RX_TIMING_OFFSET_INFO_DETAILS 233 234 Overview of timing offset related info 235 */ 236 237 238 /* Description RESIDUAL_PHASE_OFFSET 239 240 Cumulative reference frequency error at end of RX packet, 241 expressed as the phase offset measured over 0.8us. 242 <legal all> 243 */ 244 245 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 246 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 247 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 248 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 249 250 251 /* Description RESERVED 252 253 <legal 0> 254 */ 255 256 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 257 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44 258 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63 259 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000 260 261 262 /* Description POST_RSSI_INFO_DETAILS 263 264 Overview of the post-RSSI values. 265 */ 266 267 268 /* Description RSSI_PRI20_CHAIN0 269 270 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 271 272 Value of 0x80 indicates invalid. 273 */ 274 275 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 276 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 277 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 278 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff 279 280 281 /* Description RSSI_EXT20_CHAIN0 282 283 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 284 285 Value of 0x80 indicates invalid. 286 */ 287 288 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 289 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 290 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 291 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 292 293 294 /* Description RSSI_EXT40_LOW20_CHAIN0 295 296 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 297 298 Value of 0x80 indicates invalid. 299 */ 300 301 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 302 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 303 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 304 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 305 306 307 /* Description RSSI_EXT40_HIGH20_CHAIN0 308 309 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 310 bandwidth. 311 Value of 0x80 indicates invalid. 312 */ 313 314 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 315 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 316 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 317 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 318 319 320 /* Description RSSI_EXT80_LOW20_CHAIN0 321 322 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 323 324 Value of 0x80 indicates invalid. 325 */ 326 327 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 328 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 329 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 330 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 331 332 333 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 334 335 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 336 MHz bandwidth. 337 Value of 0x80 indicates invalid. 338 */ 339 340 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 341 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 342 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 343 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 344 345 346 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 347 348 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 349 MHz bandwidth. 350 Value of 0x80 indicates invalid. 351 */ 352 353 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 354 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 355 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 356 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 357 358 359 /* Description RSSI_EXT80_HIGH20_CHAIN0 360 361 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 362 bandwidth. 363 Value of 0x80 indicates invalid. 364 */ 365 366 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 367 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 368 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 369 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 370 371 372 /* Description RSSI_EXT160_0_CHAIN0 373 374 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 375 bandwidth. 376 Value of 0x80 indicates invalid. 377 */ 378 379 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 380 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 381 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 382 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff 383 384 385 /* Description RSSI_EXT160_1_CHAIN0 386 387 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 388 bandwidth. 389 Value of 0x80 indicates invalid. 390 */ 391 392 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 393 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 394 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 395 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 396 397 398 /* Description RSSI_EXT160_2_CHAIN0 399 400 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 401 bandwidth. 402 Value of 0x80 indicates invalid. 403 */ 404 405 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 406 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 407 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 408 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 409 410 411 /* Description RSSI_EXT160_3_CHAIN0 412 413 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 414 bandwidth. 415 Value of 0x80 indicates invalid. 416 */ 417 418 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 419 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 420 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 421 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 422 423 424 /* Description RSSI_EXT160_4_CHAIN0 425 426 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 427 bandwidth. 428 Value of 0x80 indicates invalid. 429 */ 430 431 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 432 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 433 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 434 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 435 436 437 /* Description RSSI_EXT160_5_CHAIN0 438 439 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 440 bandwidth. 441 Value of 0x80 indicates invalid. 442 */ 443 444 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 445 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 446 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 447 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 448 449 450 /* Description RSSI_EXT160_6_CHAIN0 451 452 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 453 bandwidth. 454 Value of 0x80 indicates invalid. 455 */ 456 457 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 458 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 459 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 460 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 461 462 463 /* Description RSSI_EXT160_7_CHAIN0 464 465 RSSI of RX PPDU on chain 0 of extension 160, highest 20 466 MHz bandwidth. 467 Value of 0x80 indicates invalid. 468 */ 469 470 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 471 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 472 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 473 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 474 475 476 /* Description RSSI_PRI20_CHAIN1 477 478 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 479 480 Value of 0x80 indicates invalid. 481 */ 482 483 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 484 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 485 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 486 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff 487 488 489 /* Description RSSI_EXT20_CHAIN1 490 491 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 492 493 Value of 0x80 indicates invalid. 494 */ 495 496 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 497 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 498 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 499 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 500 501 502 /* Description RSSI_EXT40_LOW20_CHAIN1 503 504 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 505 506 Value of 0x80 indicates invalid. 507 */ 508 509 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 510 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 511 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 512 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 513 514 515 /* Description RSSI_EXT40_HIGH20_CHAIN1 516 517 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 518 bandwidth. 519 Value of 0x80 indicates invalid. 520 */ 521 522 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 523 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 524 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 525 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 526 527 528 /* Description RSSI_EXT80_LOW20_CHAIN1 529 530 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 531 532 Value of 0x80 indicates invalid. 533 */ 534 535 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 536 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 537 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 538 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 539 540 541 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 542 543 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 544 MHz bandwidth. 545 Value of 0x80 indicates invalid. 546 */ 547 548 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 549 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 550 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 551 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 552 553 554 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 555 556 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 557 MHz bandwidth. 558 Value of 0x80 indicates invalid. 559 */ 560 561 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 562 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 563 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 564 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 565 566 567 /* Description RSSI_EXT80_HIGH20_CHAIN1 568 569 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 570 bandwidth. 571 Value of 0x80 indicates invalid. 572 */ 573 574 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 575 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 576 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 577 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 578 579 580 /* Description RSSI_EXT160_0_CHAIN1 581 582 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 583 bandwidth. 584 Value of 0x80 indicates invalid. 585 */ 586 587 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 588 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 589 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 590 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff 591 592 593 /* Description RSSI_EXT160_1_CHAIN1 594 595 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 596 bandwidth. 597 Value of 0x80 indicates invalid. 598 */ 599 600 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 601 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 602 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 603 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 604 605 606 /* Description RSSI_EXT160_2_CHAIN1 607 608 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 609 bandwidth. 610 Value of 0x80 indicates invalid. 611 */ 612 613 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 614 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 615 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 616 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 617 618 619 /* Description RSSI_EXT160_3_CHAIN1 620 621 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 622 bandwidth. 623 Value of 0x80 indicates invalid. 624 */ 625 626 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 627 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 628 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 629 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 630 631 632 /* Description RSSI_EXT160_4_CHAIN1 633 634 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 635 bandwidth. 636 Value of 0x80 indicates invalid. 637 */ 638 639 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 640 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 641 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 642 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 643 644 645 /* Description RSSI_EXT160_5_CHAIN1 646 647 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 648 bandwidth. 649 Value of 0x80 indicates invalid. 650 */ 651 652 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 653 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 654 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 655 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 656 657 658 /* Description RSSI_EXT160_6_CHAIN1 659 660 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 661 bandwidth. 662 Value of 0x80 indicates invalid. 663 */ 664 665 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 666 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 667 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 668 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 669 670 671 /* Description RSSI_EXT160_7_CHAIN1 672 673 RSSI of RX PPDU on chain 1 of extension 160, highest 20 674 MHz bandwidth. 675 Value of 0x80 indicates invalid. 676 */ 677 678 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 679 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 680 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 681 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 682 683 684 /* Description RSSI_PRI20_CHAIN2 685 686 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 687 688 Value of 0x80 indicates invalid. 689 */ 690 691 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 692 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 693 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 694 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff 695 696 697 /* Description RSSI_EXT20_CHAIN2 698 699 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 700 701 Value of 0x80 indicates invalid. 702 */ 703 704 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 705 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 706 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 707 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 708 709 710 /* Description RSSI_EXT40_LOW20_CHAIN2 711 712 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 713 714 Value of 0x80 indicates invalid. 715 */ 716 717 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 718 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 719 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 720 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 721 722 723 /* Description RSSI_EXT40_HIGH20_CHAIN2 724 725 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 726 bandwidth. 727 Value of 0x80 indicates invalid. 728 */ 729 730 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 731 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 732 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 733 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 734 735 736 /* Description RSSI_EXT80_LOW20_CHAIN2 737 738 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 739 740 Value of 0x80 indicates invalid. 741 */ 742 743 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 744 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 745 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 746 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 747 748 749 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 750 751 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 752 MHz bandwidth. 753 Value of 0x80 indicates invalid. 754 */ 755 756 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 757 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 758 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 759 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 760 761 762 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 763 764 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 765 MHz bandwidth. 766 Value of 0x80 indicates invalid. 767 */ 768 769 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 770 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 771 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 772 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 773 774 775 /* Description RSSI_EXT80_HIGH20_CHAIN2 776 777 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 778 bandwidth. 779 Value of 0x80 indicates invalid. 780 */ 781 782 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 783 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 784 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 785 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 786 787 788 /* Description RSSI_EXT160_0_CHAIN2 789 790 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 791 bandwidth. 792 Value of 0x80 indicates invalid. 793 */ 794 795 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 796 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 797 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 798 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff 799 800 801 /* Description RSSI_EXT160_1_CHAIN2 802 803 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 804 bandwidth. 805 Value of 0x80 indicates invalid. 806 */ 807 808 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 809 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 810 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 811 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 812 813 814 /* Description RSSI_EXT160_2_CHAIN2 815 816 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 817 bandwidth. 818 Value of 0x80 indicates invalid. 819 */ 820 821 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 822 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 823 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 824 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 825 826 827 /* Description RSSI_EXT160_3_CHAIN2 828 829 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 830 bandwidth. 831 Value of 0x80 indicates invalid. 832 */ 833 834 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 835 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 836 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 837 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 838 839 840 /* Description RSSI_EXT160_4_CHAIN2 841 842 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 843 bandwidth. 844 Value of 0x80 indicates invalid. 845 */ 846 847 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 848 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 849 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 850 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 851 852 853 /* Description RSSI_EXT160_5_CHAIN2 854 855 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 856 bandwidth. 857 Value of 0x80 indicates invalid. 858 */ 859 860 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 861 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 862 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 863 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 864 865 866 /* Description RSSI_EXT160_6_CHAIN2 867 868 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 869 bandwidth. 870 Value of 0x80 indicates invalid. 871 */ 872 873 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 874 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 875 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 876 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 877 878 879 /* Description RSSI_EXT160_7_CHAIN2 880 881 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 882 bandwidth. 883 Value of 0x80 indicates invalid. 884 */ 885 886 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 887 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 888 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 889 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 890 891 892 /* Description RSSI_PRI20_CHAIN3 893 894 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 895 896 Value of 0x80 indicates invalid. 897 */ 898 899 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 900 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 901 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 902 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff 903 904 905 /* Description RSSI_EXT20_CHAIN3 906 907 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 908 909 Value of 0x80 indicates invalid. 910 */ 911 912 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 913 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 914 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 915 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 916 917 918 /* Description RSSI_EXT40_LOW20_CHAIN3 919 920 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 921 922 Value of 0x80 indicates invalid. 923 */ 924 925 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 926 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 927 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 928 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 929 930 931 /* Description RSSI_EXT40_HIGH20_CHAIN3 932 933 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 934 bandwidth. 935 Value of 0x80 indicates invalid. 936 */ 937 938 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 939 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 940 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 941 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 942 943 944 /* Description RSSI_EXT80_LOW20_CHAIN3 945 946 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 947 948 Value of 0x80 indicates invalid. 949 */ 950 951 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 952 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 953 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 954 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 955 956 957 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 958 959 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 960 MHz bandwidth. 961 Value of 0x80 indicates invalid. 962 */ 963 964 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 965 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 966 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 967 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 968 969 970 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 971 972 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 973 MHz bandwidth. 974 Value of 0x80 indicates invalid. 975 */ 976 977 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 978 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 979 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 980 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 981 982 983 /* Description RSSI_EXT80_HIGH20_CHAIN3 984 985 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 986 bandwidth. 987 Value of 0x80 indicates invalid. 988 */ 989 990 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 991 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 992 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 993 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 994 995 996 /* Description RSSI_EXT160_0_CHAIN3 997 998 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 999 bandwidth. 1000 Value of 0x80 indicates invalid. 1001 */ 1002 1003 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 1004 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1005 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1006 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff 1007 1008 1009 /* Description RSSI_EXT160_1_CHAIN3 1010 1011 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1012 bandwidth. 1013 Value of 0x80 indicates invalid. 1014 */ 1015 1016 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 1017 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1018 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1019 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 1020 1021 1022 /* Description RSSI_EXT160_2_CHAIN3 1023 1024 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1025 bandwidth. 1026 Value of 0x80 indicates invalid. 1027 */ 1028 1029 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 1030 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1031 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1032 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 1033 1034 1035 /* Description RSSI_EXT160_3_CHAIN3 1036 1037 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1038 bandwidth. 1039 Value of 0x80 indicates invalid. 1040 */ 1041 1042 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 1043 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1044 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1045 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 1046 1047 1048 /* Description RSSI_EXT160_4_CHAIN3 1049 1050 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1051 bandwidth. 1052 Value of 0x80 indicates invalid. 1053 */ 1054 1055 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 1056 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 1057 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 1058 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 1059 1060 1061 /* Description RSSI_EXT160_5_CHAIN3 1062 1063 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1064 bandwidth. 1065 Value of 0x80 indicates invalid. 1066 */ 1067 1068 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 1069 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 1070 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 1071 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 1072 1073 1074 /* Description RSSI_EXT160_6_CHAIN3 1075 1076 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1077 bandwidth. 1078 Value of 0x80 indicates invalid. 1079 */ 1080 1081 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 1082 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 1083 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 1084 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 1085 1086 1087 /* Description RSSI_EXT160_7_CHAIN3 1088 1089 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1090 MHz bandwidth. 1091 Value of 0x80 indicates invalid. 1092 */ 1093 1094 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 1095 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 1096 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 1097 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 1098 1099 1100 /* Description PHY_SW_STATUS_31_0 1101 1102 Some PHY micro code status that can be put in here. Details 1103 of definition within SW specification 1104 This field can be used for debugging, FW - SW message exchange, 1105 etc. 1106 It could for example be a pointer to a DDR memory location 1107 where PHY FW put some debug info. 1108 <legal all> 1109 */ 1110 1111 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 1112 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 1113 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 1114 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff 1115 1116 1117 /* Description PHY_SW_STATUS_63_32 1118 1119 Some PHY micro code status that can be put in here. Details 1120 of definition within SW specification 1121 This field can be used for debugging, FW - SW message exchange, 1122 etc. 1123 It could for example be a pointer to a DDR memory location 1124 where PHY FW put some debug info. 1125 <legal all> 1126 */ 1127 1128 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 1129 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 1130 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 1131 #define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 1132 1133 1134 1135 #endif // PHYRX_PKT_END 1136