1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_PKT_END_INFO_H_ 18 #define _PHYRX_PKT_END_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "receive_rssi_info.h" 23 #include "rx_timing_offset_info.h" 24 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 25 26 27 struct phyrx_pkt_end_info { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t phy_internal_nap : 1, // [0:0] 30 location_info_valid : 1, // [1:1] 31 timing_info_valid : 1, // [2:2] 32 rssi_info_valid : 1, // [3:3] 33 reserved_0a : 1, // [4:4] 34 frameless_frame_received : 1, // [5:5] 35 reserved_0b : 2, // [7:6] 36 rssi_comb : 8, // [15:8] 37 reserved_0c : 16; // [31:16] 38 uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] 39 uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] 40 uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] 41 uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] 42 struct rx_timing_offset_info rx_timing_offset_info_details; 43 struct receive_rssi_info post_rssi_info_details; 44 uint32_t phy_sw_status_31_0 : 32; // [31:0] 45 uint32_t phy_sw_status_63_32 : 32; // [31:0] 46 #else 47 uint32_t reserved_0c : 16, // [31:16] 48 rssi_comb : 8, // [15:8] 49 reserved_0b : 2, // [7:6] 50 frameless_frame_received : 1, // [5:5] 51 reserved_0a : 1, // [4:4] 52 rssi_info_valid : 1, // [3:3] 53 timing_info_valid : 1, // [2:2] 54 location_info_valid : 1, // [1:1] 55 phy_internal_nap : 1; // [0:0] 56 uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] 57 uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] 58 uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] 59 uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] 60 struct rx_timing_offset_info rx_timing_offset_info_details; 61 struct receive_rssi_info post_rssi_info_details; 62 uint32_t phy_sw_status_31_0 : 32; // [31:0] 63 uint32_t phy_sw_status_63_32 : 32; // [31:0] 64 #endif 65 }; 66 67 68 /* Description PHY_INTERNAL_NAP 69 70 When set, PHY RX entered an internal NAP state, as PHY determined 71 that this reception was not destined to this device 72 */ 73 74 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000 75 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0 76 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0 77 #define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001 78 79 80 /* Description LOCATION_INFO_VALID 81 82 Indicates that the RX_LOCATION_INFO structure later on in 83 the TLV contains valid info 84 */ 85 86 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 87 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 88 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 89 #define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 90 91 92 /* Description TIMING_INFO_VALID 93 94 Indicates that the RX_TIMING_OFFSET_INFO structure later 95 on in the TLV contains valid info 96 */ 97 98 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 99 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 100 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 101 #define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 102 103 104 /* Description RSSI_INFO_VALID 105 106 Indicates that the RECEIVE_RSSI_INFO structure later on 107 in the TLV contains valid info 108 */ 109 110 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 111 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 112 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 113 #define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 114 115 116 /* Description RESERVED_0A 117 118 <legal 0> 119 */ 120 121 #define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 122 #define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 123 #define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 124 #define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 125 126 127 /* Description FRAMELESS_FRAME_RECEIVED 128 129 When set, PHY has received the 'frameless frame' . Can be 130 used in the 'MU-RTS -CTS exchange where CTS reception can 131 be problematic. 132 <legal all> 133 */ 134 135 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 136 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 137 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 138 #define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 139 140 141 /* Description RESERVED_0B 142 143 <legal 0> 144 */ 145 146 #define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 147 #define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 148 #define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 149 #define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 150 151 152 /* Description RSSI_COMB 153 154 Combined rssi of all chains. Based on primary channel RSSI. 155 156 157 This can be used by SW for cases, e.g. Ack/BlockAck responses, 158 where 'PHYRX_RSSI_LEGACY' is not available to SW. 159 160 RSSI is reported as 8b signed values. Nominally value is 161 in dB units above or below the noisefloor(minCCApwr). 162 163 The resolution can be: 164 1dB or 0.5dB. This is statically configured within the PHY 165 and MAC 166 167 In case of 1dB, the Range is: 168 -128dB to 127dB 169 170 In case of 0.5dB, the Range is: 171 -64dB to 63.5dB 172 173 <legal all> 174 */ 175 176 #define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 177 #define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 178 #define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 179 #define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 180 181 182 /* Description RESERVED_0C 183 184 <legal 0> 185 */ 186 187 #define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 188 #define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 189 #define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 190 #define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 191 192 193 /* Description PHY_TIMESTAMP_1_LOWER_32 194 195 TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI 196 of the first rising edge of rx_clear_pri after TX_PHY_DESC. . 197 This field should set to 0 by the PHY and should be updated 198 by the AMPI before being forwarded to the rest of the MAC. 199 This field indicates the lower 32 bits of the timestamp 200 */ 201 202 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 203 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 204 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 205 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 206 207 208 /* Description PHY_TIMESTAMP_1_UPPER_32 209 210 TODO PHY: cleanup description 211 The PHY timestamp in the AMPI of the first rising edge of 212 rx_clear_pri after TX_PHY_DESC. This field should set 213 to 0 by the PHY and should be updated by the AMPI before 214 being forwarded to the rest of the MAC. This field indicates 215 the upper 32 bits of the timestamp 216 */ 217 218 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 219 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 220 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 221 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 222 223 224 /* Description PHY_TIMESTAMP_2_LOWER_32 225 226 TODO PHY: cleanup description 227 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 228 after RX_RSSI_LEGACY. This field should set to 0 by the 229 PHY and should be updated by the AMPI before being forwarded 230 to the rest of the MAC. This field indicates the lower 231 32 bits of the timestamp 232 */ 233 234 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 235 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 236 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 237 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 238 239 240 /* Description PHY_TIMESTAMP_2_UPPER_32 241 242 TODO PHY: cleanup description 243 The PHY timestamp in the AMPI of the rising edge of rx_clear_pri 244 after RX_RSSI_LEGACY. This field should set to 0 by the 245 PHY and should be updated by the AMPI before being forwarded 246 to the rest of the MAC. This field indicates the upper 247 32 bits of the timestamp 248 */ 249 250 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 251 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 252 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 253 #define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 254 255 256 /* Description RX_TIMING_OFFSET_INFO_DETAILS 257 258 Overview of timing offset related info 259 */ 260 261 262 /* Description RESIDUAL_PHASE_OFFSET 263 264 Cumulative reference frequency error at end of RX packet, 265 expressed as the phase offset measured over 0.8us. 266 <legal all> 267 */ 268 269 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 270 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 271 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 272 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 273 274 275 /* Description RESERVED 276 277 <legal 0> 278 */ 279 280 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014 281 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 282 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31 283 #define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 284 285 286 /* Description POST_RSSI_INFO_DETAILS 287 288 Overview of the post-RSSI values. 289 */ 290 291 292 /* Description RSSI_PRI20_CHAIN0 293 294 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 295 296 Value of 0x80 indicates invalid. 297 */ 298 299 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 300 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 301 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 302 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 303 304 305 /* Description RSSI_EXT20_CHAIN0 306 307 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 308 309 Value of 0x80 indicates invalid. 310 */ 311 312 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 313 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 314 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 315 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 316 317 318 /* Description RSSI_EXT40_LOW20_CHAIN0 319 320 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 321 322 Value of 0x80 indicates invalid. 323 */ 324 325 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 326 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 327 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 328 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 329 330 331 /* Description RSSI_EXT40_HIGH20_CHAIN0 332 333 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 334 bandwidth. 335 Value of 0x80 indicates invalid. 336 */ 337 338 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 339 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 340 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 341 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 342 343 344 /* Description RSSI_EXT80_LOW20_CHAIN0 345 346 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 347 348 Value of 0x80 indicates invalid. 349 */ 350 351 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c 352 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 353 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 354 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 355 356 357 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 358 359 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 360 MHz bandwidth. 361 Value of 0x80 indicates invalid. 362 */ 363 364 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c 365 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 366 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 367 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 368 369 370 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 371 372 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 373 MHz bandwidth. 374 Value of 0x80 indicates invalid. 375 */ 376 377 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c 378 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 379 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 380 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 381 382 383 /* Description RSSI_EXT80_HIGH20_CHAIN0 384 385 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 386 bandwidth. 387 Value of 0x80 indicates invalid. 388 */ 389 390 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c 391 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 392 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 393 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 394 395 396 /* Description RSSI_EXT160_0_CHAIN0 397 398 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 399 bandwidth. 400 Value of 0x80 indicates invalid. 401 */ 402 403 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 404 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 405 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 406 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff 407 408 409 /* Description RSSI_EXT160_1_CHAIN0 410 411 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 412 bandwidth. 413 Value of 0x80 indicates invalid. 414 */ 415 416 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 417 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 418 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 419 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 420 421 422 /* Description RSSI_EXT160_2_CHAIN0 423 424 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 425 bandwidth. 426 Value of 0x80 indicates invalid. 427 */ 428 429 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 430 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 431 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 432 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 433 434 435 /* Description RSSI_EXT160_3_CHAIN0 436 437 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 438 bandwidth. 439 Value of 0x80 indicates invalid. 440 */ 441 442 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 443 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 444 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 445 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 446 447 448 /* Description RSSI_EXT160_4_CHAIN0 449 450 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 451 bandwidth. 452 Value of 0x80 indicates invalid. 453 */ 454 455 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 456 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 457 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 458 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff 459 460 461 /* Description RSSI_EXT160_5_CHAIN0 462 463 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 464 bandwidth. 465 Value of 0x80 indicates invalid. 466 */ 467 468 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 469 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 470 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 471 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 472 473 474 /* Description RSSI_EXT160_6_CHAIN0 475 476 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 477 bandwidth. 478 Value of 0x80 indicates invalid. 479 */ 480 481 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 482 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 483 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 484 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 485 486 487 /* Description RSSI_EXT160_7_CHAIN0 488 489 RSSI of RX PPDU on chain 0 of extension 160, highest 20 490 MHz bandwidth. 491 Value of 0x80 indicates invalid. 492 */ 493 494 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 495 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 496 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 497 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 498 499 500 /* Description RSSI_PRI20_CHAIN1 501 502 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 503 504 Value of 0x80 indicates invalid. 505 */ 506 507 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 508 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 509 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 510 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 511 512 513 /* Description RSSI_EXT20_CHAIN1 514 515 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 516 517 Value of 0x80 indicates invalid. 518 */ 519 520 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 521 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 522 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 523 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 524 525 526 /* Description RSSI_EXT40_LOW20_CHAIN1 527 528 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 529 530 Value of 0x80 indicates invalid. 531 */ 532 533 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 534 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 535 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 536 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 537 538 539 /* Description RSSI_EXT40_HIGH20_CHAIN1 540 541 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 542 bandwidth. 543 Value of 0x80 indicates invalid. 544 */ 545 546 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 547 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 548 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 549 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 550 551 552 /* Description RSSI_EXT80_LOW20_CHAIN1 553 554 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 555 556 Value of 0x80 indicates invalid. 557 */ 558 559 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c 560 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 561 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 562 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 563 564 565 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 566 567 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 568 MHz bandwidth. 569 Value of 0x80 indicates invalid. 570 */ 571 572 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c 573 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 574 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 575 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 576 577 578 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 579 580 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 581 MHz bandwidth. 582 Value of 0x80 indicates invalid. 583 */ 584 585 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c 586 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 587 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 588 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 589 590 591 /* Description RSSI_EXT80_HIGH20_CHAIN1 592 593 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 594 bandwidth. 595 Value of 0x80 indicates invalid. 596 */ 597 598 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c 599 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 600 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 601 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 602 603 604 /* Description RSSI_EXT160_0_CHAIN1 605 606 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 607 bandwidth. 608 Value of 0x80 indicates invalid. 609 */ 610 611 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 612 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 613 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 614 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff 615 616 617 /* Description RSSI_EXT160_1_CHAIN1 618 619 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 620 bandwidth. 621 Value of 0x80 indicates invalid. 622 */ 623 624 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 625 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 626 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 627 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 628 629 630 /* Description RSSI_EXT160_2_CHAIN1 631 632 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 633 bandwidth. 634 Value of 0x80 indicates invalid. 635 */ 636 637 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 638 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 639 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 640 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 641 642 643 /* Description RSSI_EXT160_3_CHAIN1 644 645 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 646 bandwidth. 647 Value of 0x80 indicates invalid. 648 */ 649 650 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 651 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 652 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 653 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 654 655 656 /* Description RSSI_EXT160_4_CHAIN1 657 658 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 659 bandwidth. 660 Value of 0x80 indicates invalid. 661 */ 662 663 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 664 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 665 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 666 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff 667 668 669 /* Description RSSI_EXT160_5_CHAIN1 670 671 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 672 bandwidth. 673 Value of 0x80 indicates invalid. 674 */ 675 676 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 677 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 678 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 679 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 680 681 682 /* Description RSSI_EXT160_6_CHAIN1 683 684 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 685 bandwidth. 686 Value of 0x80 indicates invalid. 687 */ 688 689 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 690 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 691 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 692 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 693 694 695 /* Description RSSI_EXT160_7_CHAIN1 696 697 RSSI of RX PPDU on chain 1 of extension 160, highest 20 698 MHz bandwidth. 699 Value of 0x80 indicates invalid. 700 */ 701 702 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 703 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 704 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 705 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 706 707 708 /* Description RSSI_PRI20_CHAIN2 709 710 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 711 712 Value of 0x80 indicates invalid. 713 */ 714 715 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 716 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 717 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 718 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 719 720 721 /* Description RSSI_EXT20_CHAIN2 722 723 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 724 725 Value of 0x80 indicates invalid. 726 */ 727 728 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 729 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 730 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 731 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 732 733 734 /* Description RSSI_EXT40_LOW20_CHAIN2 735 736 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 737 738 Value of 0x80 indicates invalid. 739 */ 740 741 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 742 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 743 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 744 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 745 746 747 /* Description RSSI_EXT40_HIGH20_CHAIN2 748 749 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 750 bandwidth. 751 Value of 0x80 indicates invalid. 752 */ 753 754 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 755 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 756 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 757 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 758 759 760 /* Description RSSI_EXT80_LOW20_CHAIN2 761 762 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 763 764 Value of 0x80 indicates invalid. 765 */ 766 767 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c 768 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 769 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 770 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 771 772 773 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 774 775 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 776 MHz bandwidth. 777 Value of 0x80 indicates invalid. 778 */ 779 780 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c 781 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 782 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 783 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 784 785 786 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 787 788 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 789 MHz bandwidth. 790 Value of 0x80 indicates invalid. 791 */ 792 793 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c 794 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 795 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 796 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 797 798 799 /* Description RSSI_EXT80_HIGH20_CHAIN2 800 801 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 802 bandwidth. 803 Value of 0x80 indicates invalid. 804 */ 805 806 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c 807 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 808 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 809 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 810 811 812 /* Description RSSI_EXT160_0_CHAIN2 813 814 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 815 bandwidth. 816 Value of 0x80 indicates invalid. 817 */ 818 819 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 820 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 821 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 822 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff 823 824 825 /* Description RSSI_EXT160_1_CHAIN2 826 827 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 828 bandwidth. 829 Value of 0x80 indicates invalid. 830 */ 831 832 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 833 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 834 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 835 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 836 837 838 /* Description RSSI_EXT160_2_CHAIN2 839 840 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 841 bandwidth. 842 Value of 0x80 indicates invalid. 843 */ 844 845 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 846 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 847 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 848 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 849 850 851 /* Description RSSI_EXT160_3_CHAIN2 852 853 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 854 bandwidth. 855 Value of 0x80 indicates invalid. 856 */ 857 858 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 859 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 860 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 861 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 862 863 864 /* Description RSSI_EXT160_4_CHAIN2 865 866 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 867 bandwidth. 868 Value of 0x80 indicates invalid. 869 */ 870 871 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 872 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 873 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 874 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff 875 876 877 /* Description RSSI_EXT160_5_CHAIN2 878 879 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 880 bandwidth. 881 Value of 0x80 indicates invalid. 882 */ 883 884 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 885 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 886 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 887 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 888 889 890 /* Description RSSI_EXT160_6_CHAIN2 891 892 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 893 bandwidth. 894 Value of 0x80 indicates invalid. 895 */ 896 897 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 898 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 899 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 900 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 901 902 903 /* Description RSSI_EXT160_7_CHAIN2 904 905 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 906 bandwidth. 907 Value of 0x80 indicates invalid. 908 */ 909 910 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 911 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 912 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 913 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 914 915 916 /* Description RSSI_PRI20_CHAIN3 917 918 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 919 920 Value of 0x80 indicates invalid. 921 */ 922 923 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 924 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 925 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 926 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 927 928 929 /* Description RSSI_EXT20_CHAIN3 930 931 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 932 933 Value of 0x80 indicates invalid. 934 */ 935 936 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 937 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 938 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 939 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 940 941 942 /* Description RSSI_EXT40_LOW20_CHAIN3 943 944 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 945 946 Value of 0x80 indicates invalid. 947 */ 948 949 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 950 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 951 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 952 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 953 954 955 /* Description RSSI_EXT40_HIGH20_CHAIN3 956 957 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 958 bandwidth. 959 Value of 0x80 indicates invalid. 960 */ 961 962 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 963 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 964 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 965 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 966 967 968 /* Description RSSI_EXT80_LOW20_CHAIN3 969 970 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 971 972 Value of 0x80 indicates invalid. 973 */ 974 975 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c 976 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 977 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 978 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 979 980 981 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 982 983 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 984 MHz bandwidth. 985 Value of 0x80 indicates invalid. 986 */ 987 988 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c 989 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 990 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 991 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 992 993 994 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 995 996 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 997 MHz bandwidth. 998 Value of 0x80 indicates invalid. 999 */ 1000 1001 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c 1002 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1003 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 1004 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1005 1006 1007 /* Description RSSI_EXT80_HIGH20_CHAIN3 1008 1009 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1010 bandwidth. 1011 Value of 0x80 indicates invalid. 1012 */ 1013 1014 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c 1015 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1016 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 1017 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1018 1019 1020 /* Description RSSI_EXT160_0_CHAIN3 1021 1022 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1023 bandwidth. 1024 Value of 0x80 indicates invalid. 1025 */ 1026 1027 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 1028 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1029 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1030 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff 1031 1032 1033 /* Description RSSI_EXT160_1_CHAIN3 1034 1035 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1036 bandwidth. 1037 Value of 0x80 indicates invalid. 1038 */ 1039 1040 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 1041 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1042 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1043 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 1044 1045 1046 /* Description RSSI_EXT160_2_CHAIN3 1047 1048 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1049 bandwidth. 1050 Value of 0x80 indicates invalid. 1051 */ 1052 1053 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 1054 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1055 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1056 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 1057 1058 1059 /* Description RSSI_EXT160_3_CHAIN3 1060 1061 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1062 bandwidth. 1063 Value of 0x80 indicates invalid. 1064 */ 1065 1066 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 1067 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1068 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1069 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 1070 1071 1072 /* Description RSSI_EXT160_4_CHAIN3 1073 1074 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1075 bandwidth. 1076 Value of 0x80 indicates invalid. 1077 */ 1078 1079 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 1080 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 1081 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 1082 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff 1083 1084 1085 /* Description RSSI_EXT160_5_CHAIN3 1086 1087 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1088 bandwidth. 1089 Value of 0x80 indicates invalid. 1090 */ 1091 1092 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 1093 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 1094 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 1095 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 1096 1097 1098 /* Description RSSI_EXT160_6_CHAIN3 1099 1100 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1101 bandwidth. 1102 Value of 0x80 indicates invalid. 1103 */ 1104 1105 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 1106 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 1107 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 1108 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 1109 1110 1111 /* Description RSSI_EXT160_7_CHAIN3 1112 1113 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1114 MHz bandwidth. 1115 Value of 0x80 indicates invalid. 1116 */ 1117 1118 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 1119 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 1120 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 1121 #define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 1122 1123 1124 /* Description PHY_SW_STATUS_31_0 1125 1126 Some PHY micro code status that can be put in here. Details 1127 of definition within SW specification 1128 This field can be used for debugging, FW - SW message exchange, 1129 etc. 1130 It could for example be a pointer to a DDR memory location 1131 where PHY FW put some debug info. 1132 <legal all> 1133 */ 1134 1135 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 1136 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 1137 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 1138 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff 1139 1140 1141 /* Description PHY_SW_STATUS_63_32 1142 1143 Some PHY micro code status that can be put in here. Details 1144 of definition within SW specification 1145 This field can be used for debugging, FW - SW message exchange, 1146 etc. 1147 It could for example be a pointer to a DDR memory location 1148 where PHY FW put some debug info. 1149 <legal all> 1150 */ 1151 1152 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c 1153 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 1154 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 1155 #define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff 1156 1157 1158 1159 #endif // PHYRX_PKT_END_INFO 1160