1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_RSSI_LEGACY_H_ 18 #define _PHYRX_RSSI_LEGACY_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "receive_rssi_info.h" 23 #define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 24 25 #define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 26 27 28 struct phyrx_rssi_legacy { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 uint32_t reception_type : 4, // [3:0] 31 rx_chain_mask_type : 1, // [4:4] 32 receive_bandwidth : 3, // [7:5] 33 rx_chain_mask : 8, // [15:8] 34 phy_ppdu_id : 16; // [31:16] 35 uint32_t sw_phy_meta_data : 32; // [31:0] 36 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 37 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 38 uint32_t reserved_4a : 32; // [31:0] 39 uint32_t preamble_time_to_rxframe : 8, // [7:0] 40 standalone_snifer_mode : 1, // [8:8] 41 reserved_5a : 23; // [31:9] 42 uint32_t reserved_6a : 32; // [31:0] 43 uint32_t reserved_7a : 32; // [31:0] 44 struct receive_rssi_info pre_rssi_info_details; 45 struct receive_rssi_info preamble_rssi_info_details; 46 uint32_t pre_rssi_comb : 8, // [7:0] 47 rssi_comb : 8, // [15:8] 48 normalized_pre_rssi_comb : 8, // [23:16] 49 normalized_rssi_comb : 8; // [31:24] 50 uint32_t rssi_comb_ppdu : 8, // [7:0] 51 rssi_db_to_dbm_offset : 8, // [15:8] 52 rssi_for_spatial_reuse : 8, // [23:16] 53 rssi_for_trigger_resp : 8; // [31:24] 54 #else 55 uint32_t phy_ppdu_id : 16, // [31:16] 56 rx_chain_mask : 8, // [15:8] 57 receive_bandwidth : 3, // [7:5] 58 rx_chain_mask_type : 1, // [4:4] 59 reception_type : 4; // [3:0] 60 uint32_t sw_phy_meta_data : 32; // [31:0] 61 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 62 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 63 uint32_t reserved_4a : 32; // [31:0] 64 uint32_t reserved_5a : 23, // [31:9] 65 standalone_snifer_mode : 1, // [8:8] 66 preamble_time_to_rxframe : 8; // [7:0] 67 uint32_t reserved_6a : 32; // [31:0] 68 uint32_t reserved_7a : 32; // [31:0] 69 struct receive_rssi_info pre_rssi_info_details; 70 struct receive_rssi_info preamble_rssi_info_details; 71 uint32_t normalized_rssi_comb : 8, // [31:24] 72 normalized_pre_rssi_comb : 8, // [23:16] 73 rssi_comb : 8, // [15:8] 74 pre_rssi_comb : 8; // [7:0] 75 uint32_t rssi_for_trigger_resp : 8, // [31:24] 76 rssi_for_spatial_reuse : 8, // [23:16] 77 rssi_db_to_dbm_offset : 8, // [15:8] 78 rssi_comb_ppdu : 8; // [7:0] 79 #endif 80 }; 81 82 83 /* Description RECEPTION_TYPE 84 85 This field helps MAC SW determine which field in this (and 86 following TLVs) will contain valid information. For example 87 some RSSI info not valid in case of uplink_ofdma.. 88 89 In case of UL MU OFDMA or UL MU-MIMO reception pre-announced 90 by MAC during trigger Tx, e-nums 0 or 1 should be used. 91 92 93 In case of UL MU OFDMA+MIMO reception, or in case of UL 94 MU reception when PHY has not been pre-informed, e-num 2 95 should be used. 96 If this happens, the UL MU frame in the medium is by definition 97 not for this device. 98 99 <enum 0 reception_is_uplink_ofdma> 100 <enum 1 reception_is_uplink_mimo> 101 <enum 2 reception_is_other> 102 <enum 3 reception_is_frameless> PHY RX has been instructed 103 in advance that the upcoming reception is frameless. This 104 implieas that in advance it is known that all frames will 105 collide in the medium, and nothing can be properly decoded... 106 This can happen during the CTS reception in response to 107 the triggered MU-RTS transmission. 108 MAC takes no action when seeing this e_num. For the frameless 109 reception the indication in pkt_end is the final one evaluated 110 by the MAC 111 112 For the relationship between pkt_type and this field, see 113 the table at the end of this TLV description. 114 <legal 0-3> 115 */ 116 117 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x0000000000000000 118 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 119 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 120 #define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x000000000000000f 121 122 123 /* Description RX_CHAIN_MASK_TYPE 124 125 Indicates if the field rx_chain_mask represents the mask 126 at start of reception (on which the Rssi_comb value is 127 based), or the setting used during the remainder of the 128 reception 129 130 1'b0: rxtd.listen_pri80_mask 131 1'b1: Final receive mask 132 133 <legal all> 134 */ 135 136 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 137 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 138 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 139 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 140 141 142 /* Description RECEIVE_BANDWIDTH 143 144 Full receive Bandwidth 145 146 <enum 0 20_mhz>20 Mhz BW 147 <enum 1 40_mhz>40 Mhz BW 148 <enum 2 80_mhz>80 Mhz BW 149 <enum 3 160_mhz>160 Mhz BW 150 <enum 4 320_mhz>320 Mhz BW 151 <enum 5 240_mhz>240 Mhz BW 152 */ 153 154 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 155 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 156 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 157 #define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 158 159 160 /* Description RX_CHAIN_MASK 161 162 The chain mask at the start of the reception of this frame. 163 164 165 each bit is one antenna 166 0: the chain is NOT used 167 1: the chain is used 168 169 Supports up to 8 chains 170 171 Used in 11ax TPC calculations for UL OFDMA/MIMO and has 172 to be in sync with the rssi_comb value as this is also used 173 by the MAC for the TPC calculations. 174 <legal all> 175 */ 176 177 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x0000000000000000 178 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 179 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 180 #define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x000000000000ff00 181 182 183 /* Description PHY_PPDU_ID 184 185 A ppdu counter value that PHY increments for every PPDU 186 received. The counter value wraps around 187 <legal all> 188 */ 189 190 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x0000000000000000 191 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 192 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 193 #define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0x00000000ffff0000 194 195 196 /* Description SW_PHY_META_DATA 197 198 32 bit Meta data that SW can program in a 32 bit PHY register 199 and PHY will insert the value in every RX_RSSI_LEGACY TLV 200 that it generates. 201 SW uses this field to embed among other things some SW channel 202 info. 203 */ 204 205 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000000 206 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 32 207 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 63 208 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff00000000 209 210 211 /* Description PPDU_START_TIMESTAMP_31_0 212 213 Timestamp that indicates when the PPDU that contained this 214 MPDU started on the medium, lower 32 bits 215 216 Note that PHY will detect the start later, and will have 217 to derive out of the preamble info when the frame actually 218 appeared on the medium. 219 */ 220 221 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 222 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 223 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 224 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 225 226 227 /* Description PPDU_START_TIMESTAMP_63_32 228 229 Timestamp that indicates when the PPDU that contained this 230 MPDU started on the medium, upper 32 bits 231 232 Note that PHY will detect the start later, and will have 233 to derive out of the preamble info when the frame actually 234 appeared on the medium. 235 */ 236 237 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 238 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 32 239 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 63 240 #define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 241 242 243 /* Description RESERVED_4A 244 245 NOTE: DO not assign a field... Internally used in RXPCU 246 to store 'RX_PPDU_START::Rxframe_assert_timestamp.' 247 <legal 0> 248 */ 249 250 #define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 251 #define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 252 #define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 253 #define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0x00000000ffffffff 254 255 256 /* Description PREAMBLE_TIME_TO_RXFRAME 257 258 The time taken (in us) from the frame starting on the medium 259 and PHY raising 'rx_frame' 260 <legal all> 261 */ 262 263 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000010 264 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 32 265 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 39 266 #define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 267 268 269 /* Description STANDALONE_SNIFER_MODE 270 271 When set to 1, PHY has been configured to operate in the 272 stand alone sniffer mode. 273 When 0, PHY is operating in the "normal" mission mode. 274 <legal all> 275 */ 276 277 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_OFFSET 0x0000000000000010 278 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_LSB 40 279 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MSB 40 280 #define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MASK 0x0000010000000000 281 282 283 /* Description RESERVED_5A 284 285 <legal 0> 286 */ 287 288 #define PHYRX_RSSI_LEGACY_RESERVED_5A_OFFSET 0x0000000000000010 289 #define PHYRX_RSSI_LEGACY_RESERVED_5A_LSB 41 290 #define PHYRX_RSSI_LEGACY_RESERVED_5A_MSB 63 291 #define PHYRX_RSSI_LEGACY_RESERVED_5A_MASK 0xfffffe0000000000 292 293 294 /* Description RESERVED_6A 295 296 NOTE: DO not assign a field... Internally used in RXPCU 297 to construct 'RX_PPDU_START.' 298 <legal 0> 299 */ 300 301 #define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 302 #define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 303 #define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 304 #define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff 305 306 307 /* Description RESERVED_7A 308 309 NOTE: DO not assign a field... Internally used in RXPCU 310 to construct 'RX_PPDU_START.' 311 <legal 0> 312 */ 313 314 #define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 315 #define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 316 #define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 317 #define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 318 319 320 /* Description PRE_RSSI_INFO_DETAILS 321 322 This field is not valid when reception_is_uplink_ofdma 323 324 Overview of the pre-RSSI values. That is RSSI values measured 325 on the medium before this reception started. 326 */ 327 328 329 /* Description RSSI_PRI20_CHAIN0 330 331 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 332 333 Value of 0x80 indicates invalid. 334 */ 335 336 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 337 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 338 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 339 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff 340 341 342 /* Description RSSI_EXT20_CHAIN0 343 344 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 345 346 Value of 0x80 indicates invalid. 347 */ 348 349 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 350 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 351 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 352 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 353 354 355 /* Description RSSI_EXT40_LOW20_CHAIN0 356 357 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 358 359 Value of 0x80 indicates invalid. 360 */ 361 362 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 363 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 364 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 365 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 366 367 368 /* Description RSSI_EXT40_HIGH20_CHAIN0 369 370 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 371 bandwidth. 372 Value of 0x80 indicates invalid. 373 */ 374 375 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 376 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 377 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 378 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 379 380 381 /* Description RSSI_EXT80_LOW20_CHAIN0 382 383 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 384 385 Value of 0x80 indicates invalid. 386 */ 387 388 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 389 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 390 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 391 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 392 393 394 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 395 396 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 397 MHz bandwidth. 398 Value of 0x80 indicates invalid. 399 */ 400 401 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 402 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 403 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 404 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 405 406 407 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 408 409 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 410 MHz bandwidth. 411 Value of 0x80 indicates invalid. 412 */ 413 414 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 415 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 416 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 417 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 418 419 420 /* Description RSSI_EXT80_HIGH20_CHAIN0 421 422 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 423 bandwidth. 424 Value of 0x80 indicates invalid. 425 */ 426 427 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 428 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 429 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 430 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 431 432 433 /* Description RSSI_EXT160_0_CHAIN0 434 435 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 436 bandwidth. 437 Value of 0x80 indicates invalid. 438 */ 439 440 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 441 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 442 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 443 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff 444 445 446 /* Description RSSI_EXT160_1_CHAIN0 447 448 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 449 bandwidth. 450 Value of 0x80 indicates invalid. 451 */ 452 453 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 454 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 455 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 456 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 457 458 459 /* Description RSSI_EXT160_2_CHAIN0 460 461 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 462 bandwidth. 463 Value of 0x80 indicates invalid. 464 */ 465 466 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 467 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 468 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 469 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 470 471 472 /* Description RSSI_EXT160_3_CHAIN0 473 474 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 475 bandwidth. 476 Value of 0x80 indicates invalid. 477 */ 478 479 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 480 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 481 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 482 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 483 484 485 /* Description RSSI_EXT160_4_CHAIN0 486 487 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 488 bandwidth. 489 Value of 0x80 indicates invalid. 490 */ 491 492 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 493 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 494 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 495 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 496 497 498 /* Description RSSI_EXT160_5_CHAIN0 499 500 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 501 bandwidth. 502 Value of 0x80 indicates invalid. 503 */ 504 505 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 506 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 507 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 508 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 509 510 511 /* Description RSSI_EXT160_6_CHAIN0 512 513 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 514 bandwidth. 515 Value of 0x80 indicates invalid. 516 */ 517 518 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 519 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 520 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 521 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 522 523 524 /* Description RSSI_EXT160_7_CHAIN0 525 526 RSSI of RX PPDU on chain 0 of extension 160, highest 20 527 MHz bandwidth. 528 Value of 0x80 indicates invalid. 529 */ 530 531 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 532 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 533 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 534 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 535 536 537 /* Description RSSI_PRI20_CHAIN1 538 539 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 540 541 Value of 0x80 indicates invalid. 542 */ 543 544 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 545 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 546 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 547 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff 548 549 550 /* Description RSSI_EXT20_CHAIN1 551 552 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 553 554 Value of 0x80 indicates invalid. 555 */ 556 557 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 558 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 559 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 560 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 561 562 563 /* Description RSSI_EXT40_LOW20_CHAIN1 564 565 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 566 567 Value of 0x80 indicates invalid. 568 */ 569 570 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 571 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 572 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 573 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 574 575 576 /* Description RSSI_EXT40_HIGH20_CHAIN1 577 578 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 579 bandwidth. 580 Value of 0x80 indicates invalid. 581 */ 582 583 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 584 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 585 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 586 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 587 588 589 /* Description RSSI_EXT80_LOW20_CHAIN1 590 591 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 592 593 Value of 0x80 indicates invalid. 594 */ 595 596 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 597 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 598 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 599 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 600 601 602 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 603 604 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 605 MHz bandwidth. 606 Value of 0x80 indicates invalid. 607 */ 608 609 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 610 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 611 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 612 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 613 614 615 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 616 617 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 618 MHz bandwidth. 619 Value of 0x80 indicates invalid. 620 */ 621 622 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 623 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 624 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 625 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 626 627 628 /* Description RSSI_EXT80_HIGH20_CHAIN1 629 630 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 631 bandwidth. 632 Value of 0x80 indicates invalid. 633 */ 634 635 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 636 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 637 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 638 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 639 640 641 /* Description RSSI_EXT160_0_CHAIN1 642 643 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 644 bandwidth. 645 Value of 0x80 indicates invalid. 646 */ 647 648 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 649 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 650 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 651 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff 652 653 654 /* Description RSSI_EXT160_1_CHAIN1 655 656 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 657 bandwidth. 658 Value of 0x80 indicates invalid. 659 */ 660 661 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 662 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 663 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 664 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 665 666 667 /* Description RSSI_EXT160_2_CHAIN1 668 669 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 670 bandwidth. 671 Value of 0x80 indicates invalid. 672 */ 673 674 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 675 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 676 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 677 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 678 679 680 /* Description RSSI_EXT160_3_CHAIN1 681 682 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 683 bandwidth. 684 Value of 0x80 indicates invalid. 685 */ 686 687 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 688 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 689 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 690 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 691 692 693 /* Description RSSI_EXT160_4_CHAIN1 694 695 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 696 bandwidth. 697 Value of 0x80 indicates invalid. 698 */ 699 700 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 701 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 702 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 703 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 704 705 706 /* Description RSSI_EXT160_5_CHAIN1 707 708 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 709 bandwidth. 710 Value of 0x80 indicates invalid. 711 */ 712 713 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 714 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 715 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 716 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 717 718 719 /* Description RSSI_EXT160_6_CHAIN1 720 721 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 722 bandwidth. 723 Value of 0x80 indicates invalid. 724 */ 725 726 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 727 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 728 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 729 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 730 731 732 /* Description RSSI_EXT160_7_CHAIN1 733 734 RSSI of RX PPDU on chain 1 of extension 160, highest 20 735 MHz bandwidth. 736 Value of 0x80 indicates invalid. 737 */ 738 739 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 740 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 741 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 742 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 743 744 745 /* Description RSSI_PRI20_CHAIN2 746 747 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 748 749 Value of 0x80 indicates invalid. 750 */ 751 752 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 753 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 754 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 755 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff 756 757 758 /* Description RSSI_EXT20_CHAIN2 759 760 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 761 762 Value of 0x80 indicates invalid. 763 */ 764 765 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 766 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 767 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 768 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 769 770 771 /* Description RSSI_EXT40_LOW20_CHAIN2 772 773 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 774 775 Value of 0x80 indicates invalid. 776 */ 777 778 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 779 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 780 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 781 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 782 783 784 /* Description RSSI_EXT40_HIGH20_CHAIN2 785 786 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 787 bandwidth. 788 Value of 0x80 indicates invalid. 789 */ 790 791 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 792 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 793 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 794 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 795 796 797 /* Description RSSI_EXT80_LOW20_CHAIN2 798 799 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 800 801 Value of 0x80 indicates invalid. 802 */ 803 804 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 805 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 806 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 807 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 808 809 810 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 811 812 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 813 MHz bandwidth. 814 Value of 0x80 indicates invalid. 815 */ 816 817 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 818 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 819 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 820 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 821 822 823 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 824 825 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 826 MHz bandwidth. 827 Value of 0x80 indicates invalid. 828 */ 829 830 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 831 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 832 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 833 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 834 835 836 /* Description RSSI_EXT80_HIGH20_CHAIN2 837 838 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 839 bandwidth. 840 Value of 0x80 indicates invalid. 841 */ 842 843 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 844 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 845 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 846 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 847 848 849 /* Description RSSI_EXT160_0_CHAIN2 850 851 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 852 bandwidth. 853 Value of 0x80 indicates invalid. 854 */ 855 856 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 857 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 858 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 859 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff 860 861 862 /* Description RSSI_EXT160_1_CHAIN2 863 864 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 865 bandwidth. 866 Value of 0x80 indicates invalid. 867 */ 868 869 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 870 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 871 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 872 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 873 874 875 /* Description RSSI_EXT160_2_CHAIN2 876 877 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 878 bandwidth. 879 Value of 0x80 indicates invalid. 880 */ 881 882 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 883 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 884 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 885 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 886 887 888 /* Description RSSI_EXT160_3_CHAIN2 889 890 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 891 bandwidth. 892 Value of 0x80 indicates invalid. 893 */ 894 895 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 896 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 897 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 898 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 899 900 901 /* Description RSSI_EXT160_4_CHAIN2 902 903 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 904 bandwidth. 905 Value of 0x80 indicates invalid. 906 */ 907 908 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 909 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 910 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 911 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 912 913 914 /* Description RSSI_EXT160_5_CHAIN2 915 916 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 917 bandwidth. 918 Value of 0x80 indicates invalid. 919 */ 920 921 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 922 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 923 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 924 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 925 926 927 /* Description RSSI_EXT160_6_CHAIN2 928 929 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 930 bandwidth. 931 Value of 0x80 indicates invalid. 932 */ 933 934 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 935 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 936 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 937 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 938 939 940 /* Description RSSI_EXT160_7_CHAIN2 941 942 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 943 bandwidth. 944 Value of 0x80 indicates invalid. 945 */ 946 947 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 948 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 949 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 950 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 951 952 953 /* Description RSSI_PRI20_CHAIN3 954 955 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 956 957 Value of 0x80 indicates invalid. 958 */ 959 960 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 961 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 962 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 963 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff 964 965 966 /* Description RSSI_EXT20_CHAIN3 967 968 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 969 970 Value of 0x80 indicates invalid. 971 */ 972 973 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 974 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 975 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 976 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 977 978 979 /* Description RSSI_EXT40_LOW20_CHAIN3 980 981 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 982 983 Value of 0x80 indicates invalid. 984 */ 985 986 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 987 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 988 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 989 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 990 991 992 /* Description RSSI_EXT40_HIGH20_CHAIN3 993 994 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 995 bandwidth. 996 Value of 0x80 indicates invalid. 997 */ 998 999 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 1000 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1001 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 1002 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 1003 1004 1005 /* Description RSSI_EXT80_LOW20_CHAIN3 1006 1007 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 1008 1009 Value of 0x80 indicates invalid. 1010 */ 1011 1012 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 1013 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 1014 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 1015 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 1016 1017 1018 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 1019 1020 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1021 MHz bandwidth. 1022 Value of 0x80 indicates invalid. 1023 */ 1024 1025 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 1026 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 1027 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 1028 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 1029 1030 1031 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 1032 1033 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1034 MHz bandwidth. 1035 Value of 0x80 indicates invalid. 1036 */ 1037 1038 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 1039 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 1040 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 1041 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 1042 1043 1044 /* Description RSSI_EXT80_HIGH20_CHAIN3 1045 1046 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1047 bandwidth. 1048 Value of 0x80 indicates invalid. 1049 */ 1050 1051 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 1052 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 1053 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 1054 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 1055 1056 1057 /* Description RSSI_EXT160_0_CHAIN3 1058 1059 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1060 bandwidth. 1061 Value of 0x80 indicates invalid. 1062 */ 1063 1064 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 1065 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1066 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1067 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff 1068 1069 1070 /* Description RSSI_EXT160_1_CHAIN3 1071 1072 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1073 bandwidth. 1074 Value of 0x80 indicates invalid. 1075 */ 1076 1077 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 1078 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1079 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1080 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 1081 1082 1083 /* Description RSSI_EXT160_2_CHAIN3 1084 1085 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1086 bandwidth. 1087 Value of 0x80 indicates invalid. 1088 */ 1089 1090 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 1091 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1092 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1093 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 1094 1095 1096 /* Description RSSI_EXT160_3_CHAIN3 1097 1098 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1099 bandwidth. 1100 Value of 0x80 indicates invalid. 1101 */ 1102 1103 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 1104 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1105 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1106 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 1107 1108 1109 /* Description RSSI_EXT160_4_CHAIN3 1110 1111 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1112 bandwidth. 1113 Value of 0x80 indicates invalid. 1114 */ 1115 1116 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 1117 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 1118 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 1119 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 1120 1121 1122 /* Description RSSI_EXT160_5_CHAIN3 1123 1124 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1125 bandwidth. 1126 Value of 0x80 indicates invalid. 1127 */ 1128 1129 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 1130 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 1131 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 1132 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 1133 1134 1135 /* Description RSSI_EXT160_6_CHAIN3 1136 1137 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1138 bandwidth. 1139 Value of 0x80 indicates invalid. 1140 */ 1141 1142 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 1143 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 1144 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 1145 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 1146 1147 1148 /* Description RSSI_EXT160_7_CHAIN3 1149 1150 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1151 MHz bandwidth. 1152 Value of 0x80 indicates invalid. 1153 */ 1154 1155 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 1156 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 1157 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 1158 #define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 1159 1160 1161 /* Description PREAMBLE_RSSI_INFO_DETAILS 1162 1163 This field is not valid when reception_is_uplink_ofdma 1164 1165 Overview of the RSSI values measured during the pre-amble 1166 phase of this reception 1167 */ 1168 1169 1170 /* Description RSSI_PRI20_CHAIN0 1171 1172 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1173 1174 Value of 0x80 indicates invalid. 1175 */ 1176 1177 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 1178 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1179 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 1180 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff 1181 1182 1183 /* Description RSSI_EXT20_CHAIN0 1184 1185 RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. 1186 1187 Value of 0x80 indicates invalid. 1188 */ 1189 1190 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 1191 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1192 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 1193 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 1194 1195 1196 /* Description RSSI_EXT40_LOW20_CHAIN0 1197 1198 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. 1199 1200 Value of 0x80 indicates invalid. 1201 */ 1202 1203 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 1204 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1205 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 1206 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 1207 1208 1209 /* Description RSSI_EXT40_HIGH20_CHAIN0 1210 1211 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1212 bandwidth. 1213 Value of 0x80 indicates invalid. 1214 */ 1215 1216 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 1217 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1218 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 1219 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 1220 1221 1222 /* Description RSSI_EXT80_LOW20_CHAIN0 1223 1224 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. 1225 1226 Value of 0x80 indicates invalid. 1227 */ 1228 1229 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 1230 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 1231 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 1232 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 1233 1234 1235 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 1236 1237 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1238 MHz bandwidth. 1239 Value of 0x80 indicates invalid. 1240 */ 1241 1242 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 1243 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 1244 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 1245 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 1246 1247 1248 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 1249 1250 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1251 MHz bandwidth. 1252 Value of 0x80 indicates invalid. 1253 */ 1254 1255 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 1256 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 1257 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 1258 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 1259 1260 1261 /* Description RSSI_EXT80_HIGH20_CHAIN0 1262 1263 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1264 bandwidth. 1265 Value of 0x80 indicates invalid. 1266 */ 1267 1268 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 1269 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 1270 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 1271 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 1272 1273 1274 /* Description RSSI_EXT160_0_CHAIN0 1275 1276 RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz 1277 bandwidth. 1278 Value of 0x80 indicates invalid. 1279 */ 1280 1281 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 1282 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 1283 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 1284 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff 1285 1286 1287 /* Description RSSI_EXT160_1_CHAIN0 1288 1289 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1290 bandwidth. 1291 Value of 0x80 indicates invalid. 1292 */ 1293 1294 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 1295 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 1296 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 1297 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 1298 1299 1300 /* Description RSSI_EXT160_2_CHAIN0 1301 1302 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1303 bandwidth. 1304 Value of 0x80 indicates invalid. 1305 */ 1306 1307 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 1308 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 1309 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 1310 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 1311 1312 1313 /* Description RSSI_EXT160_3_CHAIN0 1314 1315 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1316 bandwidth. 1317 Value of 0x80 indicates invalid. 1318 */ 1319 1320 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 1321 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 1322 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 1323 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 1324 1325 1326 /* Description RSSI_EXT160_4_CHAIN0 1327 1328 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1329 bandwidth. 1330 Value of 0x80 indicates invalid. 1331 */ 1332 1333 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 1334 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 1335 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 1336 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 1337 1338 1339 /* Description RSSI_EXT160_5_CHAIN0 1340 1341 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1342 bandwidth. 1343 Value of 0x80 indicates invalid. 1344 */ 1345 1346 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 1347 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 1348 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 1349 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 1350 1351 1352 /* Description RSSI_EXT160_6_CHAIN0 1353 1354 RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz 1355 bandwidth. 1356 Value of 0x80 indicates invalid. 1357 */ 1358 1359 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 1360 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 1361 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 1362 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 1363 1364 1365 /* Description RSSI_EXT160_7_CHAIN0 1366 1367 RSSI of RX PPDU on chain 0 of extension 160, highest 20 1368 MHz bandwidth. 1369 Value of 0x80 indicates invalid. 1370 */ 1371 1372 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 1373 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 1374 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 1375 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 1376 1377 1378 /* Description RSSI_PRI20_CHAIN1 1379 1380 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1381 1382 Value of 0x80 indicates invalid. 1383 */ 1384 1385 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 1386 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1387 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 1388 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff 1389 1390 1391 /* Description RSSI_EXT20_CHAIN1 1392 1393 RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. 1394 1395 Value of 0x80 indicates invalid. 1396 */ 1397 1398 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 1399 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1400 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 1401 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 1402 1403 1404 /* Description RSSI_EXT40_LOW20_CHAIN1 1405 1406 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. 1407 1408 Value of 0x80 indicates invalid. 1409 */ 1410 1411 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 1412 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1413 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 1414 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 1415 1416 1417 /* Description RSSI_EXT40_HIGH20_CHAIN1 1418 1419 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1420 bandwidth. 1421 Value of 0x80 indicates invalid. 1422 */ 1423 1424 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 1425 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1426 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 1427 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 1428 1429 1430 /* Description RSSI_EXT80_LOW20_CHAIN1 1431 1432 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. 1433 1434 Value of 0x80 indicates invalid. 1435 */ 1436 1437 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 1438 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 1439 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 1440 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 1441 1442 1443 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 1444 1445 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1446 MHz bandwidth. 1447 Value of 0x80 indicates invalid. 1448 */ 1449 1450 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 1451 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 1452 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 1453 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 1454 1455 1456 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 1457 1458 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1459 MHz bandwidth. 1460 Value of 0x80 indicates invalid. 1461 */ 1462 1463 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 1464 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 1465 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 1466 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 1467 1468 1469 /* Description RSSI_EXT80_HIGH20_CHAIN1 1470 1471 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1472 bandwidth. 1473 Value of 0x80 indicates invalid. 1474 */ 1475 1476 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 1477 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 1478 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 1479 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 1480 1481 1482 /* Description RSSI_EXT160_0_CHAIN1 1483 1484 RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz 1485 bandwidth. 1486 Value of 0x80 indicates invalid. 1487 */ 1488 1489 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 1490 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 1491 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 1492 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff 1493 1494 1495 /* Description RSSI_EXT160_1_CHAIN1 1496 1497 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1498 bandwidth. 1499 Value of 0x80 indicates invalid. 1500 */ 1501 1502 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 1503 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 1504 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 1505 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 1506 1507 1508 /* Description RSSI_EXT160_2_CHAIN1 1509 1510 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1511 bandwidth. 1512 Value of 0x80 indicates invalid. 1513 */ 1514 1515 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 1516 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 1517 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 1518 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 1519 1520 1521 /* Description RSSI_EXT160_3_CHAIN1 1522 1523 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1524 bandwidth. 1525 Value of 0x80 indicates invalid. 1526 */ 1527 1528 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 1529 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 1530 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 1531 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 1532 1533 1534 /* Description RSSI_EXT160_4_CHAIN1 1535 1536 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1537 bandwidth. 1538 Value of 0x80 indicates invalid. 1539 */ 1540 1541 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 1542 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 1543 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 1544 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 1545 1546 1547 /* Description RSSI_EXT160_5_CHAIN1 1548 1549 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1550 bandwidth. 1551 Value of 0x80 indicates invalid. 1552 */ 1553 1554 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 1555 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 1556 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 1557 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 1558 1559 1560 /* Description RSSI_EXT160_6_CHAIN1 1561 1562 RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz 1563 bandwidth. 1564 Value of 0x80 indicates invalid. 1565 */ 1566 1567 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 1568 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 1569 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 1570 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 1571 1572 1573 /* Description RSSI_EXT160_7_CHAIN1 1574 1575 RSSI of RX PPDU on chain 1 of extension 160, highest 20 1576 MHz bandwidth. 1577 Value of 0x80 indicates invalid. 1578 */ 1579 1580 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 1581 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 1582 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 1583 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 1584 1585 1586 /* Description RSSI_PRI20_CHAIN2 1587 1588 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1589 1590 Value of 0x80 indicates invalid. 1591 */ 1592 1593 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 1594 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1595 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 1596 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff 1597 1598 1599 /* Description RSSI_EXT20_CHAIN2 1600 1601 RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. 1602 1603 Value of 0x80 indicates invalid. 1604 */ 1605 1606 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 1607 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1608 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 1609 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 1610 1611 1612 /* Description RSSI_EXT40_LOW20_CHAIN2 1613 1614 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. 1615 1616 Value of 0x80 indicates invalid. 1617 */ 1618 1619 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 1620 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1621 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 1622 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 1623 1624 1625 /* Description RSSI_EXT40_HIGH20_CHAIN2 1626 1627 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1628 bandwidth. 1629 Value of 0x80 indicates invalid. 1630 */ 1631 1632 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 1633 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1634 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 1635 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 1636 1637 1638 /* Description RSSI_EXT80_LOW20_CHAIN2 1639 1640 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. 1641 1642 Value of 0x80 indicates invalid. 1643 */ 1644 1645 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 1646 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 1647 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 1648 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 1649 1650 1651 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 1652 1653 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1654 MHz bandwidth. 1655 Value of 0x80 indicates invalid. 1656 */ 1657 1658 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 1659 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 1660 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 1661 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 1662 1663 1664 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 1665 1666 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1667 MHz bandwidth. 1668 Value of 0x80 indicates invalid. 1669 */ 1670 1671 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 1672 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 1673 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 1674 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 1675 1676 1677 /* Description RSSI_EXT80_HIGH20_CHAIN2 1678 1679 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1680 bandwidth. 1681 Value of 0x80 indicates invalid. 1682 */ 1683 1684 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 1685 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 1686 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 1687 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 1688 1689 1690 /* Description RSSI_EXT160_0_CHAIN2 1691 1692 RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz 1693 bandwidth. 1694 Value of 0x80 indicates invalid. 1695 */ 1696 1697 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 1698 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 1699 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 1700 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff 1701 1702 1703 /* Description RSSI_EXT160_1_CHAIN2 1704 1705 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1706 bandwidth. 1707 Value of 0x80 indicates invalid. 1708 */ 1709 1710 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 1711 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 1712 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 1713 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 1714 1715 1716 /* Description RSSI_EXT160_2_CHAIN2 1717 1718 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1719 bandwidth. 1720 Value of 0x80 indicates invalid. 1721 */ 1722 1723 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 1724 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 1725 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 1726 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 1727 1728 1729 /* Description RSSI_EXT160_3_CHAIN2 1730 1731 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1732 bandwidth. 1733 Value of 0x80 indicates invalid. 1734 */ 1735 1736 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 1737 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 1738 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 1739 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 1740 1741 1742 /* Description RSSI_EXT160_4_CHAIN2 1743 1744 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1745 bandwidth. 1746 Value of 0x80 indicates invalid. 1747 */ 1748 1749 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 1750 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 1751 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 1752 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 1753 1754 1755 /* Description RSSI_EXT160_5_CHAIN2 1756 1757 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1758 bandwidth. 1759 Value of 0x80 indicates invalid. 1760 */ 1761 1762 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 1763 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 1764 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 1765 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 1766 1767 1768 /* Description RSSI_EXT160_6_CHAIN2 1769 1770 RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz 1771 bandwidth. 1772 Value of 0x80 indicates invalid. 1773 */ 1774 1775 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 1776 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 1777 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 1778 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 1779 1780 1781 /* Description RSSI_EXT160_7_CHAIN2 1782 1783 RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz 1784 bandwidth. 1785 Value of 0x80 indicates invalid. 1786 */ 1787 1788 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 1789 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 1790 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 1791 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 1792 1793 1794 /* Description RSSI_PRI20_CHAIN3 1795 1796 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1797 1798 Value of 0x80 indicates invalid. 1799 */ 1800 1801 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 1802 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1803 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 1804 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff 1805 1806 1807 /* Description RSSI_EXT20_CHAIN3 1808 1809 RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. 1810 1811 Value of 0x80 indicates invalid. 1812 */ 1813 1814 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 1815 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1816 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 1817 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 1818 1819 1820 /* Description RSSI_EXT40_LOW20_CHAIN3 1821 1822 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. 1823 1824 Value of 0x80 indicates invalid. 1825 */ 1826 1827 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 1828 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1829 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 1830 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 1831 1832 1833 /* Description RSSI_EXT40_HIGH20_CHAIN3 1834 1835 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1836 bandwidth. 1837 Value of 0x80 indicates invalid. 1838 */ 1839 1840 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 1841 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1842 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 1843 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 1844 1845 1846 /* Description RSSI_EXT80_LOW20_CHAIN3 1847 1848 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. 1849 1850 Value of 0x80 indicates invalid. 1851 */ 1852 1853 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 1854 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 1855 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 1856 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 1857 1858 1859 /* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 1860 1861 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1862 MHz bandwidth. 1863 Value of 0x80 indicates invalid. 1864 */ 1865 1866 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 1867 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 1868 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 1869 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 1870 1871 1872 /* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 1873 1874 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1875 MHz bandwidth. 1876 Value of 0x80 indicates invalid. 1877 */ 1878 1879 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 1880 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 1881 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 1882 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 1883 1884 1885 /* Description RSSI_EXT80_HIGH20_CHAIN3 1886 1887 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1888 bandwidth. 1889 Value of 0x80 indicates invalid. 1890 */ 1891 1892 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 1893 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 1894 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 1895 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 1896 1897 1898 /* Description RSSI_EXT160_0_CHAIN3 1899 1900 RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz 1901 bandwidth. 1902 Value of 0x80 indicates invalid. 1903 */ 1904 1905 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 1906 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 1907 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 1908 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff 1909 1910 1911 /* Description RSSI_EXT160_1_CHAIN3 1912 1913 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1914 bandwidth. 1915 Value of 0x80 indicates invalid. 1916 */ 1917 1918 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 1919 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 1920 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 1921 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 1922 1923 1924 /* Description RSSI_EXT160_2_CHAIN3 1925 1926 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1927 bandwidth. 1928 Value of 0x80 indicates invalid. 1929 */ 1930 1931 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 1932 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 1933 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 1934 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 1935 1936 1937 /* Description RSSI_EXT160_3_CHAIN3 1938 1939 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1940 bandwidth. 1941 Value of 0x80 indicates invalid. 1942 */ 1943 1944 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 1945 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 1946 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 1947 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 1948 1949 1950 /* Description RSSI_EXT160_4_CHAIN3 1951 1952 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1953 bandwidth. 1954 Value of 0x80 indicates invalid. 1955 */ 1956 1957 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 1958 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 1959 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 1960 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 1961 1962 1963 /* Description RSSI_EXT160_5_CHAIN3 1964 1965 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1966 bandwidth. 1967 Value of 0x80 indicates invalid. 1968 */ 1969 1970 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 1971 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 1972 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 1973 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 1974 1975 1976 /* Description RSSI_EXT160_6_CHAIN3 1977 1978 RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz 1979 bandwidth. 1980 Value of 0x80 indicates invalid. 1981 */ 1982 1983 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 1984 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 1985 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 1986 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 1987 1988 1989 /* Description RSSI_EXT160_7_CHAIN3 1990 1991 RSSI of RX PPDU on chain 3 of extension 160, highest 20 1992 MHz bandwidth. 1993 Value of 0x80 indicates invalid. 1994 */ 1995 1996 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 1997 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 1998 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 1999 #define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 2000 2001 2002 /* Description PRE_RSSI_COMB 2003 2004 Combined pre_rssi of all chains. Based on primary channel 2005 RSSI. 2006 2007 RSSI is reported as 8b signed values. Nominally value is 2008 in dB units above or below the noisefloor(minCCApwr). 2009 2010 The resolution can be: 2011 1dB or 0.5dB. This is statically configured within the PHY 2012 and MAC 2013 2014 In case of 1dB, the Range is: 2015 -128dB to 127dB 2016 2017 In case of 0.5dB, the Range is: 2018 -64dB to 63.5dB 2019 2020 <legal all> 2021 */ 2022 2023 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 2024 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 2025 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 2026 #define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff 2027 2028 2029 /* Description RSSI_COMB 2030 2031 Combined rssi of all chains. Based on primary channel RSSI. 2032 2033 2034 RSSI is reported as 8b signed values. Nominally value is 2035 in dB units above or below the noisefloor(minCCApwr). 2036 2037 The resolution can be: 2038 1dB or 0.5dB. This is statically configured within the PHY 2039 and MAC 2040 2041 In case of 1dB, the Range is: 2042 -128dB to 127dB 2043 2044 In case of 0.5dB, the Range is: 2045 -64dB to 63.5dB 2046 2047 <legal all> 2048 */ 2049 2050 #define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 2051 #define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 2052 #define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 2053 #define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 2054 2055 2056 /* Description NORMALIZED_PRE_RSSI_COMB 2057 2058 Combined pre_rssi of all chains, but "normalized" back to 2059 a single chain. This avoids PDG from having to evaluate 2060 this in combination with receive chain mask and perform 2061 all kinds of pre-processing algorithms. 2062 2063 Based on primary channel RSSI. 2064 2065 RSSI is reported as 8b signed values. Nominally value is 2066 in dB units above or below the noisefloor(minCCApwr). 2067 2068 The resolution can be: 2069 1dB or 0.5dB. This is statically configured within the PHY 2070 and MAC 2071 2072 In case of 1dB, the Range is: 2073 -128dB to 127dB 2074 2075 In case of 0.5dB, the Range is: 2076 -64dB to 63.5dB 2077 2078 <legal all> 2079 */ 2080 2081 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 2082 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 2083 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 2084 #define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 2085 2086 2087 /* Description NORMALIZED_RSSI_COMB 2088 2089 Combined rssi of all chains, but "normalized" back to a 2090 single chain. This avoids PDG from having to evaluate this 2091 in combination with receive chain mask and perform all 2092 kinds of pre-processing algorithms. 2093 2094 Based on primary channel RSSI. 2095 2096 RSSI is reported as 8b signed values. Nominally value is 2097 in dB units above or below the noisefloor(minCCApwr). 2098 2099 The resolution can be: 2100 1dB or 0.5dB. This is statically configured within the PHY 2101 and MAC 2102 In case of 1dB, the Range is: 2103 -128dB to 127dB 2104 2105 In case of 0.5dB, the Range is: 2106 -64dB to 63.5dB 2107 2108 <legal all> 2109 */ 2110 2111 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 2112 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 2113 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 2114 #define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 2115 2116 2117 /* Description RSSI_COMB_PPDU 2118 2119 Combined rssi of all chains, based on active RUs/subchannels, 2120 a.k.a. rssi_pkt_bw_mac 2121 2122 RSSI is reported as 8b signed values. Nominally value is 2123 in dB units above or below the noisefloor(minCCApwr). 2124 2125 The resolution can be: 2126 1dB or 0.5dB. This is statically configured within the PHY 2127 and MAC 2128 2129 In case of 1dB, the Range is: 2130 -128dB to 127dB 2131 2132 In case of 0.5dB, the Range is: 2133 -64dB to 63.5dB 2134 2135 When packet BW is 20 MHz, 2136 rssi_comb_ppdu = rssi_comb. 2137 2138 When packet BW > 20 MHz, 2139 rssi_comb < rssi_comb_ppdu because rssi_comb only includes 2140 power of primary 20 MHz while rssi_comb_ppdu includes power 2141 of active RUs/subchannels. 2142 2143 <legal all> 2144 */ 2145 2146 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 2147 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 2148 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 2149 #define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 2150 2151 2152 /* Description RSSI_DB_TO_DBM_OFFSET 2153 2154 Offset between 'dB' and 'dBm' values. SW can use this value 2155 to convert RSSI 'dBm' values back to 'dB,' and report both 2156 the values. 2157 2158 When rssi_db_to_dbm_offset = 0, 2159 all rssi_xxx fields are defined in dB. 2160 2161 When rssi_db_to_dbm_offset is a large negative value, all 2162 rssi_xxx fields are defined in dBm. 2163 2164 <legal all> 2165 */ 2166 2167 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 2168 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 2169 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 2170 #define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 2171 2172 2173 /* Description RSSI_FOR_SPATIAL_REUSE 2174 2175 RSSI to be used by HWSCH for transmit (power) selection 2176 during an SR opportunity, reported as an 8-bit signed value 2177 2178 2179 The resolution can be: 2180 1dB or 0.5dB. This is statically configured within the PHY 2181 and MAC 2182 2183 In case of 1dB, the Range is: 2184 -128dB to 127dB 2185 2186 In case of 0.5dB, the Range is: 2187 -64dB to 63.5dB 2188 2189 As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for 2190 OBSS PD spatial reuse, the received signal strength level 2191 should be measured from the L-STF or L-LTF (but not L-SIG), 2192 just as measured to indicate CCA. 2193 2194 Also, as per 802.11ax draft 3.3, for OBSS PD spatial reuse, 2195 MAC should compare this value with its programmed OBSS_PDlevel 2196 scaled from 20 MHz to the Rx PPDU bandwidth. Since MAC 2197 does not do this scaling, PHY is instead expected to normalize 2198 the reported RSSI to 20 MHz. 2199 2200 Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, for 2201 SRP spatial reuse, the received power level should be measured 2202 from the L-STF or L-LTF (but not L-SIG) and normalized 2203 to 20 MHz. 2204 <legal all> 2205 */ 2206 2207 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 2208 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 2209 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 2210 #define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 2211 2212 2213 /* Description RSSI_FOR_TRIGGER_RESP 2214 2215 RSSI to be used by PDG for transmit (power) selection during 2216 trigger response, reported as an 8-bit signed value 2217 2218 The resolution can be: 2219 1dB or 0.5dB. This is statically configured within the PHY 2220 and MAC 2221 2222 In case of 1dB, the Range is: 2223 -128dB to 127dB 2224 2225 In case of 0.5dB, the Range is: 2226 -64dB to 63.5dB 2227 2228 As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for trigger 2229 response, the received power should be measured from the 2230 non-HE portion of the preamble of the PPDU containing the 2231 trigger, normalized to 20 MHz, averaged over the antennas 2232 over which the average pathloss is being computed. 2233 <legal all> 2234 */ 2235 2236 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 2237 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 2238 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 2239 #define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 2240 2241 2242 2243 #endif // PHYRX_RSSI_LEGACY 2244