1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 18 #define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_status_header.h" 23 #define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26 24 25 #define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13 26 27 28 struct reo_descriptor_threshold_reached_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_status_header status_header; 31 uint32_t threshold_index : 2, // [1:0] 32 reserved_2 : 30; // [31:2] 33 uint32_t link_descriptor_counter0 : 24, // [23:0] 34 reserved_3 : 8; // [31:24] 35 uint32_t link_descriptor_counter1 : 24, // [23:0] 36 reserved_4 : 8; // [31:24] 37 uint32_t link_descriptor_counter2 : 24, // [23:0] 38 reserved_5 : 8; // [31:24] 39 uint32_t link_descriptor_counter_sum : 26, // [25:0] 40 reserved_6 : 6; // [31:26] 41 uint32_t reserved_7 : 32; // [31:0] 42 uint32_t reserved_8 : 32; // [31:0] 43 uint32_t reserved_9a : 32; // [31:0] 44 uint32_t reserved_10a : 32; // [31:0] 45 uint32_t reserved_11a : 32; // [31:0] 46 uint32_t reserved_12a : 32; // [31:0] 47 uint32_t reserved_13a : 32; // [31:0] 48 uint32_t reserved_14a : 32; // [31:0] 49 uint32_t reserved_15a : 32; // [31:0] 50 uint32_t reserved_16a : 32; // [31:0] 51 uint32_t reserved_17a : 32; // [31:0] 52 uint32_t reserved_18a : 32; // [31:0] 53 uint32_t reserved_19a : 32; // [31:0] 54 uint32_t reserved_20a : 32; // [31:0] 55 uint32_t reserved_21a : 32; // [31:0] 56 uint32_t reserved_22a : 32; // [31:0] 57 uint32_t reserved_23a : 32; // [31:0] 58 uint32_t reserved_24a : 32; // [31:0] 59 uint32_t reserved_25a : 28, // [27:0] 60 looping_count : 4; // [31:28] 61 #else 62 struct uniform_reo_status_header status_header; 63 uint32_t reserved_2 : 30, // [31:2] 64 threshold_index : 2; // [1:0] 65 uint32_t reserved_3 : 8, // [31:24] 66 link_descriptor_counter0 : 24; // [23:0] 67 uint32_t reserved_4 : 8, // [31:24] 68 link_descriptor_counter1 : 24; // [23:0] 69 uint32_t reserved_5 : 8, // [31:24] 70 link_descriptor_counter2 : 24; // [23:0] 71 uint32_t reserved_6 : 6, // [31:26] 72 link_descriptor_counter_sum : 26; // [25:0] 73 uint32_t reserved_7 : 32; // [31:0] 74 uint32_t reserved_8 : 32; // [31:0] 75 uint32_t reserved_9a : 32; // [31:0] 76 uint32_t reserved_10a : 32; // [31:0] 77 uint32_t reserved_11a : 32; // [31:0] 78 uint32_t reserved_12a : 32; // [31:0] 79 uint32_t reserved_13a : 32; // [31:0] 80 uint32_t reserved_14a : 32; // [31:0] 81 uint32_t reserved_15a : 32; // [31:0] 82 uint32_t reserved_16a : 32; // [31:0] 83 uint32_t reserved_17a : 32; // [31:0] 84 uint32_t reserved_18a : 32; // [31:0] 85 uint32_t reserved_19a : 32; // [31:0] 86 uint32_t reserved_20a : 32; // [31:0] 87 uint32_t reserved_21a : 32; // [31:0] 88 uint32_t reserved_22a : 32; // [31:0] 89 uint32_t reserved_23a : 32; // [31:0] 90 uint32_t reserved_24a : 32; // [31:0] 91 uint32_t looping_count : 4, // [31:28] 92 reserved_25a : 28; // [27:0] 93 #endif 94 }; 95 96 97 /* Description STATUS_HEADER 98 99 Consumer: SW 100 Producer: REO 101 102 Details that can link this status with the original command. 103 It also contains info on how long REO took to execute this 104 command. 105 */ 106 107 108 /* Description REO_STATUS_NUMBER 109 110 Consumer: SW , DEBUG 111 Producer: REO 112 113 The value in this field is equal to value of the 'REO_CMD_Number' 114 field the REO command 115 116 This field helps to correlate the statuses with the REO 117 commands. 118 119 <legal all> 120 */ 121 122 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 123 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 124 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 125 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 126 127 128 /* Description CMD_EXECUTION_TIME 129 130 Consumer: DEBUG 131 Producer: REO 132 133 The amount of time REO took to excecute the command. Note 134 that this time does not include the duration of the command 135 waiting in the command ring, before the execution started. 136 137 138 In us. 139 140 <legal all> 141 */ 142 143 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 144 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 145 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 146 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 147 148 149 /* Description REO_CMD_EXECUTION_STATUS 150 151 Consumer: DEBUG 152 Producer: REO 153 154 Execution status of the command. 155 156 <enum 0 reo_successful_execution> Command has successfully 157 be executed 158 <enum 1 reo_blocked_execution> Command could not be executed 159 as the queue or cache was blocked 160 <enum 2 reo_failed_execution> Command has encountered problems 161 when executing, like the queue descriptor not being valid. 162 None of the status fields in the entire STATUS TLV are valid. 163 164 <enum 3 reo_resource_blocked> Command is NOT executed because 165 one or more descriptors were blocked. This is SW programming 166 mistake. 167 None of the status fields in the entire STATUS TLV are valid. 168 169 170 <legal 0-3> 171 */ 172 173 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 174 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 175 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 176 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 177 178 179 /* Description RESERVED_0A 180 181 <legal 0> 182 */ 183 184 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 185 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 186 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 187 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 188 189 190 /* Description TIMESTAMP 191 192 Timestamp at the moment that this status report is written. 193 194 195 <legal all> 196 */ 197 198 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 199 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 200 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 201 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 202 203 204 /* Description THRESHOLD_INDEX 205 206 The index of the threshold register whose value got reached 207 208 209 <enum 0 reo_desc_counter0_threshold> 210 <enum 1 reo_desc_counter1_threshold> 211 <enum 2 reo_desc_counter2_threshold> 212 <enum 3 reo_desc_counter_sum_threshold> 213 214 <legal all> 215 */ 216 217 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008 218 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 219 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 220 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003 221 222 223 /* Description RESERVED_2 224 225 <legal 0> 226 */ 227 228 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008 229 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 230 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 231 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc 232 233 234 /* Description LINK_DESCRIPTOR_COUNTER0 235 236 Value of this counter at generation of this message 237 <legal all> 238 */ 239 240 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008 241 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32 242 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55 243 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000 244 245 246 /* Description RESERVED_3 247 248 <legal 0> 249 */ 250 251 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008 252 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56 253 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63 254 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000 255 256 257 /* Description LINK_DESCRIPTOR_COUNTER1 258 259 Value of this counter at generation of this message 260 <legal all> 261 */ 262 263 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010 264 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 265 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 266 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff 267 268 269 /* Description RESERVED_4 270 271 <legal 0> 272 */ 273 274 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010 275 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 276 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 277 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000 278 279 280 /* Description LINK_DESCRIPTOR_COUNTER2 281 282 Value of this counter at generation of this message 283 <legal all> 284 */ 285 286 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010 287 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32 288 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55 289 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000 290 291 292 /* Description RESERVED_5 293 294 <legal 0> 295 */ 296 297 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010 298 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56 299 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63 300 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000 301 302 303 /* Description LINK_DESCRIPTOR_COUNTER_SUM 304 305 Value of this counter at generation of this message 306 <legal all> 307 */ 308 309 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018 310 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 311 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 312 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff 313 314 315 /* Description RESERVED_6 316 317 <legal 0> 318 */ 319 320 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018 321 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 322 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 323 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000 324 325 326 /* Description RESERVED_7 327 328 <legal 0> 329 */ 330 331 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018 332 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32 333 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63 334 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000 335 336 337 /* Description RESERVED_8 338 339 <legal 0> 340 */ 341 342 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020 343 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 344 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 345 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff 346 347 348 /* Description RESERVED_9A 349 350 <legal 0> 351 */ 352 353 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 354 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32 355 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63 356 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000 357 358 359 /* Description RESERVED_10A 360 361 <legal 0> 362 */ 363 364 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 365 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 366 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 367 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 368 369 370 /* Description RESERVED_11A 371 372 <legal 0> 373 */ 374 375 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 376 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32 377 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63 378 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000 379 380 381 /* Description RESERVED_12A 382 383 <legal 0> 384 */ 385 386 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 387 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 388 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 389 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 390 391 392 /* Description RESERVED_13A 393 394 <legal 0> 395 */ 396 397 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 398 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32 399 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63 400 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000 401 402 403 /* Description RESERVED_14A 404 405 <legal 0> 406 */ 407 408 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 409 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 410 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 411 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 412 413 414 /* Description RESERVED_15A 415 416 <legal 0> 417 */ 418 419 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 420 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32 421 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63 422 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000 423 424 425 /* Description RESERVED_16A 426 427 <legal 0> 428 */ 429 430 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 431 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 432 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 433 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 434 435 436 /* Description RESERVED_17A 437 438 <legal 0> 439 */ 440 441 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 442 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32 443 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63 444 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000 445 446 447 /* Description RESERVED_18A 448 449 <legal 0> 450 */ 451 452 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 453 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 454 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 455 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 456 457 458 /* Description RESERVED_19A 459 460 <legal 0> 461 */ 462 463 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 464 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32 465 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63 466 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000 467 468 469 /* Description RESERVED_20A 470 471 <legal 0> 472 */ 473 474 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 475 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 476 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 477 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 478 479 480 /* Description RESERVED_21A 481 482 <legal 0> 483 */ 484 485 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 486 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32 487 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63 488 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000 489 490 491 /* Description RESERVED_22A 492 493 <legal 0> 494 */ 495 496 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 497 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 498 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 499 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 500 501 502 /* Description RESERVED_23A 503 504 <legal 0> 505 */ 506 507 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 508 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32 509 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63 510 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000 511 512 513 /* Description RESERVED_24A 514 515 <legal 0> 516 */ 517 518 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 519 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 520 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 521 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 522 523 524 /* Description RESERVED_25A 525 526 <legal 0> 527 */ 528 529 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 530 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32 531 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59 532 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 533 534 535 /* Description LOOPING_COUNT 536 537 A count value that indicates the number of times the producer 538 of entries into this Ring has looped around the ring. 539 At initialization time, this value is set to 0. On the first 540 loop, this value is set to 1. After the max value is reached 541 allowed by the number of bits for this field, the count 542 value continues with 0 again. 543 544 In case SW is the consumer of the ring entries, it can use 545 this field to figure out up to where the producer of entries 546 has created new entries. This eliminates the need to check 547 where the "head pointer' of the ring is located once the 548 SW starts processing an interrupt indicating that new entries 549 have been put into this ring... 550 551 Also note that SW if it wants only needs to look at the 552 LSB bit of this count value. 553 <legal all> 554 */ 555 556 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 557 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60 558 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63 559 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 560 561 562 563 #endif // REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 564