1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_DESTINATION_RING_H_ 18 #define _REO_DESTINATION_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_msdu_desc_info.h" 23 #include "rx_mpdu_desc_info.h" 24 #include "buffer_addr_info.h" 25 #define NUM_OF_DWORDS_REO_DESTINATION_RING 8 26 27 28 struct reo_destination_ring { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct buffer_addr_info buf_or_link_desc_addr_info; 31 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 32 struct rx_msdu_desc_info rx_msdu_desc_info_details; 33 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 34 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 35 uint32_t reo_dest_buffer_type : 1, // [0:0] 36 reo_push_reason : 2, // [2:1] 37 reo_error_code : 5, // [7:3] 38 captured_msdu_data_size : 4, // [11:8] 39 sw_exception : 1, // [12:12] 40 src_link_id : 3, // [15:13] 41 reo_destination_struct_signature : 4, // [19:16] 42 ring_id : 8, // [27:20] 43 looping_count : 4; // [31:28] 44 #else 45 struct buffer_addr_info buf_or_link_desc_addr_info; 46 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 47 struct rx_msdu_desc_info rx_msdu_desc_info_details; 48 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 49 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 50 uint32_t looping_count : 4, // [31:28] 51 ring_id : 8, // [27:20] 52 reo_destination_struct_signature : 4, // [19:16] 53 src_link_id : 3, // [15:13] 54 sw_exception : 1, // [12:12] 55 captured_msdu_data_size : 4, // [11:8] 56 reo_error_code : 5, // [7:3] 57 reo_push_reason : 2, // [2:1] 58 reo_dest_buffer_type : 1; // [0:0] 59 #endif 60 }; 61 62 63 /* Description BUF_OR_LINK_DESC_ADDR_INFO 64 65 Consumer: REO/SW/FW 66 Producer: RXDMA 67 68 Details of the physical address of the a buffer or MSDU 69 link descriptor 70 */ 71 72 73 /* Description BUFFER_ADDR_31_0 74 75 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 76 descriptor OR Link Descriptor 77 78 In case of 'NULL' pointer, this field is set to 0 79 <legal all> 80 */ 81 82 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 83 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 84 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 85 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 86 87 88 /* Description BUFFER_ADDR_39_32 89 90 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 91 descriptor OR Link Descriptor 92 93 In case of 'NULL' pointer, this field is set to 0 94 <legal all> 95 */ 96 97 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 98 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 99 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 100 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 101 102 103 /* Description RETURN_BUFFER_MANAGER 104 105 Consumer: WBM 106 Producer: SW/FW 107 108 In case of 'NULL' pointer, this field is set to 0 109 110 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 111 descriptor OR link descriptor that is being pointed to 112 shall be returned after the frame has been processed. It 113 is used by WBM for routing purposes. 114 115 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 116 to the WMB buffer idle list 117 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 118 to the WBM idle link descriptor idle list, where the chip 119 0 WBM is chosen in case of a multi-chip config 120 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 121 to the chip 1 WBM idle link descriptor idle list 122 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 123 to the chip 2 WBM idle link descriptor idle list 124 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 125 returned to chip 3 WBM idle link descriptor idle list 126 <enum 4 FW_BM> This buffer shall be returned to the FW 127 <enum 5 SW0_BM> This buffer shall be returned to the SW, 128 ring 0 129 <enum 6 SW1_BM> This buffer shall be returned to the SW, 130 ring 1 131 <enum 7 SW2_BM> This buffer shall be returned to the SW, 132 ring 2 133 <enum 8 SW3_BM> This buffer shall be returned to the SW, 134 ring 3 135 <enum 9 SW4_BM> This buffer shall be returned to the SW, 136 ring 4 137 <enum 10 SW5_BM> This buffer shall be returned to the SW, 138 ring 5 139 <enum 11 SW6_BM> This buffer shall be returned to the SW, 140 ring 6 141 142 <legal 0-12> 143 */ 144 145 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 146 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 147 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 148 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 149 150 151 /* Description SW_BUFFER_COOKIE 152 153 Cookie field exclusively used by SW. 154 155 In case of 'NULL' pointer, this field is set to 0 156 157 HW ignores the contents, accept that it passes the programmed 158 value on to other descriptors together with the physical 159 address 160 161 Field can be used by SW to for example associate the buffers 162 physical address with the virtual address 163 The bit definitions as used by SW are within SW HLD specification 164 165 166 NOTE1: 167 The three most significant bits can have a special meaning 168 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 169 and field transmit_bw_restriction is set 170 171 In case of NON punctured transmission: 172 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 173 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 174 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 175 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 176 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 177 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 178 Sw_buffer_cookie[19:18] = 2'b11: reserved 179 180 In case of punctured transmission: 181 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 182 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 183 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 184 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 185 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 186 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 187 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 188 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 189 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 190 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 191 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 192 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 193 Sw_buffer_cookie[19:18] = 2'b11: reserved 194 195 Note: a punctured transmission is indicated by the presence 196 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 197 198 <legal all> 199 */ 200 201 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 202 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 203 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 204 #define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 205 206 207 /* Description RX_MPDU_DESC_INFO_DETAILS 208 209 Consumer: REO/SW/FW 210 Producer: RXDMA 211 212 General information related to the MPDU that is passed on 213 from REO entrance ring to the REO destination ring 214 215 When enabled in REO, REO will overwrite this structure to 216 have only the 'Msdu_count' field and 56 bits of the previous 217 PN from 'RX_REO_QUEUE' 218 */ 219 220 221 /* Description MSDU_COUNT 222 223 Consumer: REO/SW/FW 224 Producer: RXDMA 225 226 The number of MSDUs within the MPDU 227 <legal all> 228 */ 229 230 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 231 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 232 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 233 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 234 235 236 /* Description FRAGMENT_FLAG 237 238 Consumer: REO/SW/FW 239 Producer: RXDMA 240 241 When set, this MPDU is a fragment and REO should forward 242 this fragment MPDU to the REO destination ring without 243 any reorder checks, pn checks or bitmap update. This implies 244 that REO is forwarding the pointer to the MSDU link descriptor. 245 The destination ring is coming from a programmable register 246 setting in REO 247 248 <legal all> 249 */ 250 251 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 252 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 253 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 254 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 255 256 257 /* Description MPDU_RETRY_BIT 258 259 Consumer: REO/SW/FW 260 Producer: RXDMA 261 262 The retry bit setting from the MPDU header of the received 263 frame 264 <legal all> 265 */ 266 267 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 268 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 269 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 270 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 271 272 273 /* Description AMPDU_FLAG 274 275 Consumer: REO/SW/FW 276 Producer: RXDMA 277 278 When set, the MPDU was received as part of an A-MPDU. 279 <legal all> 280 */ 281 282 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 283 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 284 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 285 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 286 287 288 /* Description BAR_FRAME 289 290 Consumer: REO/SW/FW 291 Producer: RXDMA 292 293 When set, the received frame is a BAR frame. After processing, 294 this frame shall be pushed to SW or deleted. 295 <legal all> 296 */ 297 298 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 299 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 300 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 301 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 302 303 304 /* Description PN_FIELDS_CONTAIN_VALID_INFO 305 306 Consumer: REO/SW/FW 307 Producer: RXDMA 308 309 Copied here by RXDMA from RX_MPDU_END 310 When not set, REO will Not perform a PN sequence number 311 check 312 */ 313 314 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 315 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 316 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 317 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 318 319 320 /* Description RAW_MPDU 321 322 Field only valid when first_msdu_in_mpdu_flag is set. 323 324 When set, the contents in the MSDU buffer contains a 'RAW' 325 MPDU. This 'RAW' MPDU might be spread out over multiple 326 MSDU buffers. 327 <legal all> 328 */ 329 330 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 331 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 332 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 333 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 334 335 336 /* Description MORE_FRAGMENT_FLAG 337 338 The More Fragment bit setting from the MPDU header of the 339 received frame 340 341 <legal all> 342 */ 343 344 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 345 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 346 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 347 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 348 349 350 /* Description SRC_INFO 351 352 Source (virtual) device/interface info. associated with 353 this peer 354 355 This field gets passed on by REO to PPE in the EDMA descriptor 356 ('REO_TO_PPE_RING'). 357 358 <legal all> 359 */ 360 361 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 362 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 363 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 364 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 365 366 367 /* Description MPDU_QOS_CONTROL_VALID 368 369 When set, the MPDU has a QoS control field. 370 371 In case of ndp or phy_err, this field will never be set. 372 373 <legal all> 374 */ 375 376 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 377 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 378 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 379 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 380 381 382 /* Description TID 383 384 Field only valid when mpdu_qos_control_valid is set 385 386 The TID field in the QoS control field 387 <legal all> 388 */ 389 390 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 391 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 392 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 393 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 394 395 396 /* Description PEER_META_DATA 397 398 Meta data that SW has programmed in the Peer table entry 399 of the transmitting STA. 400 <legal all> 401 */ 402 403 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 404 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 405 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 406 #define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 407 408 409 /* Description RX_MSDU_DESC_INFO_DETAILS 410 411 General information related to the MSDU that is passed on 412 from RXDMA all the way to to the REO destination ring. 413 */ 414 415 416 /* Description FIRST_MSDU_IN_MPDU_FLAG 417 418 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 419 multiple buffers, this field will be valid in the Last 420 buffer used by the MSDU 421 422 <enum 0 Not_first_msdu> This is not the first MSDU in the 423 MPDU. 424 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 425 426 427 <legal all> 428 */ 429 430 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 431 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 432 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 433 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 434 435 436 /* Description LAST_MSDU_IN_MPDU_FLAG 437 438 Consumer: WBM/REO/SW/FW 439 Producer: RXDMA 440 441 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 442 multiple buffers, this field will be valid in the Last 443 buffer used by the MSDU 444 445 <enum 0 Not_last_msdu> There are more MSDUs linked to this 446 MSDU that belongs to this MPDU 447 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 448 This setting is only allowed in combination with 'Msdu_continuation' 449 set to 0. This implies that when an msdu is spread out over 450 multiple buffers and thus msdu_continuation is set, only 451 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 452 be set. 453 454 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 455 are set, the MPDU that this MSDU belongs to only contains 456 a single MSDU. 457 458 459 <legal all> 460 */ 461 462 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 463 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 464 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 465 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 466 467 468 /* Description MSDU_CONTINUATION 469 470 When set, this MSDU buffer was not able to hold the entire 471 MSDU. The next buffer will therefor contain additional 472 information related to this MSDU. 473 474 <legal all> 475 */ 476 477 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 478 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 479 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 480 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 481 482 483 /* Description MSDU_LENGTH 484 485 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 486 multiple buffers, this field will be valid in the First 487 buffer used by MSDU. 488 489 Full MSDU length in bytes after decapsulation. 490 491 This field is still valid for MPDU frames without A-MSDU. 492 It still represents MSDU length after decapsulation 493 494 Or in case of RAW MPDUs, it indicates the length of the 495 entire MPDU (without FCS field) 496 <legal all> 497 */ 498 499 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 500 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 501 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 502 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 503 504 505 /* Description MSDU_DROP 506 507 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 508 multiple buffers, this field will be valid in the Last 509 buffer used by the MSDU 510 511 When set, REO shall drop this MSDU and not forward it to 512 any other ring... 513 <legal all> 514 */ 515 516 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 517 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 518 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 519 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 520 521 522 /* Description SA_IS_VALID 523 524 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 525 multiple buffers, this field will be valid in the Last 526 buffer used by the MSDU 527 528 Indicates that OLE found a valid SA entry for this MSDU 529 <legal all> 530 */ 531 532 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 533 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 534 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 535 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 536 537 538 /* Description DA_IS_VALID 539 540 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 541 multiple buffers, this field will be valid in the Last 542 buffer used by the MSDU 543 544 Indicates that OLE found a valid DA entry for this MSDU 545 <legal all> 546 */ 547 548 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 549 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 550 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 551 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 552 553 554 /* Description DA_IS_MCBC 555 556 Field Only valid if "da_is_valid" is set 557 558 Indicates the DA address was a Multicast of Broadcast address 559 for this MSDU 560 <legal all> 561 */ 562 563 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 564 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 565 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 566 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 567 568 569 /* Description L3_HEADER_PADDING_MSB 570 571 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 572 as the LSB is always zero) 573 Number of bytes padded to make sure that the L3 header will 574 always start of a Dword boundary 575 <legal all> 576 */ 577 578 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 579 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 580 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 581 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 582 583 584 /* Description TCP_UDP_CHKSUM_FAIL 585 586 Passed on from 'RX_ATTENTION' TLV 587 Indicates that the computed checksum did not match the checksum 588 in the TCP/UDP header. 589 <legal all> 590 */ 591 592 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 593 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 594 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 595 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 596 597 598 /* Description IP_CHKSUM_FAIL 599 600 Passed on from 'RX_ATTENTION' TLV 601 Indicates that the computed checksum did not match the checksum 602 in the IP header. 603 <legal all> 604 */ 605 606 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 607 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 608 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 609 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 610 611 612 /* Description FR_DS 613 614 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 615 TLV 616 Set if the 'from DS' bit is set in the frame control. 617 <legal all> 618 */ 619 620 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 621 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 622 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 623 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 624 625 626 /* Description TO_DS 627 628 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 629 TLV 630 Set if the 'to DS' bit is set in the frame control. 631 <legal all> 632 */ 633 634 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 635 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 636 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 637 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 638 639 640 /* Description INTRA_BSS 641 642 This packet needs intra-BSS routing by SW as the 'vdev_id' 643 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 644 that this MSDU was got in. 645 646 <legal all> 647 */ 648 649 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 650 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 651 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 652 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 653 654 655 /* Description DEST_CHIP_ID 656 657 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 658 to support intra-BSS routing with multi-chip multi-link 659 operation. 660 661 This indicates into which chip's TCL the packet should be 662 queued. 663 664 <legal all> 665 */ 666 667 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 668 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 669 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 670 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 671 672 673 /* Description DECAP_FORMAT 674 675 Indicates the format after decapsulation: 676 677 <enum 0 RAW> No encapsulation 678 <enum 1 Native_WiFi> 679 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 680 681 <enum 3 802_3> Indicate Ethernet 682 683 <legal all> 684 */ 685 686 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 687 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 688 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 689 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 690 691 692 /* Description DEST_CHIP_PMAC_ID 693 694 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 695 to support intra-BSS routing with multi-chip multi-link 696 operation. 697 698 This indicates into which link/'vdev' the packet should 699 be queued in TCL. 700 701 <legal all> 702 */ 703 704 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000010 705 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 706 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 707 #define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 708 709 710 /* Description BUFFER_VIRT_ADDR_31_0 711 712 Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address 713 714 715 Lower 32 bits of the 64-bit virtual address corresponding 716 to Buf_or_link_desc_addr_info 717 <legal all> 718 */ 719 720 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 721 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 722 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 723 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 724 725 726 /* Description BUFFER_VIRT_ADDR_63_32 727 728 Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address 729 730 731 Upper 32 bits of the 64-bit virtual address corresponding 732 to Buf_or_link_desc_addr_info 733 <legal all> 734 */ 735 736 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 737 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 738 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 739 #define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 740 741 742 /* Description REO_DEST_BUFFER_TYPE 743 744 Indicates the type of address provided in the 'Buf_or_link_desc_addr_info' 745 746 747 <enum 0 MSDU_buf_address> The address of an MSDU buffer 748 <enum 1 MSDU_link_desc_address> The address of the MSDU 749 link descriptor. 750 751 <legal all> 752 */ 753 754 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 755 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 756 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 757 #define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 758 759 760 /* Description REO_PUSH_REASON 761 762 Indicates why REO pushed the frame to this exit ring 763 764 <enum 0 reo_error_detected> Reo detected an error an pushed 765 this frame to this queue 766 <enum 1 reo_routing_instruction> Reo pushed the frame to 767 this queue per received routing instructions. No error 768 within REO was detected 769 770 771 <legal 0 - 1> 772 */ 773 774 #define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c 775 #define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 776 #define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 777 #define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 778 779 780 /* Description REO_ERROR_CODE 781 782 Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. 783 784 785 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided 786 in the REO_ENTRANCE ring is set to 0 787 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid 788 bit is NOT set 789 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 790 session having been setup. 791 <enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN, 792 Retry bit set: duplicate frame 793 <enum 4 ba_duplicate> BA session, duplicate frame 794 <enum 5 regular_frame_2k_jump> A normal (management/data 795 frame) received with 2K jump in SN 796 <enum 6 bar_frame_2k_jump> A bar received with 2K jump in 797 SSN 798 <enum 7 regular_frame_OOR> A normal (management/data frame) 799 received with SN falling within the OOR window 800 <enum 8 bar_frame_OOR> A bar received with SSN falling within 801 the OOR window 802 <enum 9 bar_frame_no_ba_session> A bar received without 803 a BA session 804 <enum 10 bar_frame_sn_equals_ssn> A bar received with SSN 805 equal to SN 806 <enum 11 pn_check_failed> PN Check Failed packet. 807 <enum 12 2k_error_handling_flag_set> Frame is forwarded 808 as a result of the 'Seq_2k_error_detected_flag' been set 809 in the REO Queue descriptor 810 <enum 13 pn_error_handling_flag_set> Frame is forwarded 811 as a result of the 'pn_error_detected_flag' been set in 812 the REO Queue descriptor 813 <enum 14 queue_descriptor_blocked_set> Frame is forwarded 814 as a result of the queue descriptor(address) being blocked 815 as SW/FW seems to be currently in the process of making 816 updates to this descriptor... 817 818 <legal 0-14> 819 */ 820 821 #define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c 822 #define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 823 #define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 824 #define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 825 826 827 /* Description CAPTURED_MSDU_DATA_SIZE 828 829 The number of following REO_DESTINATION STRUCTs that have 830 been replaced with msdu_data extracted from the msdu_buffer 831 and copied into the ring for easy FW/SW access. 832 Note that it is possible that these STRUCTs wrap around 833 the end of the ring. 834 <legal 0-4> 835 */ 836 837 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c 838 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 839 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 840 #define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 841 842 843 /* Description SW_EXCEPTION 844 845 This field has the same setting as the SW_exception field 846 in the corresponding REO_entrance_ring descriptor. 847 When set, the REO entrance descriptor is generated by FW, 848 and the MPDU was processed in the following way: 849 - NO re-order function is needed. 850 - MPDU delinking is determined by the setting of Entrance 851 ring field: SW_excection_mpdu_delink 852 - Destination ring selection is based on the setting of 853 the Entrance ring field SW_exception_destination _ring_valid 854 855 <legal all> 856 */ 857 858 #define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c 859 #define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 860 #define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 861 #define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 862 863 864 /* Description SRC_LINK_ID 865 866 Consumer: SW 867 Producer: RXDMA 868 869 Set to the link ID of the PMAC that received the frame 870 <legal all> 871 */ 872 873 #define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c 874 #define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 875 #define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 876 #define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 877 878 879 /* Description REO_DESTINATION_STRUCT_SIGNATURE 880 881 Set to value 0x8 when msdu capture mode is enabled for this 882 ring <legal 0, 8 > 883 */ 884 885 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c 886 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 887 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 888 #define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 889 890 891 /* Description RING_ID 892 893 The buffer pointer ring ID. 894 0 refers to the IDLE ring 895 1 - N refers to other rings 896 897 Helps with debugging when dumping ring contents. 898 899 This can be used in conjunction with the Reo_destination_struct_signature. 900 901 902 For debugging, if enabled, REO may fill the Rx MPDU sequence 903 number in {Looping_count, ring_id}. 904 905 <legal all> 906 */ 907 908 #define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c 909 #define REO_DESTINATION_RING_RING_ID_LSB 20 910 #define REO_DESTINATION_RING_RING_ID_MSB 27 911 #define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 912 913 914 /* Description LOOPING_COUNT 915 916 A count value that indicates the number of times the producer 917 of entries into this Ring has looped around the ring. 918 At initialization time, this value is set to 0. On the first 919 loop, this value is set to 1. After the max value is reached 920 allowed by the number of bits for this field, the count 921 value continues with 0 again. 922 In case SW is the consumer of the ring entries, it can use 923 this field to figure out up to where the producer of entries 924 has created new entries. This eliminates the need to check 925 where the "head pointer' of the ring is located once the 926 SW starts processing an interrupt indicating that new entries 927 have been put into this ring... 928 929 Also note that SW if it wants only needs to look at the 930 LSB bit of this count value. 931 932 For debugging, if enabled, REO may fill the Rx MPDU sequence 933 number in {Looping_count, ring_id}. 934 935 <legal all> 936 */ 937 938 #define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c 939 #define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 940 #define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 941 #define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 942 943 944 945 #endif // REO_DESTINATION_RING 946