1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_ENTRANCE_RING_H_ 18 #define _REO_ENTRANCE_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_details.h" 23 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 24 25 26 struct reo_entrance_ring { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct rx_mpdu_details reo_level_mpdu_frame_info; 29 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 30 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 31 rounded_mpdu_byte_count : 14, // [21:8] 32 reo_destination_indication : 5, // [26:22] 33 frameless_bar : 1, // [27:27] 34 reserved_5a : 4; // [31:28] 35 uint32_t rxdma_push_reason : 2, // [1:0] 36 rxdma_error_code : 5, // [6:2] 37 mpdu_fragment_number : 4, // [10:7] 38 sw_exception : 1, // [11:11] 39 sw_exception_mpdu_delink : 1, // [12:12] 40 sw_exception_destination_ring_valid : 1, // [13:13] 41 sw_exception_destination_ring : 5, // [18:14] 42 mpdu_sequence_number : 12, // [30:19] 43 reserved_6a : 1; // [31:31] 44 uint32_t phy_ppdu_id : 16, // [15:0] 45 src_link_id : 3, // [18:16] 46 reserved_7a : 1, // [19:19] 47 ring_id : 8, // [27:20] 48 looping_count : 4; // [31:28] 49 #else 50 struct rx_mpdu_details reo_level_mpdu_frame_info; 51 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 52 uint32_t reserved_5a : 4, // [31:28] 53 frameless_bar : 1, // [27:27] 54 reo_destination_indication : 5, // [26:22] 55 rounded_mpdu_byte_count : 14, // [21:8] 56 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 57 uint32_t reserved_6a : 1, // [31:31] 58 mpdu_sequence_number : 12, // [30:19] 59 sw_exception_destination_ring : 5, // [18:14] 60 sw_exception_destination_ring_valid : 1, // [13:13] 61 sw_exception_mpdu_delink : 1, // [12:12] 62 sw_exception : 1, // [11:11] 63 mpdu_fragment_number : 4, // [10:7] 64 rxdma_error_code : 5, // [6:2] 65 rxdma_push_reason : 2; // [1:0] 66 uint32_t looping_count : 4, // [31:28] 67 ring_id : 8, // [27:20] 68 reserved_7a : 1, // [19:19] 69 src_link_id : 3, // [18:16] 70 phy_ppdu_id : 16; // [15:0] 71 #endif 72 }; 73 74 75 /* Description REO_LEVEL_MPDU_FRAME_INFO 76 77 Consumer: REO 78 Producer: RXDMA 79 80 Details related to the MPDU being pushed into the REO 81 */ 82 83 84 /* Description MSDU_LINK_DESC_ADDR_INFO 85 86 Consumer: REO/SW/FW 87 Producer: RXDMA 88 89 Details of the physical address of the MSDU link descriptor 90 that contains pointers to MSDUs related to this MPDU 91 */ 92 93 94 /* Description BUFFER_ADDR_31_0 95 96 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 97 descriptor OR Link Descriptor 98 99 In case of 'NULL' pointer, this field is set to 0 100 <legal all> 101 */ 102 103 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 104 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 105 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 106 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 107 108 109 /* Description BUFFER_ADDR_39_32 110 111 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 112 descriptor OR Link Descriptor 113 114 In case of 'NULL' pointer, this field is set to 0 115 <legal all> 116 */ 117 118 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 119 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 120 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 121 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 122 123 124 /* Description RETURN_BUFFER_MANAGER 125 126 Consumer: WBM 127 Producer: SW/FW 128 129 In case of 'NULL' pointer, this field is set to 0 130 131 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 132 descriptor OR link descriptor that is being pointed to 133 shall be returned after the frame has been processed. It 134 is used by WBM for routing purposes. 135 136 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 137 to the WMB buffer idle list 138 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 139 to the WBM idle link descriptor idle list, where the chip 140 0 WBM is chosen in case of a multi-chip config 141 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 142 to the chip 1 WBM idle link descriptor idle list 143 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 144 to the chip 2 WBM idle link descriptor idle list 145 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 146 returned to chip 3 WBM idle link descriptor idle list 147 <enum 4 FW_BM> This buffer shall be returned to the FW 148 <enum 5 SW0_BM> This buffer shall be returned to the SW, 149 ring 0 150 <enum 6 SW1_BM> This buffer shall be returned to the SW, 151 ring 1 152 <enum 7 SW2_BM> This buffer shall be returned to the SW, 153 ring 2 154 <enum 8 SW3_BM> This buffer shall be returned to the SW, 155 ring 3 156 <enum 9 SW4_BM> This buffer shall be returned to the SW, 157 ring 4 158 <enum 10 SW5_BM> This buffer shall be returned to the SW, 159 ring 5 160 <enum 11 SW6_BM> This buffer shall be returned to the SW, 161 ring 6 162 163 <legal 0-12> 164 */ 165 166 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 167 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 168 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 169 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 170 171 172 /* Description SW_BUFFER_COOKIE 173 174 Cookie field exclusively used by SW. 175 176 In case of 'NULL' pointer, this field is set to 0 177 178 HW ignores the contents, accept that it passes the programmed 179 value on to other descriptors together with the physical 180 address 181 182 Field can be used by SW to for example associate the buffers 183 physical address with the virtual address 184 The bit definitions as used by SW are within SW HLD specification 185 186 187 NOTE1: 188 The three most significant bits can have a special meaning 189 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 190 and field transmit_bw_restriction is set 191 192 In case of NON punctured transmission: 193 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 194 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 195 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 196 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 197 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 198 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 199 Sw_buffer_cookie[19:18] = 2'b11: reserved 200 201 In case of punctured transmission: 202 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 203 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 204 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 205 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 206 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 207 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 208 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 209 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 210 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 211 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 212 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 213 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 214 Sw_buffer_cookie[19:18] = 2'b11: reserved 215 216 Note: a punctured transmission is indicated by the presence 217 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 218 219 <legal all> 220 */ 221 222 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 223 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 224 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 225 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 226 227 228 /* Description RX_MPDU_DESC_INFO_DETAILS 229 230 Consumer: REO/SW/FW 231 Producer: RXDMA 232 233 General information related to the MPDU that should be passed 234 on from REO entrance ring to the REO destination ring 235 */ 236 237 238 /* Description MSDU_COUNT 239 240 Consumer: REO/SW/FW 241 Producer: RXDMA 242 243 The number of MSDUs within the MPDU 244 <legal all> 245 */ 246 247 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 248 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 249 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 250 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 251 252 253 /* Description FRAGMENT_FLAG 254 255 Consumer: REO/SW/FW 256 Producer: RXDMA 257 258 When set, this MPDU is a fragment and REO should forward 259 this fragment MPDU to the REO destination ring without 260 any reorder checks, pn checks or bitmap update. This implies 261 that REO is forwarding the pointer to the MSDU link descriptor. 262 The destination ring is coming from a programmable register 263 setting in REO 264 265 <legal all> 266 */ 267 268 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 269 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 270 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 271 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 272 273 274 /* Description MPDU_RETRY_BIT 275 276 Consumer: REO/SW/FW 277 Producer: RXDMA 278 279 The retry bit setting from the MPDU header of the received 280 frame 281 <legal all> 282 */ 283 284 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 285 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 286 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 287 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 288 289 290 /* Description AMPDU_FLAG 291 292 Consumer: REO/SW/FW 293 Producer: RXDMA 294 295 When set, the MPDU was received as part of an A-MPDU. 296 <legal all> 297 */ 298 299 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 300 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 301 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 302 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 303 304 305 /* Description BAR_FRAME 306 307 Consumer: REO/SW/FW 308 Producer: RXDMA 309 310 When set, the received frame is a BAR frame. After processing, 311 this frame shall be pushed to SW or deleted. 312 <legal all> 313 */ 314 315 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 316 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 317 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 318 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 319 320 321 /* Description PN_FIELDS_CONTAIN_VALID_INFO 322 323 Consumer: REO/SW/FW 324 Producer: RXDMA 325 326 Copied here by RXDMA from RX_MPDU_END 327 When not set, REO will Not perform a PN sequence number 328 check 329 */ 330 331 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 332 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 333 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 334 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 335 336 337 /* Description RAW_MPDU 338 339 Field only valid when first_msdu_in_mpdu_flag is set. 340 341 When set, the contents in the MSDU buffer contains a 'RAW' 342 MPDU. This 'RAW' MPDU might be spread out over multiple 343 MSDU buffers. 344 <legal all> 345 */ 346 347 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 348 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 349 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 350 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 351 352 353 /* Description MORE_FRAGMENT_FLAG 354 355 The More Fragment bit setting from the MPDU header of the 356 received frame 357 358 <legal all> 359 */ 360 361 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 362 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 363 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 364 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 365 366 367 /* Description SRC_INFO 368 369 Source (virtual) device/interface info. associated with 370 this peer 371 372 This field gets passed on by REO to PPE in the EDMA descriptor 373 ('REO_TO_PPE_RING'). 374 375 <legal all> 376 */ 377 378 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 379 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 380 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 381 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 382 383 384 /* Description MPDU_QOS_CONTROL_VALID 385 386 When set, the MPDU has a QoS control field. 387 388 In case of ndp or phy_err, this field will never be set. 389 390 <legal all> 391 */ 392 393 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 394 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 395 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 396 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 397 398 399 /* Description TID 400 401 Field only valid when mpdu_qos_control_valid is set 402 403 The TID field in the QoS control field 404 <legal all> 405 */ 406 407 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 408 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 409 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 410 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 411 412 413 /* Description PEER_META_DATA 414 415 Meta data that SW has programmed in the Peer table entry 416 of the transmitting STA. 417 <legal all> 418 */ 419 420 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 421 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 422 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 423 #define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 424 425 426 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 427 428 Consumer: REO 429 Producer: RXDMA 430 431 Address (lower 32 bits) of the REO queue descriptor 432 433 Alternatively, REO internally looks up the 434 queue descriptor address from 'Sw_peer_id' and 'Tid.' In 435 this mode, RXDMA fills 'Sw_peer_id' from 'RX_MPDU_START' 436 in the LSB 16 bits. 'Tid' is available in 'RX_MPDU_DETAILS.' 437 438 <legal all> 439 */ 440 441 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 442 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 443 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 444 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 445 446 447 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 448 449 Consumer: REO 450 Producer: RXDMA 451 452 Address (upper 8 bits) of the REO queue descriptor 453 Alternatively, REO internally looks up the 454 queue descriptor address from 'Sw_peer_id' and 'Tid.' In 455 this mode, this field is unused. 456 <legal all> 457 */ 458 459 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 460 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 461 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 462 #define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 463 464 465 /* Description ROUNDED_MPDU_BYTE_COUNT 466 467 An approximation of the number of bytes received in this 468 MPDU. 469 Used to keeps stats on the amount of data flowing through 470 a queue. 471 <legal all> 472 */ 473 474 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 475 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 476 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 477 #define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 478 479 480 /* Description REO_DESTINATION_INDICATION 481 482 RXDMA copy the MPDU's first MSDU's destination indication 483 field here. This is used for REO to be able to re-route 484 the packet to a different SW destination ring if the packet 485 is detected as error in REO. 486 487 The ID of the REO exit ring where the MSDU frame shall push 488 after (MPDU level) reordering has finished. 489 490 <enum 0 reo_destination_sw0> Reo will push the frame into 491 the REO2SW0 ring 492 <enum 1 reo_destination_sw1> Reo will push the frame into 493 the REO2SW1 ring 494 <enum 2 reo_destination_sw2> Reo will push the frame into 495 the REO2SW2 ring 496 <enum 3 reo_destination_sw3> Reo will push the frame into 497 the REO2SW3 ring 498 <enum 4 reo_destination_sw4> Reo will push the frame into 499 the REO2SW4 ring 500 <enum 5 reo_destination_release> Reo will push the frame 501 into the REO_release ring 502 <enum 6 reo_destination_fw> Reo will push the frame into 503 the REO2FW ring 504 <enum 7 reo_destination_sw5> Reo will push the frame into 505 the REO2SW5 ring (REO remaps this in chips without REO2SW5 506 ring) 507 <enum 8 reo_destination_sw6> Reo will push the frame into 508 the REO2SW6 ring (REO remaps this in chips without REO2SW6 509 ring) 510 <enum 9 reo_destination_sw7> Reo will push the frame into 511 the REO2SW7 ring (REO remaps this in chips without REO2SW7 512 ring) 513 <enum 10 reo_destination_sw8> Reo will push the frame into 514 the REO2SW8 ring (REO remaps this in chips without REO2SW8 515 ring) 516 <enum 11 reo_destination_11> REO remaps this 517 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 518 REO remaps this 519 <enum 14 reo_destination_14> REO remaps this 520 <enum 15 reo_destination_15> REO remaps this 521 <enum 16 reo_destination_16> REO remaps this 522 <enum 17 reo_destination_17> REO remaps this 523 <enum 18 reo_destination_18> REO remaps this 524 <enum 19 reo_destination_19> REO remaps this 525 <enum 20 reo_destination_20> REO remaps this 526 <enum 21 reo_destination_21> REO remaps this 527 <enum 22 reo_destination_22> REO remaps this 528 <enum 23 reo_destination_23> REO remaps this 529 <enum 24 reo_destination_24> REO remaps this 530 <enum 25 reo_destination_25> REO remaps this 531 <enum 26 reo_destination_26> REO remaps this 532 <enum 27 reo_destination_27> REO remaps this 533 <enum 28 reo_destination_28> REO remaps this 534 <enum 29 reo_destination_29> REO remaps this 535 <enum 30 reo_destination_30> REO remaps this 536 <enum 31 reo_destination_31> REO remaps this 537 538 <legal all> 539 */ 540 541 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 542 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 543 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 544 #define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 545 546 547 /* Description FRAMELESS_BAR 548 549 When set, this REO entrance ring struct contains BAR info 550 from a multi TID BAR frame. The original multi TID BAR 551 frame itself contained all the REO info for the first TID, 552 but all the subsequent TID info and their linkage to the 553 REO descriptors is passed down as 'frameless' BAR info. 554 555 556 The only fields valid in this descriptor when this bit is 557 set are: 558 Rx_reo_queue_desc_addr_31_0 559 RX_reo_queue_desc_addr_39_32 560 561 And within the 562 Reo_level_mpdu_frame_info: 563 Within Rx_mpdu_desc_info_details: 564 Mpdu_Sequence_number 565 BAR_frame 566 Peer_meta_data 567 All other fields shall be set to 0 568 569 <legal all> 570 */ 571 572 #define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 573 #define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 574 #define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 575 #define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 576 577 578 /* Description RESERVED_5A 579 580 <legal 0> 581 */ 582 583 #define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 584 #define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 585 #define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 586 #define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 587 588 589 /* Description RXDMA_PUSH_REASON 590 591 Indicates why rxdma pushed the frame to this ring 592 593 This field is ignored by REO. 594 595 <enum 0 rxdma_error_detected> RXDMA detected an error an 596 pushed this frame to this queue 597 <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 598 to this queue per received routing instructions. No error 599 within RXDMA was detected 600 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 601 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 602 set, but instead WBM might just see a NULL pointer in the 603 MSDU link descriptor. This is to be considered a normal 604 condition for this scenario. 605 606 <legal 0 - 2> 607 */ 608 609 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 610 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 611 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 612 #define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 613 614 615 /* Description RXDMA_ERROR_CODE 616 617 Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'. 618 619 620 This field is ignored by REO. 621 622 <enum 0 rxdma_overflow_err>MPDU frame is not complete due 623 to a FIFO overflow error in RXPCU. 624 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 625 due to receiving incomplete MPDU from the PHY 626 <enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed 627 628 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error 629 or CRYPTO received an encrypted frame, but did not get 630 a valid corresponding key id in the peer entry. 631 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error 632 633 <enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted 634 frame error when encrypted was expected 635 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length 636 error 637 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max number 638 of MSDUs allowed in an MPDU got exceeded 639 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error 640 641 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 642 parsing error 643 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 644 during SA search 645 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 646 during DA search 647 <enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout 648 during flow search 649 <enum 13 rxdma_flush_request>RXDMA received a flush request 650 651 <enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast 652 echo 653 <enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an 654 A-MSDU with either 'from DS = 0' with an SA mismatching 655 TA or 'to DS = 0' with a DA mismatching RA. 656 <enum 17 rxdma_unauthorized_wds_err>RX PCU reported that 657 Rx peer entry did not indicate 'authorized_to_send_WDS' 658 and also indicated 'from DS = to DS = 1.' 659 <enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported 660 a broadcast or multicast RA as well as either A-MSDU present 661 or 'from DS = to DS = 1.' 662 */ 663 664 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 665 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 666 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 667 #define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c 668 669 670 /* Description MPDU_FRAGMENT_NUMBER 671 672 Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag 673 is set. 674 675 The fragment number from the 802.11 header. 676 677 Note that the sequence number is embedded in the field: 678 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number 679 680 681 <legal all> 682 */ 683 684 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 685 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 686 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 687 #define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 688 689 690 /* Description SW_EXCEPTION 691 692 When not set, REO is performing all its default MPDU processing 693 operations, 694 When set, this REO entrance descriptor is generated by FW, 695 and should be processed as an exception. This implies: 696 NO re-order function is needed. 697 MPDU delinking is determined by the setting of field SW_excection_mpdu_delink 698 699 Destination ring selection is based on the setting of the 700 field SW_exception_destination_ring_valid 701 In the destination ring descriptor set bit: SW_exception_entry 702 703 <legal all> 704 */ 705 706 #define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 707 #define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 708 #define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 709 #define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 710 711 712 /* Description SW_EXCEPTION_MPDU_DELINK 713 714 Field only valid when SW_exception is set. 715 1'b0: REO should NOT delink the MPDU, and thus pass this 716 MPDU on to the destination ring as is. This implies that 717 in the REO_DESTINATION_RING struct field Buf_or_link_desc_addr_info 718 should point to an MSDU link descriptor 719 1'b1: REO should perform the normal MPDU delink into MSDU 720 operations. 721 <legal all> 722 */ 723 724 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 725 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 726 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 727 #define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 728 729 730 /* Description SW_EXCEPTION_DESTINATION_RING_VALID 731 732 Field only valid when SW_exception is set. 733 1'b0: REO shall push the MPDU (or delinked MPDU based on 734 the setting of SW_exception_mpdu_delink) to the destination 735 ring according to field reo_destination_indication. 736 1'b1: REO shall push the MPDU (or delinked MPDU based on 737 the setting of SW_exception_mpdu_delink) to the destination 738 ring according to field SW_exception_destination_ring. 739 <legal all> 740 */ 741 742 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 743 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 744 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 745 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 746 747 748 /* Description SW_EXCEPTION_DESTINATION_RING 749 750 Field only valid when fields SW_exception and SW_exception_destination_ring_valid 751 are set. 752 The ID of the ring where REO shall push this frame. 753 <enum 0 reo_destination_sw0> Reo will push the frame into 754 the REO2SW0 ring 755 <enum 1 reo_destination_sw1> Reo will push the frame into 756 the REO2SW1 ring 757 <enum 2 reo_destination_sw2> Reo will push the frame into 758 the REO2SW1 ring 759 <enum 3 reo_destination_sw3> Reo will push the frame into 760 the REO2SW1 ring 761 <enum 4 reo_destination_sw4> Reo will push the frame into 762 the REO2SW1 ring 763 <enum 5 reo_destination_release> Reo will push the frame 764 into the REO_release ring 765 <enum 6 reo_destination_fw> Reo will push the frame into 766 the REO2FW ring 767 <enum 7 reo_destination_sw5> REO remaps this 768 <enum 8 reo_destination_sw6> REO remaps this 769 <enum 9 reo_destination_sw7> REO remaps this 770 <enum 10 reo_destination_sw8> REO remaps this 771 <enum 11 reo_destination_11> REO remaps this 772 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 773 REO remaps this 774 <enum 14 reo_destination_14> REO remaps this 775 <enum 15 reo_destination_15> REO remaps this 776 <enum 16 reo_destination_16> REO remaps this 777 <enum 17 reo_destination_17> REO remaps this 778 <enum 18 reo_destination_18> REO remaps this 779 <enum 19 reo_destination_19> REO remaps this 780 <enum 20 reo_destination_20> REO remaps this 781 <enum 21 reo_destination_21> REO remaps this 782 <enum 22 reo_destination_22> REO remaps this 783 <enum 23 reo_destination_23> REO remaps this 784 <enum 24 reo_destination_24> REO remaps this 785 <enum 25 reo_destination_25> REO remaps this 786 <enum 26 reo_destination_26> REO remaps this 787 <enum 27 reo_destination_27> REO remaps this 788 <enum 28 reo_destination_28> REO remaps this 789 <enum 29 reo_destination_29> REO remaps this 790 <enum 30 reo_destination_30> REO remaps this 791 <enum 31 reo_destination_31> REO remaps this 792 793 <legal all> 794 */ 795 796 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 797 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 798 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 799 #define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 800 801 802 /* Description MPDU_SEQUENCE_NUMBER 803 804 Consumer: REO/SW/FW 805 Producer: RXDMA 806 807 The field can have two different meanings based on the setting 808 of sub-field Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.BAR_frame: 809 810 811 'BAR_frame' is NOT set: 812 The MPDU sequence number of the received frame. 813 814 'BAR_frame' is set. 815 The MPDU Start sequence number from the BAR frame 816 <legal all> 817 */ 818 819 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 820 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 821 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 822 #define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 823 824 825 /* Description RESERVED_6A 826 827 Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 828 Mpdu_qos_control_valid is set 829 830 This indicates whether the 'Ack policy' field within the 831 QoS control field of the MPDU indicates 'no-Ack.' 832 <legal all> 833 */ 834 835 #define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 836 #define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 837 #define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 838 #define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 839 840 841 /* Description PHY_PPDU_ID 842 843 A PPDU counter value that PHY increments for every PPDU 844 received 845 The counter value wraps around. RXDMA can be configured 846 to copy this from the RX_PPDU_START TLV for every output 847 descriptor. 848 849 This field is ignored by REO. 850 851 <legal all> 852 */ 853 854 #define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c 855 #define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 856 #define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 857 #define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff 858 859 860 /* Description SRC_LINK_ID 861 862 Consumer: SW 863 Producer: RXDMA 864 865 Set to the link ID of the PMAC that received the frame 866 <legal all> 867 */ 868 869 #define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c 870 #define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 871 #define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 872 #define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 873 874 875 876 #define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c 877 #define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 878 #define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 879 #define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 880 881 882 /* Description RING_ID 883 884 Consumer: SW/REO/DEBUG 885 Producer: SRNG (of RXDMA) 886 887 For debugging. 888 This field is filled in by the SRNG module. 889 It help to identify the ring that is being looked <legal 890 all> 891 */ 892 893 #define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c 894 #define REO_ENTRANCE_RING_RING_ID_LSB 20 895 #define REO_ENTRANCE_RING_RING_ID_MSB 27 896 #define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 897 898 899 /* Description LOOPING_COUNT 900 901 Consumer: SW/REO/DEBUG 902 Producer: SRNG (of RXDMA) 903 904 For debugging. 905 This field is filled in by the SRNG module. 906 907 A count value that indicates the number of times the producer 908 of entries into this Ring has looped around the ring. 909 At initialization time, this value is set to 0. On the first 910 loop, this value is set to 1. After the max value is reached 911 allowed by the number of bits for this field, the count 912 value continues with 0 again. 913 914 In case SW is the consumer of the ring entries, it can use 915 this field to figure out up to where the producer of entries 916 has created new entries. This eliminates the need to check 917 where the "head pointer' of the ring is located once the 918 SW starts processing an interrupt indicating that new entries 919 have been put into this ring... 920 921 Also note that SW if it wants only needs to look at the 922 LSB bit of this count value. 923 <legal all> 924 */ 925 926 #define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c 927 #define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 928 #define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 929 #define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 930 931 932 933 #endif // REO_ENTRANCE_RING 934