xref: /wlan-driver/fw-api/hw/qcn6432/reo_flush_cache.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name /*
2*5113495bSYour Name  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name #ifndef _REO_FLUSH_CACHE_H_
18*5113495bSYour Name #define _REO_FLUSH_CACHE_H_
19*5113495bSYour Name #if !defined(__ASSEMBLER__)
20*5113495bSYour Name #endif
21*5113495bSYour Name 
22*5113495bSYour Name #include "uniform_reo_cmd_header.h"
23*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
24*5113495bSYour Name 
25*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
26*5113495bSYour Name 
27*5113495bSYour Name 
28*5113495bSYour Name struct reo_flush_cache {
29*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
30*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
31*5113495bSYour Name              uint32_t flush_addr_31_0                                         : 32; // [31:0]
32*5113495bSYour Name              uint32_t flush_addr_39_32                                        :  8, // [7:0]
33*5113495bSYour Name                       forward_all_mpdus_in_queue                              :  1, // [8:8]
34*5113495bSYour Name                       release_cache_block_index                               :  1, // [9:9]
35*5113495bSYour Name                       cache_block_resource_index                              :  2, // [11:10]
36*5113495bSYour Name                       flush_without_invalidate                                :  1, // [12:12]
37*5113495bSYour Name                       block_cache_usage_after_flush                           :  1, // [13:13]
38*5113495bSYour Name                       flush_entire_cache                                      :  1, // [14:14]
39*5113495bSYour Name                       flush_queue_1k_desc                                     :  1, // [15:15]
40*5113495bSYour Name                       reserved_2b                                             : 16; // [31:16]
41*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
42*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
43*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
44*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
45*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
46*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
47*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
48*5113495bSYour Name #else
49*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
50*5113495bSYour Name              uint32_t flush_addr_31_0                                         : 32; // [31:0]
51*5113495bSYour Name              uint32_t reserved_2b                                             : 16, // [31:16]
52*5113495bSYour Name                       flush_queue_1k_desc                                     :  1, // [15:15]
53*5113495bSYour Name                       flush_entire_cache                                      :  1, // [14:14]
54*5113495bSYour Name                       block_cache_usage_after_flush                           :  1, // [13:13]
55*5113495bSYour Name                       flush_without_invalidate                                :  1, // [12:12]
56*5113495bSYour Name                       cache_block_resource_index                              :  2, // [11:10]
57*5113495bSYour Name                       release_cache_block_index                               :  1, // [9:9]
58*5113495bSYour Name                       forward_all_mpdus_in_queue                              :  1, // [8:8]
59*5113495bSYour Name                       flush_addr_39_32                                        :  8; // [7:0]
60*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
61*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
62*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
63*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
64*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
65*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
66*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
67*5113495bSYour Name #endif
68*5113495bSYour Name };
69*5113495bSYour Name 
70*5113495bSYour Name 
71*5113495bSYour Name /* Description		CMD_HEADER
72*5113495bSYour Name 
73*5113495bSYour Name 			Consumer: REO
74*5113495bSYour Name 			Producer: SW
75*5113495bSYour Name 
76*5113495bSYour Name 			Details for command execution tracking purposes.
77*5113495bSYour Name */
78*5113495bSYour Name 
79*5113495bSYour Name 
80*5113495bSYour Name /* Description		REO_CMD_NUMBER
81*5113495bSYour Name 
82*5113495bSYour Name 			Consumer: REO/SW/DEBUG
83*5113495bSYour Name 			Producer: SW
84*5113495bSYour Name 
85*5113495bSYour Name 			This number can be used by SW to track, identify and link
86*5113495bSYour Name 			 the created commands with the command statusses
87*5113495bSYour Name 
88*5113495bSYour Name 
89*5113495bSYour Name 			<legal all>
90*5113495bSYour Name */
91*5113495bSYour Name 
92*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
93*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
94*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
95*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
96*5113495bSYour Name 
97*5113495bSYour Name 
98*5113495bSYour Name /* Description		REO_STATUS_REQUIRED
99*5113495bSYour Name 
100*5113495bSYour Name 			Consumer: REO
101*5113495bSYour Name 			Producer: SW
102*5113495bSYour Name 
103*5113495bSYour Name 			<enum 0 NoStatus> REO does not need to generate a status
104*5113495bSYour Name 			 TLV for the execution of this command
105*5113495bSYour Name 			<enum 1 StatusRequired> REO shall generate a status TLV
106*5113495bSYour Name 			for the execution of this command
107*5113495bSYour Name 
108*5113495bSYour Name 			<legal all>
109*5113495bSYour Name */
110*5113495bSYour Name 
111*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
112*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
113*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
114*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
115*5113495bSYour Name 
116*5113495bSYour Name 
117*5113495bSYour Name /* Description		RESERVED_0A
118*5113495bSYour Name 
119*5113495bSYour Name 			<legal 0>
120*5113495bSYour Name */
121*5113495bSYour Name 
122*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
123*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB                                  17
124*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB                                  31
125*5113495bSYour Name #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
126*5113495bSYour Name 
127*5113495bSYour Name 
128*5113495bSYour Name /* Description		FLUSH_ADDR_31_0
129*5113495bSYour Name 
130*5113495bSYour Name 			Consumer: REO
131*5113495bSYour Name 			Producer: SW
132*5113495bSYour Name 
133*5113495bSYour Name 			Address (lower 32 bits) of the descriptor to flush
134*5113495bSYour Name 			<legal all>
135*5113495bSYour Name */
136*5113495bSYour Name 
137*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET                                      0x0000000000000000
138*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB                                         32
139*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB                                         63
140*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK                                        0xffffffff00000000
141*5113495bSYour Name 
142*5113495bSYour Name 
143*5113495bSYour Name /* Description		FLUSH_ADDR_39_32
144*5113495bSYour Name 
145*5113495bSYour Name 			Consumer: REO
146*5113495bSYour Name 			Producer: SW
147*5113495bSYour Name 
148*5113495bSYour Name 			Address (upper 8 bits) of the descriptor to flush
149*5113495bSYour Name 			<legal all>
150*5113495bSYour Name */
151*5113495bSYour Name 
152*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET                                     0x0000000000000008
153*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB                                        0
154*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB                                        7
155*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK                                       0x00000000000000ff
156*5113495bSYour Name 
157*5113495bSYour Name 
158*5113495bSYour Name /* Description		FORWARD_ALL_MPDUS_IN_QUEUE
159*5113495bSYour Name 
160*5113495bSYour Name 			Is only allowed to be set when the flush address corresponds
161*5113495bSYour Name 			 with a REO descriptor.
162*5113495bSYour Name 
163*5113495bSYour Name 			When set, REO shall first forward all the MPDUs held in
164*5113495bSYour Name 			the indicated re-order queue, before flushing the descriptor
165*5113495bSYour Name 			 from the cache.
166*5113495bSYour Name 			<legal all>
167*5113495bSYour Name */
168*5113495bSYour Name 
169*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET                           0x0000000000000008
170*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB                              8
171*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB                              8
172*5113495bSYour Name #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK                             0x0000000000000100
173*5113495bSYour Name 
174*5113495bSYour Name 
175*5113495bSYour Name /* Description		RELEASE_CACHE_BLOCK_INDEX
176*5113495bSYour Name 
177*5113495bSYour Name 			Field not valid when Flush_entire_cache is set.
178*5113495bSYour Name 
179*5113495bSYour Name 			If SW has previously used a blocking resource that it now
180*5113495bSYour Name 			 wants to re-use for this command, this bit shall be set.
181*5113495bSYour Name 			It prevents SW from having to send a separate REO_UNBLOCK_CACHE
182*5113495bSYour Name 			 command.
183*5113495bSYour Name 
184*5113495bSYour Name 			When set, HW will first release the blocking resource (indicated
185*5113495bSYour Name 			 in field 'Cache_block_resouce_index') before this command
186*5113495bSYour Name 			 gets executed.
187*5113495bSYour Name 			If that resource was already unblocked, this will be considered
188*5113495bSYour Name 			 an error. This command will not be executed, and an error
189*5113495bSYour Name 			 shall be returned.
190*5113495bSYour Name 			<legal all>
191*5113495bSYour Name */
192*5113495bSYour Name 
193*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET                            0x0000000000000008
194*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB                               9
195*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB                               9
196*5113495bSYour Name #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK                              0x0000000000000200
197*5113495bSYour Name 
198*5113495bSYour Name 
199*5113495bSYour Name /* Description		CACHE_BLOCK_RESOURCE_INDEX
200*5113495bSYour Name 
201*5113495bSYour Name 			Field not valid when Flush_entire_cache is set.
202*5113495bSYour Name 
203*5113495bSYour Name 			Indicates which of the four blocking resources in REO will
204*5113495bSYour Name 			 be assigned for managing the blocking of this (descriptor)
205*5113495bSYour Name 			address
206*5113495bSYour Name 			<legal all>
207*5113495bSYour Name */
208*5113495bSYour Name 
209*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                           0x0000000000000008
210*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                              10
211*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                              11
212*5113495bSYour Name #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                             0x0000000000000c00
213*5113495bSYour Name 
214*5113495bSYour Name 
215*5113495bSYour Name /* Description		FLUSH_WITHOUT_INVALIDATE
216*5113495bSYour Name 
217*5113495bSYour Name 			Field not valid when Flush_entire_cache is set.
218*5113495bSYour Name 
219*5113495bSYour Name 			When set, REO shall flush the cache line contents from the
220*5113495bSYour Name 			 cache, but there is NO need to invalidate the cache line
221*5113495bSYour Name 			 entry... The contents in the cache can be maintained. This
222*5113495bSYour Name 			 feature can be used by SW (and DV) to get a current snapshot
223*5113495bSYour Name 			 of the contents in the cache
224*5113495bSYour Name 
225*5113495bSYour Name 			<legal all>
226*5113495bSYour Name */
227*5113495bSYour Name 
228*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET                             0x0000000000000008
229*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB                                12
230*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB                                12
231*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK                               0x0000000000001000
232*5113495bSYour Name 
233*5113495bSYour Name 
234*5113495bSYour Name /* Description		BLOCK_CACHE_USAGE_AFTER_FLUSH
235*5113495bSYour Name 
236*5113495bSYour Name 			Field not valid when Flush_entire_cache is set.
237*5113495bSYour Name 
238*5113495bSYour Name 			When set, REO shall block any cache accesses to this address
239*5113495bSYour Name 			 till explicitly unblocked.
240*5113495bSYour Name 
241*5113495bSYour Name 			Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue'
242*5113495bSYour Name 			to ensure all packets are flushed out in order to make sure
243*5113495bSYour Name 			 this queue desc is not in one of the aging link lists.
244*5113495bSYour Name 			In case SW does not want to flush the MPDUs in the queue,
245*5113495bSYour Name 			see the recipe description below this TLV definition.
246*5113495bSYour Name 
247*5113495bSYour Name 			The 'blocking' index to be used for this is indicated in
248*5113495bSYour Name 			 field 'cache_block_resource_index'. If SW had previously
249*5113495bSYour Name 			 used this blocking resource and was not freed up yet, SW
250*5113495bSYour Name 			 shall first unblock that index (by setting bit Release_cache_block_index)
251*5113495bSYour Name 			or use an unblock command.
252*5113495bSYour Name 
253*5113495bSYour Name 			If the resource indicated here was already blocked (and
254*5113495bSYour Name 			did not get unblocked in this command), it is considered
255*5113495bSYour Name 			 an error scenario...
256*5113495bSYour Name 			No flush shall happen. The status for this command shall
257*5113495bSYour Name 			 indicate error.
258*5113495bSYour Name 
259*5113495bSYour Name 			<legal all>
260*5113495bSYour Name */
261*5113495bSYour Name 
262*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET                        0x0000000000000008
263*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB                           13
264*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB                           13
265*5113495bSYour Name #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK                          0x0000000000002000
266*5113495bSYour Name 
267*5113495bSYour Name 
268*5113495bSYour Name /* Description		FLUSH_ENTIRE_CACHE
269*5113495bSYour Name 
270*5113495bSYour Name 			When set, the entire cache shall be flushed. The entire
271*5113495bSYour Name 			cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND'
272*5113495bSYour Name 			is received with bit unblock type set to unblock_cache.
273*5113495bSYour Name 			All other fields in this command are to be ignored.
274*5113495bSYour Name 
275*5113495bSYour Name 			Note that flushing the entire cache has no changes to the
276*5113495bSYour Name 			 current settings of the blocking resource settings
277*5113495bSYour Name 
278*5113495bSYour Name 			<legal all>
279*5113495bSYour Name */
280*5113495bSYour Name 
281*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET                                   0x0000000000000008
282*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB                                      14
283*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB                                      14
284*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK                                     0x0000000000004000
285*5113495bSYour Name 
286*5113495bSYour Name 
287*5113495bSYour Name /* Description		FLUSH_QUEUE_1K_DESC
288*5113495bSYour Name 
289*5113495bSYour Name 			When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor
290*5113495bSYour Name 			 after flushing the 'RX_REO_QUEUE' descriptor.
291*5113495bSYour Name 
292*5113495bSYour Name 			This bit shall only be set when the BA_window_size > 255
293*5113495bSYour Name 			 in 'RX_REO_QUEUE.'
294*5113495bSYour Name 			<legal all>
295*5113495bSYour Name */
296*5113495bSYour Name 
297*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET                                  0x0000000000000008
298*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB                                     15
299*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB                                     15
300*5113495bSYour Name #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK                                    0x0000000000008000
301*5113495bSYour Name 
302*5113495bSYour Name 
303*5113495bSYour Name /* Description		RESERVED_2B
304*5113495bSYour Name 
305*5113495bSYour Name 			<legal 0>
306*5113495bSYour Name */
307*5113495bSYour Name 
308*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET                                          0x0000000000000008
309*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_LSB                                             16
310*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_MSB                                             31
311*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_2B_MASK                                            0x00000000ffff0000
312*5113495bSYour Name 
313*5113495bSYour Name 
314*5113495bSYour Name /* Description		RESERVED_3A
315*5113495bSYour Name 
316*5113495bSYour Name 			<legal 0>
317*5113495bSYour Name */
318*5113495bSYour Name 
319*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET                                          0x0000000000000008
320*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_LSB                                             32
321*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_MSB                                             63
322*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_3A_MASK                                            0xffffffff00000000
323*5113495bSYour Name 
324*5113495bSYour Name 
325*5113495bSYour Name /* Description		RESERVED_4A
326*5113495bSYour Name 
327*5113495bSYour Name 			<legal 0>
328*5113495bSYour Name */
329*5113495bSYour Name 
330*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET                                          0x0000000000000010
331*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_LSB                                             0
332*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_MSB                                             31
333*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_4A_MASK                                            0x00000000ffffffff
334*5113495bSYour Name 
335*5113495bSYour Name 
336*5113495bSYour Name /* Description		RESERVED_5A
337*5113495bSYour Name 
338*5113495bSYour Name 			<legal 0>
339*5113495bSYour Name */
340*5113495bSYour Name 
341*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET                                          0x0000000000000010
342*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_LSB                                             32
343*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_MSB                                             63
344*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_5A_MASK                                            0xffffffff00000000
345*5113495bSYour Name 
346*5113495bSYour Name 
347*5113495bSYour Name /* Description		RESERVED_6A
348*5113495bSYour Name 
349*5113495bSYour Name 			<legal 0>
350*5113495bSYour Name */
351*5113495bSYour Name 
352*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET                                          0x0000000000000018
353*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_LSB                                             0
354*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_MSB                                             31
355*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_6A_MASK                                            0x00000000ffffffff
356*5113495bSYour Name 
357*5113495bSYour Name 
358*5113495bSYour Name /* Description		RESERVED_7A
359*5113495bSYour Name 
360*5113495bSYour Name 			<legal 0>
361*5113495bSYour Name */
362*5113495bSYour Name 
363*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET                                          0x0000000000000018
364*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_LSB                                             32
365*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_MSB                                             63
366*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_7A_MASK                                            0xffffffff00000000
367*5113495bSYour Name 
368*5113495bSYour Name 
369*5113495bSYour Name /* Description		RESERVED_8A
370*5113495bSYour Name 
371*5113495bSYour Name 			<legal 0>
372*5113495bSYour Name */
373*5113495bSYour Name 
374*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET                                          0x0000000000000020
375*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_LSB                                             0
376*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_MSB                                             31
377*5113495bSYour Name #define REO_FLUSH_CACHE_RESERVED_8A_MASK                                            0x00000000ffffffff
378*5113495bSYour Name 
379*5113495bSYour Name 
380*5113495bSYour Name /* Description		TLV64_PADDING
381*5113495bSYour Name 
382*5113495bSYour Name 			Automatic DWORD padding inserted while converting TLV32
383*5113495bSYour Name 			to TLV64 for 64 bit ARCH
384*5113495bSYour Name 			<legal 0>
385*5113495bSYour Name */
386*5113495bSYour Name 
387*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET                                        0x0000000000000020
388*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_LSB                                           32
389*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_MSB                                           63
390*5113495bSYour Name #define REO_FLUSH_CACHE_TLV64_PADDING_MASK                                          0xffffffff00000000
391*5113495bSYour Name 
392*5113495bSYour Name 
393*5113495bSYour Name 
394*5113495bSYour Name #endif   // REO_FLUSH_CACHE
395