1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_FLUSH_CACHE_H_ 18 #define _REO_FLUSH_CACHE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_cmd_header.h" 23 #define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 24 25 #define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 26 27 28 struct reo_flush_cache { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_cmd_header cmd_header; 31 uint32_t flush_addr_31_0 : 32; // [31:0] 32 uint32_t flush_addr_39_32 : 8, // [7:0] 33 forward_all_mpdus_in_queue : 1, // [8:8] 34 release_cache_block_index : 1, // [9:9] 35 cache_block_resource_index : 2, // [11:10] 36 flush_without_invalidate : 1, // [12:12] 37 block_cache_usage_after_flush : 1, // [13:13] 38 flush_entire_cache : 1, // [14:14] 39 flush_queue_1k_desc : 1, // [15:15] 40 reserved_2b : 16; // [31:16] 41 uint32_t reserved_3a : 32; // [31:0] 42 uint32_t reserved_4a : 32; // [31:0] 43 uint32_t reserved_5a : 32; // [31:0] 44 uint32_t reserved_6a : 32; // [31:0] 45 uint32_t reserved_7a : 32; // [31:0] 46 uint32_t reserved_8a : 32; // [31:0] 47 uint32_t tlv64_padding : 32; // [31:0] 48 #else 49 struct uniform_reo_cmd_header cmd_header; 50 uint32_t flush_addr_31_0 : 32; // [31:0] 51 uint32_t reserved_2b : 16, // [31:16] 52 flush_queue_1k_desc : 1, // [15:15] 53 flush_entire_cache : 1, // [14:14] 54 block_cache_usage_after_flush : 1, // [13:13] 55 flush_without_invalidate : 1, // [12:12] 56 cache_block_resource_index : 2, // [11:10] 57 release_cache_block_index : 1, // [9:9] 58 forward_all_mpdus_in_queue : 1, // [8:8] 59 flush_addr_39_32 : 8; // [7:0] 60 uint32_t reserved_3a : 32; // [31:0] 61 uint32_t reserved_4a : 32; // [31:0] 62 uint32_t reserved_5a : 32; // [31:0] 63 uint32_t reserved_6a : 32; // [31:0] 64 uint32_t reserved_7a : 32; // [31:0] 65 uint32_t reserved_8a : 32; // [31:0] 66 uint32_t tlv64_padding : 32; // [31:0] 67 #endif 68 }; 69 70 71 /* Description CMD_HEADER 72 73 Consumer: REO 74 Producer: SW 75 76 Details for command execution tracking purposes. 77 */ 78 79 80 /* Description REO_CMD_NUMBER 81 82 Consumer: REO/SW/DEBUG 83 Producer: SW 84 85 This number can be used by SW to track, identify and link 86 the created commands with the command statusses 87 88 89 <legal all> 90 */ 91 92 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 93 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 94 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 95 #define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 96 97 98 /* Description REO_STATUS_REQUIRED 99 100 Consumer: REO 101 Producer: SW 102 103 <enum 0 NoStatus> REO does not need to generate a status 104 TLV for the execution of this command 105 <enum 1 StatusRequired> REO shall generate a status TLV 106 for the execution of this command 107 108 <legal all> 109 */ 110 111 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 112 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 113 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 114 #define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 115 116 117 /* Description RESERVED_0A 118 119 <legal 0> 120 */ 121 122 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 123 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 124 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 125 #define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 126 127 128 /* Description FLUSH_ADDR_31_0 129 130 Consumer: REO 131 Producer: SW 132 133 Address (lower 32 bits) of the descriptor to flush 134 <legal all> 135 */ 136 137 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 138 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 139 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 140 #define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 141 142 143 /* Description FLUSH_ADDR_39_32 144 145 Consumer: REO 146 Producer: SW 147 148 Address (upper 8 bits) of the descriptor to flush 149 <legal all> 150 */ 151 152 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 153 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 154 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 155 #define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff 156 157 158 /* Description FORWARD_ALL_MPDUS_IN_QUEUE 159 160 Is only allowed to be set when the flush address corresponds 161 with a REO descriptor. 162 163 When set, REO shall first forward all the MPDUs held in 164 the indicated re-order queue, before flushing the descriptor 165 from the cache. 166 <legal all> 167 */ 168 169 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 170 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 171 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 172 #define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 173 174 175 /* Description RELEASE_CACHE_BLOCK_INDEX 176 177 Field not valid when Flush_entire_cache is set. 178 179 If SW has previously used a blocking resource that it now 180 wants to re-use for this command, this bit shall be set. 181 It prevents SW from having to send a separate REO_UNBLOCK_CACHE 182 command. 183 184 When set, HW will first release the blocking resource (indicated 185 in field 'Cache_block_resouce_index') before this command 186 gets executed. 187 If that resource was already unblocked, this will be considered 188 an error. This command will not be executed, and an error 189 shall be returned. 190 <legal all> 191 */ 192 193 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 194 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 195 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 196 #define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 197 198 199 /* Description CACHE_BLOCK_RESOURCE_INDEX 200 201 Field not valid when Flush_entire_cache is set. 202 203 Indicates which of the four blocking resources in REO will 204 be assigned for managing the blocking of this (descriptor) 205 address 206 <legal all> 207 */ 208 209 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 210 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 211 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 212 #define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 213 214 215 /* Description FLUSH_WITHOUT_INVALIDATE 216 217 Field not valid when Flush_entire_cache is set. 218 219 When set, REO shall flush the cache line contents from the 220 cache, but there is NO need to invalidate the cache line 221 entry... The contents in the cache can be maintained. This 222 feature can be used by SW (and DV) to get a current snapshot 223 of the contents in the cache 224 225 <legal all> 226 */ 227 228 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 229 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 230 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 231 #define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 232 233 234 /* Description BLOCK_CACHE_USAGE_AFTER_FLUSH 235 236 Field not valid when Flush_entire_cache is set. 237 238 When set, REO shall block any cache accesses to this address 239 till explicitly unblocked. 240 241 Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue' 242 to ensure all packets are flushed out in order to make sure 243 this queue desc is not in one of the aging link lists. 244 In case SW does not want to flush the MPDUs in the queue, 245 see the recipe description below this TLV definition. 246 247 The 'blocking' index to be used for this is indicated in 248 field 'cache_block_resource_index'. If SW had previously 249 used this blocking resource and was not freed up yet, SW 250 shall first unblock that index (by setting bit Release_cache_block_index) 251 or use an unblock command. 252 253 If the resource indicated here was already blocked (and 254 did not get unblocked in this command), it is considered 255 an error scenario... 256 No flush shall happen. The status for this command shall 257 indicate error. 258 259 <legal all> 260 */ 261 262 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 263 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 264 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 265 #define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 266 267 268 /* Description FLUSH_ENTIRE_CACHE 269 270 When set, the entire cache shall be flushed. The entire 271 cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND' 272 is received with bit unblock type set to unblock_cache. 273 All other fields in this command are to be ignored. 274 275 Note that flushing the entire cache has no changes to the 276 current settings of the blocking resource settings 277 278 <legal all> 279 */ 280 281 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 282 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 283 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 284 #define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 285 286 287 /* Description FLUSH_QUEUE_1K_DESC 288 289 When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor 290 after flushing the 'RX_REO_QUEUE' descriptor. 291 292 This bit shall only be set when the BA_window_size > 255 293 in 'RX_REO_QUEUE.' 294 <legal all> 295 */ 296 297 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 298 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 299 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 300 #define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 301 302 303 /* Description RESERVED_2B 304 305 <legal 0> 306 */ 307 308 #define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 309 #define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 310 #define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 311 #define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 312 313 314 /* Description RESERVED_3A 315 316 <legal 0> 317 */ 318 319 #define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 320 #define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 321 #define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 322 #define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 323 324 325 /* Description RESERVED_4A 326 327 <legal 0> 328 */ 329 330 #define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 331 #define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 332 #define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 333 #define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff 334 335 336 /* Description RESERVED_5A 337 338 <legal 0> 339 */ 340 341 #define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 342 #define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 343 #define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 344 #define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 345 346 347 /* Description RESERVED_6A 348 349 <legal 0> 350 */ 351 352 #define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 353 #define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 354 #define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 355 #define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff 356 357 358 /* Description RESERVED_7A 359 360 <legal 0> 361 */ 362 363 #define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 364 #define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 365 #define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 366 #define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 367 368 369 /* Description RESERVED_8A 370 371 <legal 0> 372 */ 373 374 #define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 375 #define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 376 #define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 377 #define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff 378 379 380 /* Description TLV64_PADDING 381 382 Automatic DWORD padding inserted while converting TLV32 383 to TLV64 for 64 bit ARCH 384 <legal 0> 385 */ 386 387 #define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 388 #define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 389 #define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 390 #define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 391 392 393 394 #endif // REO_FLUSH_CACHE 395