xref: /wlan-driver/fw-api/hw/qcn6432/reo_flush_queue.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name /*
2*5113495bSYour Name  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name #ifndef _REO_FLUSH_QUEUE_H_
18*5113495bSYour Name #define _REO_FLUSH_QUEUE_H_
19*5113495bSYour Name #if !defined(__ASSEMBLER__)
20*5113495bSYour Name #endif
21*5113495bSYour Name 
22*5113495bSYour Name #include "uniform_reo_cmd_header.h"
23*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
24*5113495bSYour Name 
25*5113495bSYour Name #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
26*5113495bSYour Name 
27*5113495bSYour Name 
28*5113495bSYour Name struct reo_flush_queue {
29*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
30*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
31*5113495bSYour Name              uint32_t flush_desc_addr_31_0                                    : 32; // [31:0]
32*5113495bSYour Name              uint32_t flush_desc_addr_39_32                                   :  8, // [7:0]
33*5113495bSYour Name                       block_desc_addr_usage_after_flush                       :  1, // [8:8]
34*5113495bSYour Name                       block_resource_index                                    :  2, // [10:9]
35*5113495bSYour Name                       reserved_2a                                             : 21; // [31:11]
36*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
37*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
38*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
39*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
40*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
41*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
42*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
43*5113495bSYour Name #else
44*5113495bSYour Name              struct   uniform_reo_cmd_header                                    cmd_header;
45*5113495bSYour Name              uint32_t flush_desc_addr_31_0                                    : 32; // [31:0]
46*5113495bSYour Name              uint32_t reserved_2a                                             : 21, // [31:11]
47*5113495bSYour Name                       block_resource_index                                    :  2, // [10:9]
48*5113495bSYour Name                       block_desc_addr_usage_after_flush                       :  1, // [8:8]
49*5113495bSYour Name                       flush_desc_addr_39_32                                   :  8; // [7:0]
50*5113495bSYour Name              uint32_t reserved_3a                                             : 32; // [31:0]
51*5113495bSYour Name              uint32_t reserved_4a                                             : 32; // [31:0]
52*5113495bSYour Name              uint32_t reserved_5a                                             : 32; // [31:0]
53*5113495bSYour Name              uint32_t reserved_6a                                             : 32; // [31:0]
54*5113495bSYour Name              uint32_t reserved_7a                                             : 32; // [31:0]
55*5113495bSYour Name              uint32_t reserved_8a                                             : 32; // [31:0]
56*5113495bSYour Name              uint32_t tlv64_padding                                           : 32; // [31:0]
57*5113495bSYour Name #endif
58*5113495bSYour Name };
59*5113495bSYour Name 
60*5113495bSYour Name 
61*5113495bSYour Name /* Description		CMD_HEADER
62*5113495bSYour Name 
63*5113495bSYour Name 			Consumer: REO
64*5113495bSYour Name 			Producer: SW
65*5113495bSYour Name 
66*5113495bSYour Name 			Details for command execution tracking purposes.
67*5113495bSYour Name */
68*5113495bSYour Name 
69*5113495bSYour Name 
70*5113495bSYour Name /* Description		REO_CMD_NUMBER
71*5113495bSYour Name 
72*5113495bSYour Name 			Consumer: REO/SW/DEBUG
73*5113495bSYour Name 			Producer: SW
74*5113495bSYour Name 
75*5113495bSYour Name 			This number can be used by SW to track, identify and link
76*5113495bSYour Name 			 the created commands with the command statusses
77*5113495bSYour Name 
78*5113495bSYour Name 
79*5113495bSYour Name 			<legal all>
80*5113495bSYour Name */
81*5113495bSYour Name 
82*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x0000000000000000
83*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
84*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
85*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x000000000000ffff
86*5113495bSYour Name 
87*5113495bSYour Name 
88*5113495bSYour Name /* Description		REO_STATUS_REQUIRED
89*5113495bSYour Name 
90*5113495bSYour Name 			Consumer: REO
91*5113495bSYour Name 			Producer: SW
92*5113495bSYour Name 
93*5113495bSYour Name 			<enum 0 NoStatus> REO does not need to generate a status
94*5113495bSYour Name 			 TLV for the execution of this command
95*5113495bSYour Name 			<enum 1 StatusRequired> REO shall generate a status TLV
96*5113495bSYour Name 			for the execution of this command
97*5113495bSYour Name 
98*5113495bSYour Name 			<legal all>
99*5113495bSYour Name */
100*5113495bSYour Name 
101*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x0000000000000000
102*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
103*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
104*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x0000000000010000
105*5113495bSYour Name 
106*5113495bSYour Name 
107*5113495bSYour Name /* Description		RESERVED_0A
108*5113495bSYour Name 
109*5113495bSYour Name 			<legal 0>
110*5113495bSYour Name */
111*5113495bSYour Name 
112*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                               0x0000000000000000
113*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB                                  17
114*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB                                  31
115*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK                                 0x00000000fffe0000
116*5113495bSYour Name 
117*5113495bSYour Name 
118*5113495bSYour Name /* Description		FLUSH_DESC_ADDR_31_0
119*5113495bSYour Name 
120*5113495bSYour Name 			Consumer: REO
121*5113495bSYour Name 			Producer: SW
122*5113495bSYour Name 
123*5113495bSYour Name 			Address (lower 32 bits) of the descriptor to flush
124*5113495bSYour Name 			<legal all>
125*5113495bSYour Name */
126*5113495bSYour Name 
127*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET                                 0x0000000000000000
128*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB                                    32
129*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB                                    63
130*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK                                   0xffffffff00000000
131*5113495bSYour Name 
132*5113495bSYour Name 
133*5113495bSYour Name /* Description		FLUSH_DESC_ADDR_39_32
134*5113495bSYour Name 
135*5113495bSYour Name 			Consumer: REO
136*5113495bSYour Name 			Producer: SW
137*5113495bSYour Name 
138*5113495bSYour Name 			Address (upper 8 bits) of the descriptor to flush
139*5113495bSYour Name 			<legal all>
140*5113495bSYour Name */
141*5113495bSYour Name 
142*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET                                0x0000000000000008
143*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB                                   0
144*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB                                   7
145*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK                                  0x00000000000000ff
146*5113495bSYour Name 
147*5113495bSYour Name 
148*5113495bSYour Name /* Description		BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
149*5113495bSYour Name 
150*5113495bSYour Name 			When set, REO shall not re-fetch this address till SW explicitly
151*5113495bSYour Name 			 unblocked this address
152*5113495bSYour Name 
153*5113495bSYour Name 			If the blocking resource was already used, this command
154*5113495bSYour Name 			shall fail and an error is reported
155*5113495bSYour Name 
156*5113495bSYour Name 			<legal all>
157*5113495bSYour Name */
158*5113495bSYour Name 
159*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET                    0x0000000000000008
160*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB                       8
161*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB                       8
162*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK                      0x0000000000000100
163*5113495bSYour Name 
164*5113495bSYour Name 
165*5113495bSYour Name /* Description		BLOCK_RESOURCE_INDEX
166*5113495bSYour Name 
167*5113495bSYour Name 			Field only valid when 'Block_desc_addr_usage_after_flush
168*5113495bSYour Name 			 ' is set.
169*5113495bSYour Name 
170*5113495bSYour Name 			Indicates which of the four blocking resources in REO will
171*5113495bSYour Name 			 be assigned for managing the blocking of this address.
172*5113495bSYour Name 			<legal all>
173*5113495bSYour Name */
174*5113495bSYour Name 
175*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET                                 0x0000000000000008
176*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB                                    9
177*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB                                    10
178*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK                                   0x0000000000000600
179*5113495bSYour Name 
180*5113495bSYour Name 
181*5113495bSYour Name /* Description		RESERVED_2A
182*5113495bSYour Name 
183*5113495bSYour Name 			<legal 0>
184*5113495bSYour Name */
185*5113495bSYour Name 
186*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET                                          0x0000000000000008
187*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_LSB                                             11
188*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MSB                                             31
189*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MASK                                            0x00000000fffff800
190*5113495bSYour Name 
191*5113495bSYour Name 
192*5113495bSYour Name /* Description		RESERVED_3A
193*5113495bSYour Name 
194*5113495bSYour Name 			<legal 0>
195*5113495bSYour Name */
196*5113495bSYour Name 
197*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET                                          0x0000000000000008
198*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_LSB                                             32
199*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MSB                                             63
200*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MASK                                            0xffffffff00000000
201*5113495bSYour Name 
202*5113495bSYour Name 
203*5113495bSYour Name /* Description		RESERVED_4A
204*5113495bSYour Name 
205*5113495bSYour Name 			<legal 0>
206*5113495bSYour Name */
207*5113495bSYour Name 
208*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET                                          0x0000000000000010
209*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_LSB                                             0
210*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MSB                                             31
211*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MASK                                            0x00000000ffffffff
212*5113495bSYour Name 
213*5113495bSYour Name 
214*5113495bSYour Name /* Description		RESERVED_5A
215*5113495bSYour Name 
216*5113495bSYour Name 			<legal 0>
217*5113495bSYour Name */
218*5113495bSYour Name 
219*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET                                          0x0000000000000010
220*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_LSB                                             32
221*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MSB                                             63
222*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MASK                                            0xffffffff00000000
223*5113495bSYour Name 
224*5113495bSYour Name 
225*5113495bSYour Name /* Description		RESERVED_6A
226*5113495bSYour Name 
227*5113495bSYour Name 			<legal 0>
228*5113495bSYour Name */
229*5113495bSYour Name 
230*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET                                          0x0000000000000018
231*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_LSB                                             0
232*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MSB                                             31
233*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MASK                                            0x00000000ffffffff
234*5113495bSYour Name 
235*5113495bSYour Name 
236*5113495bSYour Name /* Description		RESERVED_7A
237*5113495bSYour Name 
238*5113495bSYour Name 			<legal 0>
239*5113495bSYour Name */
240*5113495bSYour Name 
241*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET                                          0x0000000000000018
242*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_LSB                                             32
243*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MSB                                             63
244*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MASK                                            0xffffffff00000000
245*5113495bSYour Name 
246*5113495bSYour Name 
247*5113495bSYour Name /* Description		RESERVED_8A
248*5113495bSYour Name 
249*5113495bSYour Name 			<legal 0>
250*5113495bSYour Name */
251*5113495bSYour Name 
252*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET                                          0x0000000000000020
253*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_LSB                                             0
254*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MSB                                             31
255*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MASK                                            0x00000000ffffffff
256*5113495bSYour Name 
257*5113495bSYour Name 
258*5113495bSYour Name /* Description		TLV64_PADDING
259*5113495bSYour Name 
260*5113495bSYour Name 			Automatic DWORD padding inserted while converting TLV32
261*5113495bSYour Name 			to TLV64 for 64 bit ARCH
262*5113495bSYour Name 			<legal 0>
263*5113495bSYour Name */
264*5113495bSYour Name 
265*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET                                        0x0000000000000020
266*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB                                           32
267*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB                                           63
268*5113495bSYour Name #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK                                          0xffffffff00000000
269*5113495bSYour Name 
270*5113495bSYour Name 
271*5113495bSYour Name 
272*5113495bSYour Name #endif   // REO_FLUSH_QUEUE
273