1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_FLUSH_QUEUE_H_ 18 #define _REO_FLUSH_QUEUE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_cmd_header.h" 23 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 24 25 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 26 27 28 struct reo_flush_queue { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_cmd_header cmd_header; 31 uint32_t flush_desc_addr_31_0 : 32; // [31:0] 32 uint32_t flush_desc_addr_39_32 : 8, // [7:0] 33 block_desc_addr_usage_after_flush : 1, // [8:8] 34 block_resource_index : 2, // [10:9] 35 reserved_2a : 21; // [31:11] 36 uint32_t reserved_3a : 32; // [31:0] 37 uint32_t reserved_4a : 32; // [31:0] 38 uint32_t reserved_5a : 32; // [31:0] 39 uint32_t reserved_6a : 32; // [31:0] 40 uint32_t reserved_7a : 32; // [31:0] 41 uint32_t reserved_8a : 32; // [31:0] 42 uint32_t tlv64_padding : 32; // [31:0] 43 #else 44 struct uniform_reo_cmd_header cmd_header; 45 uint32_t flush_desc_addr_31_0 : 32; // [31:0] 46 uint32_t reserved_2a : 21, // [31:11] 47 block_resource_index : 2, // [10:9] 48 block_desc_addr_usage_after_flush : 1, // [8:8] 49 flush_desc_addr_39_32 : 8; // [7:0] 50 uint32_t reserved_3a : 32; // [31:0] 51 uint32_t reserved_4a : 32; // [31:0] 52 uint32_t reserved_5a : 32; // [31:0] 53 uint32_t reserved_6a : 32; // [31:0] 54 uint32_t reserved_7a : 32; // [31:0] 55 uint32_t reserved_8a : 32; // [31:0] 56 uint32_t tlv64_padding : 32; // [31:0] 57 #endif 58 }; 59 60 61 /* Description CMD_HEADER 62 63 Consumer: REO 64 Producer: SW 65 66 Details for command execution tracking purposes. 67 */ 68 69 70 /* Description REO_CMD_NUMBER 71 72 Consumer: REO/SW/DEBUG 73 Producer: SW 74 75 This number can be used by SW to track, identify and link 76 the created commands with the command statusses 77 78 79 <legal all> 80 */ 81 82 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 83 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 84 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 85 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 86 87 88 /* Description REO_STATUS_REQUIRED 89 90 Consumer: REO 91 Producer: SW 92 93 <enum 0 NoStatus> REO does not need to generate a status 94 TLV for the execution of this command 95 <enum 1 StatusRequired> REO shall generate a status TLV 96 for the execution of this command 97 98 <legal all> 99 */ 100 101 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 102 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 103 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 104 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 105 106 107 /* Description RESERVED_0A 108 109 <legal 0> 110 */ 111 112 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 113 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 114 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 115 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 116 117 118 /* Description FLUSH_DESC_ADDR_31_0 119 120 Consumer: REO 121 Producer: SW 122 123 Address (lower 32 bits) of the descriptor to flush 124 <legal all> 125 */ 126 127 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 128 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 129 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 130 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 131 132 133 /* Description FLUSH_DESC_ADDR_39_32 134 135 Consumer: REO 136 Producer: SW 137 138 Address (upper 8 bits) of the descriptor to flush 139 <legal all> 140 */ 141 142 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 143 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 144 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 145 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 146 147 148 /* Description BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH 149 150 When set, REO shall not re-fetch this address till SW explicitly 151 unblocked this address 152 153 If the blocking resource was already used, this command 154 shall fail and an error is reported 155 156 <legal all> 157 */ 158 159 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 160 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 161 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 162 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 163 164 165 /* Description BLOCK_RESOURCE_INDEX 166 167 Field only valid when 'Block_desc_addr_usage_after_flush 168 ' is set. 169 170 Indicates which of the four blocking resources in REO will 171 be assigned for managing the blocking of this address. 172 <legal all> 173 */ 174 175 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 176 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 177 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 178 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 179 180 181 /* Description RESERVED_2A 182 183 <legal 0> 184 */ 185 186 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 187 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 188 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 189 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 190 191 192 /* Description RESERVED_3A 193 194 <legal 0> 195 */ 196 197 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 198 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 199 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 200 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 201 202 203 /* Description RESERVED_4A 204 205 <legal 0> 206 */ 207 208 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 209 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 210 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 211 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 212 213 214 /* Description RESERVED_5A 215 216 <legal 0> 217 */ 218 219 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 220 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 221 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 222 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 223 224 225 /* Description RESERVED_6A 226 227 <legal 0> 228 */ 229 230 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 231 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 232 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 233 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 234 235 236 /* Description RESERVED_7A 237 238 <legal 0> 239 */ 240 241 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 242 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 243 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 244 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 245 246 247 /* Description RESERVED_8A 248 249 <legal 0> 250 */ 251 252 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 253 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 254 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 255 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 256 257 258 /* Description TLV64_PADDING 259 260 Automatic DWORD padding inserted while converting TLV32 261 to TLV64 for 64 bit ARCH 262 <legal 0> 263 */ 264 265 #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 266 #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 267 #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 268 #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 269 270 271 272 #endif // REO_FLUSH_QUEUE 273