1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_FLUSH_TIMEOUT_LIST_H_ 18 #define _REO_FLUSH_TIMEOUT_LIST_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_cmd_header.h" 23 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10 24 25 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5 26 27 28 struct reo_flush_timeout_list { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_cmd_header cmd_header; 31 uint32_t ac_timout_list : 2, // [1:0] 32 reserved_1 : 30; // [31:2] 33 uint32_t minimum_release_desc_count : 16, // [15:0] 34 minimum_forward_buf_count : 16; // [31:16] 35 uint32_t reserved_3a : 32; // [31:0] 36 uint32_t reserved_4a : 32; // [31:0] 37 uint32_t reserved_5a : 32; // [31:0] 38 uint32_t reserved_6a : 32; // [31:0] 39 uint32_t reserved_7a : 32; // [31:0] 40 uint32_t reserved_8a : 32; // [31:0] 41 uint32_t tlv64_padding : 32; // [31:0] 42 #else 43 struct uniform_reo_cmd_header cmd_header; 44 uint32_t reserved_1 : 30, // [31:2] 45 ac_timout_list : 2; // [1:0] 46 uint32_t minimum_forward_buf_count : 16, // [31:16] 47 minimum_release_desc_count : 16; // [15:0] 48 uint32_t reserved_3a : 32; // [31:0] 49 uint32_t reserved_4a : 32; // [31:0] 50 uint32_t reserved_5a : 32; // [31:0] 51 uint32_t reserved_6a : 32; // [31:0] 52 uint32_t reserved_7a : 32; // [31:0] 53 uint32_t reserved_8a : 32; // [31:0] 54 uint32_t tlv64_padding : 32; // [31:0] 55 #endif 56 }; 57 58 59 /* Description CMD_HEADER 60 61 Consumer: REO 62 Producer: SW 63 64 Details for command execution tracking purposes. 65 */ 66 67 68 /* Description REO_CMD_NUMBER 69 70 Consumer: REO/SW/DEBUG 71 Producer: SW 72 73 This number can be used by SW to track, identify and link 74 the created commands with the command statusses 75 76 77 <legal all> 78 */ 79 80 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 81 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 82 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 83 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 84 85 86 /* Description REO_STATUS_REQUIRED 87 88 Consumer: REO 89 Producer: SW 90 91 <enum 0 NoStatus> REO does not need to generate a status 92 TLV for the execution of this command 93 <enum 1 StatusRequired> REO shall generate a status TLV 94 for the execution of this command 95 96 <legal all> 97 */ 98 99 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 100 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 101 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 102 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 103 104 105 /* Description RESERVED_0A 106 107 <legal 0> 108 */ 109 110 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 111 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 112 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 113 #define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 114 115 116 /* Description AC_TIMOUT_LIST 117 118 Consumer: REO 119 Producer: SW 120 121 The AC_timeout list to be used for this command 122 <legal all> 123 */ 124 125 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000 126 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32 127 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33 128 #define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000 129 130 131 /* Description RESERVED_1 132 133 <legal 0> 134 */ 135 136 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000 137 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34 138 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63 139 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000 140 141 142 /* Description MINIMUM_RELEASE_DESC_COUNT 143 144 Consumer: REO 145 Producer: SW 146 147 The minimum number of link descriptors requested to be released. 148 If set to 0, only buffer release counts seems to be important... 149 When set to very high value, likely the entire timeout list 150 will be exhausted before this count is reached or maybe 151 this count will not get reached. REO however will stop 152 here as it can not do anything else. 153 154 When both this field and field Minimum_forward_buf_count 155 are > 0, REO needs to meet both requirements. When both 156 entries are 0 (which should be a programming error), REO 157 does not need to do anything. 158 159 Note that this includes counts of MPDU link Desc as well 160 as MSDU link Desc. Where the count of MSDU link Desc is 161 not known to REO it's approximated by deriving from MSDU 162 count 163 <legal all> 164 */ 165 166 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 167 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 168 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 169 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff 170 171 172 /* Description MINIMUM_FORWARD_BUF_COUNT 173 174 Consumer: REO 175 Producer: SW 176 177 The minimum number of buffer descriptors requested to be 178 passed on to the REO destination rings. 179 180 If set to 0, only descriptor release counts seems to be 181 important... 182 183 When set to very high value, likely the entire timeout list 184 will be exhausted before this count is reached or maybe 185 this count will not get reached. REO however will stop 186 here as it can not do anything else. 187 188 Note that REO does not know the exact buffer count. This 189 can be approximated by using the MSDU_COUNT 190 <legal all> 191 */ 192 193 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 194 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 195 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 196 #define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000 197 198 199 /* Description RESERVED_3A 200 201 <legal 0> 202 */ 203 204 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008 205 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32 206 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63 207 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000 208 209 210 /* Description RESERVED_4A 211 212 <legal 0> 213 */ 214 215 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010 216 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 217 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 218 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff 219 220 221 /* Description RESERVED_5A 222 223 <legal 0> 224 */ 225 226 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010 227 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32 228 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63 229 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000 230 231 232 /* Description RESERVED_6A 233 234 <legal 0> 235 */ 236 237 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018 238 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 239 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 240 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff 241 242 243 /* Description RESERVED_7A 244 245 <legal 0> 246 */ 247 248 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018 249 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32 250 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63 251 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000 252 253 254 /* Description RESERVED_8A 255 256 <legal 0> 257 */ 258 259 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020 260 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 261 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 262 #define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff 263 264 265 /* Description TLV64_PADDING 266 267 Automatic DWORD padding inserted while converting TLV32 268 to TLV64 for 64 bit ARCH 269 <legal 0> 270 */ 271 272 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020 273 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32 274 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63 275 #define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000 276 277 278 279 #endif // REO_FLUSH_TIMEOUT_LIST 280