1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 18 #define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_status_header.h" 23 #define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 24 25 #define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 26 27 28 struct reo_flush_timeout_list_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_status_header status_header; 31 uint32_t error_detected : 1, // [0:0] 32 timout_list_empty : 1, // [1:1] 33 reserved_2a : 30; // [31:2] 34 uint32_t release_desc_count : 16, // [15:0] 35 forward_buf_count : 16; // [31:16] 36 uint32_t reserved_4a : 32; // [31:0] 37 uint32_t reserved_5a : 32; // [31:0] 38 uint32_t reserved_6a : 32; // [31:0] 39 uint32_t reserved_7a : 32; // [31:0] 40 uint32_t reserved_8a : 32; // [31:0] 41 uint32_t reserved_9a : 32; // [31:0] 42 uint32_t reserved_10a : 32; // [31:0] 43 uint32_t reserved_11a : 32; // [31:0] 44 uint32_t reserved_12a : 32; // [31:0] 45 uint32_t reserved_13a : 32; // [31:0] 46 uint32_t reserved_14a : 32; // [31:0] 47 uint32_t reserved_15a : 32; // [31:0] 48 uint32_t reserved_16a : 32; // [31:0] 49 uint32_t reserved_17a : 32; // [31:0] 50 uint32_t reserved_18a : 32; // [31:0] 51 uint32_t reserved_19a : 32; // [31:0] 52 uint32_t reserved_20a : 32; // [31:0] 53 uint32_t reserved_21a : 32; // [31:0] 54 uint32_t reserved_22a : 32; // [31:0] 55 uint32_t reserved_23a : 32; // [31:0] 56 uint32_t reserved_24a : 32; // [31:0] 57 uint32_t reserved_25a : 28, // [27:0] 58 looping_count : 4; // [31:28] 59 #else 60 struct uniform_reo_status_header status_header; 61 uint32_t reserved_2a : 30, // [31:2] 62 timout_list_empty : 1, // [1:1] 63 error_detected : 1; // [0:0] 64 uint32_t forward_buf_count : 16, // [31:16] 65 release_desc_count : 16; // [15:0] 66 uint32_t reserved_4a : 32; // [31:0] 67 uint32_t reserved_5a : 32; // [31:0] 68 uint32_t reserved_6a : 32; // [31:0] 69 uint32_t reserved_7a : 32; // [31:0] 70 uint32_t reserved_8a : 32; // [31:0] 71 uint32_t reserved_9a : 32; // [31:0] 72 uint32_t reserved_10a : 32; // [31:0] 73 uint32_t reserved_11a : 32; // [31:0] 74 uint32_t reserved_12a : 32; // [31:0] 75 uint32_t reserved_13a : 32; // [31:0] 76 uint32_t reserved_14a : 32; // [31:0] 77 uint32_t reserved_15a : 32; // [31:0] 78 uint32_t reserved_16a : 32; // [31:0] 79 uint32_t reserved_17a : 32; // [31:0] 80 uint32_t reserved_18a : 32; // [31:0] 81 uint32_t reserved_19a : 32; // [31:0] 82 uint32_t reserved_20a : 32; // [31:0] 83 uint32_t reserved_21a : 32; // [31:0] 84 uint32_t reserved_22a : 32; // [31:0] 85 uint32_t reserved_23a : 32; // [31:0] 86 uint32_t reserved_24a : 32; // [31:0] 87 uint32_t looping_count : 4, // [31:28] 88 reserved_25a : 28; // [27:0] 89 #endif 90 }; 91 92 93 /* Description STATUS_HEADER 94 95 Consumer: SW 96 Producer: REO 97 98 Details that can link this status with the original command. 99 It also contains info on how long REO took to execute this 100 command. 101 */ 102 103 104 /* Description REO_STATUS_NUMBER 105 106 Consumer: SW , DEBUG 107 Producer: REO 108 109 The value in this field is equal to value of the 'REO_CMD_Number' 110 field the REO command 111 112 This field helps to correlate the statuses with the REO 113 commands. 114 115 <legal all> 116 */ 117 118 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 119 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 120 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 121 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 122 123 124 /* Description CMD_EXECUTION_TIME 125 126 Consumer: DEBUG 127 Producer: REO 128 129 The amount of time REO took to excecute the command. Note 130 that this time does not include the duration of the command 131 waiting in the command ring, before the execution started. 132 133 134 In us. 135 136 <legal all> 137 */ 138 139 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 140 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 141 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 142 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 143 144 145 /* Description REO_CMD_EXECUTION_STATUS 146 147 Consumer: DEBUG 148 Producer: REO 149 150 Execution status of the command. 151 152 <enum 0 reo_successful_execution> Command has successfully 153 be executed 154 <enum 1 reo_blocked_execution> Command could not be executed 155 as the queue or cache was blocked 156 <enum 2 reo_failed_execution> Command has encountered problems 157 when executing, like the queue descriptor not being valid. 158 None of the status fields in the entire STATUS TLV are valid. 159 160 <enum 3 reo_resource_blocked> Command is NOT executed because 161 one or more descriptors were blocked. This is SW programming 162 mistake. 163 None of the status fields in the entire STATUS TLV are valid. 164 165 166 <legal 0-3> 167 */ 168 169 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 170 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 171 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 172 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 173 174 175 /* Description RESERVED_0A 176 177 <legal 0> 178 */ 179 180 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 181 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 182 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 183 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 184 185 186 /* Description TIMESTAMP 187 188 Timestamp at the moment that this status report is written. 189 190 191 <legal all> 192 */ 193 194 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 195 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 196 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 197 #define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 198 199 200 /* Description ERROR_DETECTED 201 202 0: No error has been detected while executing this command 203 204 1: command not properly executed and returned with an error 205 206 207 NOTE: Current no error is defined, but field is put in place 208 to avoid data structure changes in future... 209 */ 210 211 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 212 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 213 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 214 #define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 215 216 217 /* Description TIMOUT_LIST_EMPTY 218 219 When set, REO has depleted the timeout list and all entries 220 are gone. 221 <legal all> 222 */ 223 224 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 225 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 226 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 227 #define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 228 229 230 /* Description RESERVED_2A 231 232 <legal 0> 233 */ 234 235 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 236 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 237 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 238 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 239 240 241 /* Description RELEASE_DESC_COUNT 242 243 Consumer: REO 244 Producer: SW 245 246 The number of link descriptors released 247 <legal all> 248 */ 249 250 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 251 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 252 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 253 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 254 255 256 /* Description FORWARD_BUF_COUNT 257 258 Consumer: REO 259 Producer: SW 260 261 The number of buffers forwarded to the REO destination rings 262 263 <legal all> 264 */ 265 266 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 267 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 268 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 269 #define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 270 271 272 /* Description RESERVED_4A 273 274 <legal 0> 275 */ 276 277 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 278 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 279 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 280 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 281 282 283 /* Description RESERVED_5A 284 285 <legal 0> 286 */ 287 288 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 289 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 290 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 291 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 292 293 294 /* Description RESERVED_6A 295 296 <legal 0> 297 */ 298 299 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 300 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 301 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 302 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 303 304 305 /* Description RESERVED_7A 306 307 <legal 0> 308 */ 309 310 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 311 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 312 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 313 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 314 315 316 /* Description RESERVED_8A 317 318 <legal 0> 319 */ 320 321 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 322 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 323 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 324 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 325 326 327 /* Description RESERVED_9A 328 329 <legal 0> 330 */ 331 332 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 333 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 334 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 335 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 336 337 338 /* Description RESERVED_10A 339 340 <legal 0> 341 */ 342 343 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 344 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 345 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 346 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 347 348 349 /* Description RESERVED_11A 350 351 <legal 0> 352 */ 353 354 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 355 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 356 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 357 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 358 359 360 /* Description RESERVED_12A 361 362 <legal 0> 363 */ 364 365 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 366 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 367 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 368 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 369 370 371 /* Description RESERVED_13A 372 373 <legal 0> 374 */ 375 376 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 377 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 378 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 379 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 380 381 382 /* Description RESERVED_14A 383 384 <legal 0> 385 */ 386 387 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 388 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 389 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 390 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 391 392 393 /* Description RESERVED_15A 394 395 <legal 0> 396 */ 397 398 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 399 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 400 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 401 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 402 403 404 /* Description RESERVED_16A 405 406 <legal 0> 407 */ 408 409 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 410 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 411 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 412 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 413 414 415 /* Description RESERVED_17A 416 417 <legal 0> 418 */ 419 420 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 421 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 422 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 423 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 424 425 426 /* Description RESERVED_18A 427 428 <legal 0> 429 */ 430 431 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 432 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 433 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 434 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 435 436 437 /* Description RESERVED_19A 438 439 <legal 0> 440 */ 441 442 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 443 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 444 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 445 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 446 447 448 /* Description RESERVED_20A 449 450 <legal 0> 451 */ 452 453 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 454 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 455 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 456 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 457 458 459 /* Description RESERVED_21A 460 461 <legal 0> 462 */ 463 464 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 465 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 466 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 467 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 468 469 470 /* Description RESERVED_22A 471 472 <legal 0> 473 */ 474 475 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 476 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 477 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 478 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 479 480 481 /* Description RESERVED_23A 482 483 <legal 0> 484 */ 485 486 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 487 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 488 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 489 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 490 491 492 /* Description RESERVED_24A 493 494 <legal 0> 495 */ 496 497 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 498 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 499 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 500 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 501 502 503 /* Description RESERVED_25A 504 505 <legal 0> 506 */ 507 508 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 509 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 510 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 511 #define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 512 513 514 /* Description LOOPING_COUNT 515 516 A count value that indicates the number of times the producer 517 of entries into this Ring has looped around the ring. 518 At initialization time, this value is set to 0. On the first 519 loop, this value is set to 1. After the max value is reached 520 allowed by the number of bits for this field, the count 521 value continues with 0 again. 522 523 In case SW is the consumer of the ring entries, it can use 524 this field to figure out up to where the producer of entries 525 has created new entries. This eliminates the need to check 526 where the "head pointer' of the ring is located once the 527 SW starts processing an interrupt indicating that new entries 528 have been put into this ring... 529 530 Also note that SW if it wants only needs to look at the 531 LSB bit of this count value. 532 <legal all> 533 */ 534 535 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 536 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 537 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 538 #define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 539 540 541 542 #endif // REO_FLUSH_TIMEOUT_LIST_STATUS 543