1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_GET_QUEUE_STATS_H_ 18 #define _REO_GET_QUEUE_STATS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_cmd_header.h" 23 #define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 24 25 #define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 26 27 28 struct reo_get_queue_stats { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_cmd_header cmd_header; 31 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 32 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 33 clear_stats : 1, // [8:8] 34 reserved_2a : 23; // [31:9] 35 uint32_t reserved_3a : 32; // [31:0] 36 uint32_t reserved_4a : 32; // [31:0] 37 uint32_t reserved_5a : 32; // [31:0] 38 uint32_t reserved_6a : 32; // [31:0] 39 uint32_t reserved_7a : 32; // [31:0] 40 uint32_t reserved_8a : 32; // [31:0] 41 uint32_t tlv64_padding : 32; // [31:0] 42 #else 43 struct uniform_reo_cmd_header cmd_header; 44 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 45 uint32_t reserved_2a : 23, // [31:9] 46 clear_stats : 1, // [8:8] 47 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 48 uint32_t reserved_3a : 32; // [31:0] 49 uint32_t reserved_4a : 32; // [31:0] 50 uint32_t reserved_5a : 32; // [31:0] 51 uint32_t reserved_6a : 32; // [31:0] 52 uint32_t reserved_7a : 32; // [31:0] 53 uint32_t reserved_8a : 32; // [31:0] 54 uint32_t tlv64_padding : 32; // [31:0] 55 #endif 56 }; 57 58 59 /* Description CMD_HEADER 60 61 Consumer: REO 62 Producer: SW 63 64 Details for command execution tracking purposes. 65 */ 66 67 68 /* Description REO_CMD_NUMBER 69 70 Consumer: REO/SW/DEBUG 71 Producer: SW 72 73 This number can be used by SW to track, identify and link 74 the created commands with the command statusses 75 76 77 <legal all> 78 */ 79 80 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 81 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 82 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 83 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 84 85 86 /* Description REO_STATUS_REQUIRED 87 88 Consumer: REO 89 Producer: SW 90 91 <enum 0 NoStatus> REO does not need to generate a status 92 TLV for the execution of this command 93 <enum 1 StatusRequired> REO shall generate a status TLV 94 for the execution of this command 95 96 <legal all> 97 */ 98 99 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 100 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 101 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 102 #define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 103 104 105 /* Description RESERVED_0A 106 107 <legal 0> 108 */ 109 110 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 111 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 112 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 113 #define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 114 115 116 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 117 118 Consumer: REO 119 Producer: SW 120 121 Address (lower 32 bits) of the REO queue descriptor 122 <legal all> 123 */ 124 125 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 126 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 127 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 128 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 129 130 131 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 132 133 Consumer: REO 134 Producer: SW 135 136 Address (upper 8 bits) of the REO queue descriptor 137 <legal all> 138 */ 139 140 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 141 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 142 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 143 #define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 144 145 146 /* Description CLEAR_STATS 147 148 Clear stat settings.... 149 150 <enum 0 no_clear> Do NOT clear the stats after generating 151 the status 152 <enum 1 clear_the_stats> Clear the stats after generating 153 the status. 154 155 The stats actually cleared are: 156 Timeout_count 157 Forward_due_to_bar_count 158 Duplicate_count 159 Frames_in_order_count 160 BAR_received_count 161 MPDU_Frames_processed_count 162 MSDU_Frames_processed_count 163 Total_processed_byte_count 164 Late_receive_MPDU_count 165 window_jump_2k 166 Hole_count 167 <legal 0-1> 168 */ 169 170 #define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 171 #define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 172 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 173 #define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 174 175 176 /* Description RESERVED_2A 177 178 <legal 0> 179 */ 180 181 #define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 182 #define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 183 #define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 184 #define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 185 186 187 /* Description RESERVED_3A 188 189 <legal 0> 190 */ 191 192 #define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 193 #define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 194 #define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 195 #define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 196 197 198 /* Description RESERVED_4A 199 200 <legal 0> 201 */ 202 203 #define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 204 #define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 205 #define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 206 #define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff 207 208 209 /* Description RESERVED_5A 210 211 <legal 0> 212 */ 213 214 #define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 215 #define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 216 #define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 217 #define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 218 219 220 /* Description RESERVED_6A 221 222 <legal 0> 223 */ 224 225 #define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 226 #define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 227 #define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 228 #define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff 229 230 231 /* Description RESERVED_7A 232 233 <legal 0> 234 */ 235 236 #define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 237 #define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 238 #define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 239 #define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 240 241 242 /* Description RESERVED_8A 243 244 <legal 0> 245 */ 246 247 #define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 248 #define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 249 #define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 250 #define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff 251 252 253 /* Description TLV64_PADDING 254 255 Automatic DWORD padding inserted while converting TLV32 256 to TLV64 for 64 bit ARCH 257 <legal 0> 258 */ 259 260 #define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 261 #define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 262 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 263 #define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 264 265 266 267 #endif // REO_GET_QUEUE_STATS 268