1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_UNBLOCK_CACHE_STATUS_H_ 18 #define _REO_UNBLOCK_CACHE_STATUS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_status_header.h" 23 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 24 25 #define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 26 27 28 struct reo_unblock_cache_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_status_header status_header; 31 uint32_t error_detected : 1, // [0:0] 32 unblock_type : 1, // [1:1] 33 reserved_2a : 30; // [31:2] 34 uint32_t reserved_3a : 32; // [31:0] 35 uint32_t reserved_4a : 32; // [31:0] 36 uint32_t reserved_5a : 32; // [31:0] 37 uint32_t reserved_6a : 32; // [31:0] 38 uint32_t reserved_7a : 32; // [31:0] 39 uint32_t reserved_8a : 32; // [31:0] 40 uint32_t reserved_9a : 32; // [31:0] 41 uint32_t reserved_10a : 32; // [31:0] 42 uint32_t reserved_11a : 32; // [31:0] 43 uint32_t reserved_12a : 32; // [31:0] 44 uint32_t reserved_13a : 32; // [31:0] 45 uint32_t reserved_14a : 32; // [31:0] 46 uint32_t reserved_15a : 32; // [31:0] 47 uint32_t reserved_16a : 32; // [31:0] 48 uint32_t reserved_17a : 32; // [31:0] 49 uint32_t reserved_18a : 32; // [31:0] 50 uint32_t reserved_19a : 32; // [31:0] 51 uint32_t reserved_20a : 32; // [31:0] 52 uint32_t reserved_21a : 32; // [31:0] 53 uint32_t reserved_22a : 32; // [31:0] 54 uint32_t reserved_23a : 32; // [31:0] 55 uint32_t reserved_24a : 32; // [31:0] 56 uint32_t reserved_25a : 28, // [27:0] 57 looping_count : 4; // [31:28] 58 #else 59 struct uniform_reo_status_header status_header; 60 uint32_t reserved_2a : 30, // [31:2] 61 unblock_type : 1, // [1:1] 62 error_detected : 1; // [0:0] 63 uint32_t reserved_3a : 32; // [31:0] 64 uint32_t reserved_4a : 32; // [31:0] 65 uint32_t reserved_5a : 32; // [31:0] 66 uint32_t reserved_6a : 32; // [31:0] 67 uint32_t reserved_7a : 32; // [31:0] 68 uint32_t reserved_8a : 32; // [31:0] 69 uint32_t reserved_9a : 32; // [31:0] 70 uint32_t reserved_10a : 32; // [31:0] 71 uint32_t reserved_11a : 32; // [31:0] 72 uint32_t reserved_12a : 32; // [31:0] 73 uint32_t reserved_13a : 32; // [31:0] 74 uint32_t reserved_14a : 32; // [31:0] 75 uint32_t reserved_15a : 32; // [31:0] 76 uint32_t reserved_16a : 32; // [31:0] 77 uint32_t reserved_17a : 32; // [31:0] 78 uint32_t reserved_18a : 32; // [31:0] 79 uint32_t reserved_19a : 32; // [31:0] 80 uint32_t reserved_20a : 32; // [31:0] 81 uint32_t reserved_21a : 32; // [31:0] 82 uint32_t reserved_22a : 32; // [31:0] 83 uint32_t reserved_23a : 32; // [31:0] 84 uint32_t reserved_24a : 32; // [31:0] 85 uint32_t looping_count : 4, // [31:28] 86 reserved_25a : 28; // [27:0] 87 #endif 88 }; 89 90 91 /* Description STATUS_HEADER 92 93 Consumer: SW 94 Producer: REO 95 96 Details that can link this status with the original command. 97 It also contains info on how long REO took to execute this 98 command. 99 */ 100 101 102 /* Description REO_STATUS_NUMBER 103 104 Consumer: SW , DEBUG 105 Producer: REO 106 107 The value in this field is equal to value of the 'REO_CMD_Number' 108 field the REO command 109 110 This field helps to correlate the statuses with the REO 111 commands. 112 113 <legal all> 114 */ 115 116 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 117 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 118 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 119 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 120 121 122 /* Description CMD_EXECUTION_TIME 123 124 Consumer: DEBUG 125 Producer: REO 126 127 The amount of time REO took to excecute the command. Note 128 that this time does not include the duration of the command 129 waiting in the command ring, before the execution started. 130 131 132 In us. 133 134 <legal all> 135 */ 136 137 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 138 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 139 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 140 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 141 142 143 /* Description REO_CMD_EXECUTION_STATUS 144 145 Consumer: DEBUG 146 Producer: REO 147 148 Execution status of the command. 149 150 <enum 0 reo_successful_execution> Command has successfully 151 be executed 152 <enum 1 reo_blocked_execution> Command could not be executed 153 as the queue or cache was blocked 154 <enum 2 reo_failed_execution> Command has encountered problems 155 when executing, like the queue descriptor not being valid. 156 None of the status fields in the entire STATUS TLV are valid. 157 158 <enum 3 reo_resource_blocked> Command is NOT executed because 159 one or more descriptors were blocked. This is SW programming 160 mistake. 161 None of the status fields in the entire STATUS TLV are valid. 162 163 164 <legal 0-3> 165 */ 166 167 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 168 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 169 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 170 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 171 172 173 /* Description RESERVED_0A 174 175 <legal 0> 176 */ 177 178 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 179 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 180 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 181 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 182 183 184 /* Description TIMESTAMP 185 186 Timestamp at the moment that this status report is written. 187 188 189 <legal all> 190 */ 191 192 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 193 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 194 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 195 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 196 197 198 /* Description ERROR_DETECTED 199 200 Status for blocking resource handling 201 202 0: No error has been detected while executing this command 203 204 1: The blocking resource was not in use, and therefor it 205 could not be 'unblocked' 206 */ 207 208 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 209 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 210 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 211 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 212 213 214 /* Description UNBLOCK_TYPE 215 216 Reference to the type of Unblock command type... 217 218 <enum 0 unblock_resource_index> Unblock a blocking resource 219 220 221 <enum 1 unblock_cache> The entire cache usage is unblock. 222 223 224 <legal all> 225 */ 226 227 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 228 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 229 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 230 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 231 232 233 /* Description RESERVED_2A 234 235 <legal 0> 236 */ 237 238 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 239 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 240 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 241 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc 242 243 244 /* Description RESERVED_3A 245 246 <legal 0> 247 */ 248 249 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 250 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 251 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 252 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 253 254 255 /* Description RESERVED_4A 256 257 <legal 0> 258 */ 259 260 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 261 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 262 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 263 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 264 265 266 /* Description RESERVED_5A 267 268 <legal 0> 269 */ 270 271 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 272 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 273 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 274 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 275 276 277 /* Description RESERVED_6A 278 279 <legal 0> 280 */ 281 282 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 283 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 284 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 285 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 286 287 288 /* Description RESERVED_7A 289 290 <legal 0> 291 */ 292 293 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 294 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 295 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 296 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 297 298 299 /* Description RESERVED_8A 300 301 <legal 0> 302 */ 303 304 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 305 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 306 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 307 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 308 309 310 /* Description RESERVED_9A 311 312 <legal 0> 313 */ 314 315 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 316 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 317 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 318 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 319 320 321 /* Description RESERVED_10A 322 323 <legal 0> 324 */ 325 326 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 327 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 328 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 329 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 330 331 332 /* Description RESERVED_11A 333 334 <legal 0> 335 */ 336 337 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 338 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 339 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 340 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 341 342 343 /* Description RESERVED_12A 344 345 <legal 0> 346 */ 347 348 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 349 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 350 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 351 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 352 353 354 /* Description RESERVED_13A 355 356 <legal 0> 357 */ 358 359 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 360 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 361 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 362 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 363 364 365 /* Description RESERVED_14A 366 367 <legal 0> 368 */ 369 370 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 371 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 372 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 373 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 374 375 376 /* Description RESERVED_15A 377 378 <legal 0> 379 */ 380 381 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 382 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 383 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 384 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 385 386 387 /* Description RESERVED_16A 388 389 <legal 0> 390 */ 391 392 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 393 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 394 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 395 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 396 397 398 /* Description RESERVED_17A 399 400 <legal 0> 401 */ 402 403 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 404 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 405 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 406 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 407 408 409 /* Description RESERVED_18A 410 411 <legal 0> 412 */ 413 414 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 415 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 416 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 417 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 418 419 420 /* Description RESERVED_19A 421 422 <legal 0> 423 */ 424 425 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 426 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 427 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 428 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 429 430 431 /* Description RESERVED_20A 432 433 <legal 0> 434 */ 435 436 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 437 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 438 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 439 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 440 441 442 /* Description RESERVED_21A 443 444 <legal 0> 445 */ 446 447 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 448 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 449 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 450 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 451 452 453 /* Description RESERVED_22A 454 455 <legal 0> 456 */ 457 458 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 459 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 460 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 461 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 462 463 464 /* Description RESERVED_23A 465 466 <legal 0> 467 */ 468 469 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 470 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 471 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 472 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 473 474 475 /* Description RESERVED_24A 476 477 <legal 0> 478 */ 479 480 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 481 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 482 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 483 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 484 485 486 /* Description RESERVED_25A 487 488 <legal 0> 489 */ 490 491 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 492 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 493 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 494 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 495 496 497 /* Description LOOPING_COUNT 498 499 A count value that indicates the number of times the producer 500 of entries into this Ring has looped around the ring. 501 At initialization time, this value is set to 0. On the first 502 loop, this value is set to 1. After the max value is reached 503 allowed by the number of bits for this field, the count 504 value continues with 0 again. 505 506 In case SW is the consumer of the ring entries, it can use 507 this field to figure out up to where the producer of entries 508 has created new entries. This eliminates the need to check 509 where the "head pointer' of the ring is located once the 510 SW starts processing an interrupt indicating that new entries 511 have been put into this ring... 512 513 Also note that SW if it wants only needs to look at the 514 LSB bit of this count value. 515 <legal all> 516 */ 517 518 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 519 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 520 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 521 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 522 523 524 525 #endif // REO_UNBLOCK_CACHE_STATUS 526