1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 18 #define _REO_UPDATE_RX_REO_QUEUE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_cmd_header.h" 23 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 24 25 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 26 27 28 struct reo_update_rx_reo_queue { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_cmd_header cmd_header; 31 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 32 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 33 update_receive_queue_number : 1, // [8:8] 34 update_vld : 1, // [9:9] 35 update_associated_link_descriptor_counter : 1, // [10:10] 36 update_disable_duplicate_detection : 1, // [11:11] 37 update_soft_reorder_enable : 1, // [12:12] 38 update_ac : 1, // [13:13] 39 update_bar : 1, // [14:14] 40 update_rty : 1, // [15:15] 41 update_chk_2k_mode : 1, // [16:16] 42 update_oor_mode : 1, // [17:17] 43 update_ba_window_size : 1, // [18:18] 44 update_pn_check_needed : 1, // [19:19] 45 update_pn_shall_be_even : 1, // [20:20] 46 update_pn_shall_be_uneven : 1, // [21:21] 47 update_pn_handling_enable : 1, // [22:22] 48 update_pn_size : 1, // [23:23] 49 update_ignore_ampdu_flag : 1, // [24:24] 50 update_svld : 1, // [25:25] 51 update_ssn : 1, // [26:26] 52 update_seq_2k_error_detected_flag : 1, // [27:27] 53 update_pn_error_detected_flag : 1, // [28:28] 54 update_pn_valid : 1, // [29:29] 55 update_pn : 1, // [30:30] 56 clear_stat_counters : 1; // [31:31] 57 uint32_t receive_queue_number : 16, // [15:0] 58 vld : 1, // [16:16] 59 associated_link_descriptor_counter : 2, // [18:17] 60 disable_duplicate_detection : 1, // [19:19] 61 soft_reorder_enable : 1, // [20:20] 62 ac : 2, // [22:21] 63 bar : 1, // [23:23] 64 rty : 1, // [24:24] 65 chk_2k_mode : 1, // [25:25] 66 oor_mode : 1, // [26:26] 67 pn_check_needed : 1, // [27:27] 68 pn_shall_be_even : 1, // [28:28] 69 pn_shall_be_uneven : 1, // [29:29] 70 pn_handling_enable : 1, // [30:30] 71 ignore_ampdu_flag : 1; // [31:31] 72 uint32_t ba_window_size : 10, // [9:0] 73 pn_size : 2, // [11:10] 74 svld : 1, // [12:12] 75 ssn : 12, // [24:13] 76 seq_2k_error_detected_flag : 1, // [25:25] 77 pn_error_detected_flag : 1, // [26:26] 78 pn_valid : 1, // [27:27] 79 flush_from_cache : 1, // [28:28] 80 reserved_4a : 3; // [31:29] 81 uint32_t pn_31_0 : 32; // [31:0] 82 uint32_t pn_63_32 : 32; // [31:0] 83 uint32_t pn_95_64 : 32; // [31:0] 84 uint32_t pn_127_96 : 32; // [31:0] 85 uint32_t tlv64_padding : 32; // [31:0] 86 #else 87 struct uniform_reo_cmd_header cmd_header; 88 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 89 uint32_t clear_stat_counters : 1, // [31:31] 90 update_pn : 1, // [30:30] 91 update_pn_valid : 1, // [29:29] 92 update_pn_error_detected_flag : 1, // [28:28] 93 update_seq_2k_error_detected_flag : 1, // [27:27] 94 update_ssn : 1, // [26:26] 95 update_svld : 1, // [25:25] 96 update_ignore_ampdu_flag : 1, // [24:24] 97 update_pn_size : 1, // [23:23] 98 update_pn_handling_enable : 1, // [22:22] 99 update_pn_shall_be_uneven : 1, // [21:21] 100 update_pn_shall_be_even : 1, // [20:20] 101 update_pn_check_needed : 1, // [19:19] 102 update_ba_window_size : 1, // [18:18] 103 update_oor_mode : 1, // [17:17] 104 update_chk_2k_mode : 1, // [16:16] 105 update_rty : 1, // [15:15] 106 update_bar : 1, // [14:14] 107 update_ac : 1, // [13:13] 108 update_soft_reorder_enable : 1, // [12:12] 109 update_disable_duplicate_detection : 1, // [11:11] 110 update_associated_link_descriptor_counter : 1, // [10:10] 111 update_vld : 1, // [9:9] 112 update_receive_queue_number : 1, // [8:8] 113 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 114 uint32_t ignore_ampdu_flag : 1, // [31:31] 115 pn_handling_enable : 1, // [30:30] 116 pn_shall_be_uneven : 1, // [29:29] 117 pn_shall_be_even : 1, // [28:28] 118 pn_check_needed : 1, // [27:27] 119 oor_mode : 1, // [26:26] 120 chk_2k_mode : 1, // [25:25] 121 rty : 1, // [24:24] 122 bar : 1, // [23:23] 123 ac : 2, // [22:21] 124 soft_reorder_enable : 1, // [20:20] 125 disable_duplicate_detection : 1, // [19:19] 126 associated_link_descriptor_counter : 2, // [18:17] 127 vld : 1, // [16:16] 128 receive_queue_number : 16; // [15:0] 129 uint32_t reserved_4a : 3, // [31:29] 130 flush_from_cache : 1, // [28:28] 131 pn_valid : 1, // [27:27] 132 pn_error_detected_flag : 1, // [26:26] 133 seq_2k_error_detected_flag : 1, // [25:25] 134 ssn : 12, // [24:13] 135 svld : 1, // [12:12] 136 pn_size : 2, // [11:10] 137 ba_window_size : 10; // [9:0] 138 uint32_t pn_31_0 : 32; // [31:0] 139 uint32_t pn_63_32 : 32; // [31:0] 140 uint32_t pn_95_64 : 32; // [31:0] 141 uint32_t pn_127_96 : 32; // [31:0] 142 uint32_t tlv64_padding : 32; // [31:0] 143 #endif 144 }; 145 146 147 /* Description CMD_HEADER 148 149 Consumer: REO 150 Producer: SW 151 152 Details for command execution tracking purposes. 153 */ 154 155 156 /* Description REO_CMD_NUMBER 157 158 Consumer: REO/SW/DEBUG 159 Producer: SW 160 161 This number can be used by SW to track, identify and link 162 the created commands with the command statusses 163 164 165 <legal all> 166 */ 167 168 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 169 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 170 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 171 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 172 173 174 /* Description REO_STATUS_REQUIRED 175 176 Consumer: REO 177 Producer: SW 178 179 <enum 0 NoStatus> REO does not need to generate a status 180 TLV for the execution of this command 181 <enum 1 StatusRequired> REO shall generate a status TLV 182 for the execution of this command 183 184 <legal all> 185 */ 186 187 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 188 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 189 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 190 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 191 192 193 /* Description RESERVED_0A 194 195 <legal 0> 196 */ 197 198 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 199 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 200 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 201 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 202 203 204 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 205 206 Consumer: REO 207 Producer: SW 208 209 Address (lower 32 bits) of the REO queue descriptor 210 <legal all> 211 */ 212 213 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 214 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 215 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 216 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 217 218 219 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 220 221 Consumer: REO 222 Producer: SW 223 224 Address (upper 8 bits) of the REO queue descriptor 225 <legal all> 226 */ 227 228 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 229 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 230 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 231 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 232 233 234 /* Description UPDATE_RECEIVE_QUEUE_NUMBER 235 236 Consumer: REO 237 Producer: SW 238 When set, receive_queue_number from this command will be 239 updated in the descriptor. 240 <legal all> 241 */ 242 243 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 244 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 245 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 246 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 247 248 249 /* Description UPDATE_VLD 250 251 Consumer: REO 252 Producer: SW 253 254 When clear, REO will NOT update the VLD bit setting. For 255 this setting, SW MUST set the Flush_from_cache bit in this 256 command. 257 258 When set, VLD from this command will be updated in the descriptor. 259 260 <legal all> 261 */ 262 263 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 264 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 265 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 266 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 267 268 269 /* Description UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 270 271 Consumer: REO 272 Producer: SW 273 When set, Associated_link_descriptor_counter from this command 274 will be updated in the descriptor. 275 <legal all> 276 */ 277 278 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 279 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 280 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 281 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 282 283 284 /* Description UPDATE_DISABLE_DUPLICATE_DETECTION 285 286 Consumer: REO 287 Producer: SW 288 When set, Disable_duplicate_detection from this command 289 will be updated in the descriptor. 290 <legal all> 291 */ 292 293 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 294 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 295 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 296 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 297 298 299 /* Description UPDATE_SOFT_REORDER_ENABLE 300 301 Consumer: REO 302 Producer: SW 303 When set, Soft_reorder_enable from this command will be 304 updated in the descriptor. 305 <legal all> 306 */ 307 308 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 309 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 310 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 311 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 312 313 314 /* Description UPDATE_AC 315 316 Consumer: REO 317 Producer: SW 318 When set, AC from this command will be updated in the descriptor. 319 320 <legal all> 321 */ 322 323 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 324 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 325 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 326 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 327 328 329 /* Description UPDATE_BAR 330 331 Consumer: REO 332 Producer: SW 333 When set, BAR from this command will be updated in the descriptor. 334 335 <legal all> 336 */ 337 338 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 339 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 340 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 341 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 342 343 344 /* Description UPDATE_RTY 345 346 Consumer: REO 347 Producer: SW 348 When set, RTY from this command will be updated in the descriptor. 349 350 <legal all> 351 */ 352 353 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 354 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 355 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 356 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 357 358 359 /* Description UPDATE_CHK_2K_MODE 360 361 Consumer: REO 362 Producer: SW 363 When set, Chk_2k_mode from this command will be updated 364 in the descriptor. 365 <legal all> 366 */ 367 368 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 369 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 370 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 371 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 372 373 374 /* Description UPDATE_OOR_MODE 375 376 Consumer: REO 377 Producer: SW 378 When set, OOR_Mode from this command will be updated in 379 the descriptor. 380 <legal all> 381 */ 382 383 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 384 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 385 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 386 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 387 388 389 /* Description UPDATE_BA_WINDOW_SIZE 390 391 Consumer: REO 392 Producer: SW 393 When set, BA_window_size from this command will be updated 394 in the descriptor. 395 <legal all> 396 */ 397 398 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 399 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 400 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 401 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 402 403 404 /* Description UPDATE_PN_CHECK_NEEDED 405 406 Consumer: REO 407 Producer: SW 408 When set, Pn_check_needed from this command will be updated 409 in the descriptor. 410 <legal all> 411 */ 412 413 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 414 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 415 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 416 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 417 418 419 /* Description UPDATE_PN_SHALL_BE_EVEN 420 421 Consumer: REO 422 Producer: SW 423 When set, Pn_shall_be_even from this command will be updated 424 in the descriptor. 425 <legal all> 426 */ 427 428 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 429 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 430 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 431 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 432 433 434 /* Description UPDATE_PN_SHALL_BE_UNEVEN 435 436 Consumer: REO 437 Producer: SW 438 When set, Pn_shall_be_uneven from this command will be updated 439 in the descriptor. 440 <legal all> 441 */ 442 443 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 444 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 445 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 446 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 447 448 449 /* Description UPDATE_PN_HANDLING_ENABLE 450 451 Consumer: REO 452 Producer: SW 453 When set, Pn_handling_enable from this command will be updated 454 in the descriptor. 455 <legal all> 456 */ 457 458 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 459 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 460 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 461 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 462 463 464 /* Description UPDATE_PN_SIZE 465 466 Consumer: REO 467 Producer: SW 468 When set, Pn_size from this command will be updated in the 469 descriptor. 470 <legal all> 471 */ 472 473 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 474 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 475 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 476 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 477 478 479 /* Description UPDATE_IGNORE_AMPDU_FLAG 480 481 Consumer: REO 482 Producer: SW 483 When set, Ignore_ampdu_flag from this command will be updated 484 in the descriptor. 485 <legal all> 486 */ 487 488 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 489 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 490 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 491 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 492 493 494 /* Description UPDATE_SVLD 495 496 Consumer: REO 497 Producer: SW 498 When set, Svld from this command will be updated in the 499 descriptor. 500 <legal all> 501 */ 502 503 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 504 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 505 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 506 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 507 508 509 /* Description UPDATE_SSN 510 511 Consumer: REO 512 Producer: SW 513 When set, SSN from this command will be updated in the descriptor. 514 515 <legal all> 516 */ 517 518 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 519 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 520 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 521 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 522 523 524 /* Description UPDATE_SEQ_2K_ERROR_DETECTED_FLAG 525 526 Consumer: REO 527 Producer: SW 528 When set, Seq_2k_error_detected_flag from this command will 529 be updated in the descriptor. 530 <legal all> 531 */ 532 533 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 534 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 535 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 536 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 537 538 539 /* Description UPDATE_PN_ERROR_DETECTED_FLAG 540 541 Consumer: REO 542 Producer: SW 543 When set, pn_error_detected_flag from this command will 544 be updated in the descriptor. 545 <legal all> 546 */ 547 548 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 549 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 550 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 551 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 552 553 554 /* Description UPDATE_PN_VALID 555 556 Consumer: REO 557 Producer: SW 558 When set, pn_valid from this command will be updated in 559 the descriptor. 560 <legal all> 561 */ 562 563 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 564 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 565 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 566 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 567 568 569 /* Description UPDATE_PN 570 571 Consumer: REO 572 Producer: SW 573 When set, all pn_... fields from this command will be updated 574 in the descriptor. 575 <legal all> 576 */ 577 578 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 579 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 580 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 581 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 582 583 584 /* Description CLEAR_STAT_COUNTERS 585 586 Consumer: REO 587 Producer: SW 588 When set, REO will clear (=> set to 0) the following stat 589 counters in the REO_QUEUE_STRUCT 590 591 Last_rx_enqueue_TimeStamp 592 Last_rx_dequeue_Timestamp 593 Rx_bitmap (not a counter, but bitmap is cleared) 594 Timeout_count 595 Forward_due_to_bar_count 596 Duplicate_count 597 Frames_in_order_count 598 BAR_received_count 599 MPDU_Frames_processed_count 600 MSDU_Frames_processed_count 601 Total_processed_byte_count 602 Late_receive_MPDU_count 603 window_jump_2k 604 Hole_count 605 606 <legal all> 607 */ 608 609 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 610 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 611 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 612 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 613 614 615 /* Description RECEIVE_QUEUE_NUMBER 616 617 Field only valid when Update_receive_queue_number is set 618 619 620 Field value to be copied over into the RX_REO_QUEUE descriptor. 621 622 <legal all> 623 */ 624 625 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 626 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 627 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 628 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 629 630 631 /* Description VLD 632 633 Field only valid when Update_VLD is set 634 635 For Update_VLD set and VLD clear, SW MUST set the Flush_from_cache 636 bit in this command. 637 638 Field value to be copied over into the RX_REO_QUEUE descriptor. 639 640 <legal all> 641 */ 642 643 #define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 644 #define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 645 #define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 646 #define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 647 648 649 /* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER 650 651 Field only valid when Update_Associated_link_descriptor_counter 652 is set 653 654 Field value to be copied over into the RX_REO_QUEUE descriptor. 655 656 <legal all> 657 */ 658 659 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 660 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 661 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 662 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 663 664 665 /* Description DISABLE_DUPLICATE_DETECTION 666 667 Field only valid when Update_Disable_duplicate_detection 668 is set 669 670 Field value to be copied over into the RX_REO_QUEUE descriptor. 671 672 <legal all> 673 */ 674 675 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 676 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 677 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 678 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 679 680 681 /* Description SOFT_REORDER_ENABLE 682 683 Field only valid when Update_Soft_reorder_enable is set 684 685 Field value to be copied over into the RX_REO_QUEUE descriptor. 686 687 <legal all> 688 */ 689 690 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 691 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 692 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 693 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 694 695 696 /* Description AC 697 698 Field only valid when Update_AC is set 699 700 Field value to be copied over into the RX_REO_QUEUE descriptor. 701 702 <legal all> 703 */ 704 705 #define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 706 #define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 707 #define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 708 #define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 709 710 711 /* Description BAR 712 713 Field only valid when Update_BAR is set 714 715 Field value to be copied over into the RX_REO_QUEUE descriptor. 716 717 <legal all> 718 */ 719 720 #define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 721 #define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 722 #define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 723 #define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 724 725 726 /* Description RTY 727 728 Field only valid when Update_RTY is set 729 730 Field value to be copied over into the RX_REO_QUEUE descriptor. 731 732 <legal all> 733 */ 734 735 #define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 736 #define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 737 #define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 738 #define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 739 740 741 /* Description CHK_2K_MODE 742 743 Field only valid when Update_Chk_2k_Mode is set 744 745 Field value to be copied over into the RX_REO_QUEUE descriptor. 746 747 <legal all> 748 */ 749 750 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 751 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 752 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 753 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 754 755 756 /* Description OOR_MODE 757 758 Field only valid when Update_OOR_Mode is set 759 760 Field value to be copied over into the RX_REO_QUEUE descriptor. 761 762 <legal all> 763 */ 764 765 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 766 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 767 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 768 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 769 770 771 /* Description PN_CHECK_NEEDED 772 773 Field only valid when Update_Pn_check_needed is set 774 775 Field value to be copied over into the RX_REO_QUEUE descriptor. 776 777 <legal all> 778 */ 779 780 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 781 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 782 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 783 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 784 785 786 /* Description PN_SHALL_BE_EVEN 787 788 Field only valid when Update_Pn_shall_be_even is set 789 790 Field value to be copied over into the RX_REO_QUEUE descriptor. 791 792 <legal all> 793 */ 794 795 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 796 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 797 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 798 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 799 800 801 /* Description PN_SHALL_BE_UNEVEN 802 803 Field only valid when Update_Pn_shall_be_uneven is set 804 805 Field value to be copied over into the RX_REO_QUEUE descriptor. 806 807 <legal all> 808 */ 809 810 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 811 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 812 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 813 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 814 815 816 /* Description PN_HANDLING_ENABLE 817 818 Field only valid when Update_Pn_handling_enable is set 819 820 Field value to be copied over into the RX_REO_QUEUE descriptor. 821 822 <legal all> 823 */ 824 825 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 826 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 827 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 828 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 829 830 831 /* Description IGNORE_AMPDU_FLAG 832 833 Field only valid when Update_Ignore_ampdu_flag is set 834 835 Field value to be copied over into the RX_REO_QUEUE descriptor. 836 837 <legal all> 838 */ 839 840 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 841 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 842 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 843 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 844 845 846 /* Description BA_WINDOW_SIZE 847 848 Field only valid when Update_BA_window_size is set 849 850 Field value to be copied over into the RX_REO_QUEUE descriptor. 851 852 <legal all> 853 */ 854 855 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 856 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 857 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 858 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff 859 860 861 /* Description PN_SIZE 862 863 Field only valid when Update_Pn_size is set 864 865 Field value to be copied over into the RX_REO_QUEUE descriptor. 866 867 868 <enum 0 pn_size_24> 869 <enum 1 pn_size_48> 870 <enum 2 pn_size_128> 871 872 <legal 0-2> 873 */ 874 875 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 876 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 877 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 878 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 879 880 881 /* Description SVLD 882 883 Field only valid when Update_Svld is set 884 885 Field value to be copied over into the RX_REO_QUEUE descriptor. 886 887 <legal all> 888 */ 889 890 #define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 891 #define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 892 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 893 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 894 895 896 /* Description SSN 897 898 Field only valid when Update_SSN is set 899 900 Field value to be copied over into the RX_REO_QUEUE descriptor. 901 902 <legal all> 903 */ 904 905 #define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 906 #define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 907 #define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 908 #define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 909 910 911 /* Description SEQ_2K_ERROR_DETECTED_FLAG 912 913 Field only valid when Update_Seq_2k_error_detected_flag 914 is set 915 916 Field value to be copied over into the RX_REO_QUEUE descriptor. 917 918 <legal all> 919 */ 920 921 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 922 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 923 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 924 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 925 926 927 /* Description PN_ERROR_DETECTED_FLAG 928 929 Field only valid when Update_pn_error_detected_flag is set 930 931 932 Field value to be copied over into the RX_REO_QUEUE descriptor. 933 934 <legal all> 935 */ 936 937 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 938 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 939 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 940 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 941 942 943 /* Description PN_VALID 944 945 Field only valid when Update_pn_valid is set 946 947 Field value to be copied over into the RX_REO_QUEUE descriptor. 948 949 <legal all> 950 */ 951 952 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 953 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 954 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 955 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 956 957 958 /* Description FLUSH_FROM_CACHE 959 960 When set, REO shall, after finishing the execution of this 961 command, flush the related descriptor from the cache. 962 <legal all> 963 */ 964 965 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 966 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 967 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 968 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 969 970 971 /* Description RESERVED_4A 972 973 <legal 0> 974 */ 975 976 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 977 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 978 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 979 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 980 981 982 /* Description PN_31_0 983 984 Field only valid when Update_Pn is set 985 986 Field value to be copied over into the RX_REO_QUEUE descriptor. 987 988 <legal all> 989 */ 990 991 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 992 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 993 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 994 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 995 996 997 /* Description PN_63_32 998 999 Field only valid when Update_pn is set 1000 1001 Field value to be copied over into the RX_REO_QUEUE descriptor. 1002 1003 <legal all> 1004 */ 1005 1006 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 1007 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 1008 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 1009 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff 1010 1011 1012 /* Description PN_95_64 1013 1014 Field only valid when Update_pn is set 1015 1016 Field value to be copied over into the RX_REO_QUEUE descriptor. 1017 1018 <legal all> 1019 */ 1020 1021 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 1022 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 1023 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 1024 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 1025 1026 1027 /* Description PN_127_96 1028 1029 Field only valid when Update_pn is set 1030 1031 Field value to be copied over into the RX_REO_QUEUE descriptor. 1032 1033 <legal all> 1034 */ 1035 1036 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 1037 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 1038 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 1039 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff 1040 1041 1042 /* Description TLV64_PADDING 1043 1044 Automatic DWORD padding inserted while converting TLV32 1045 to TLV64 for 64 bit ARCH 1046 <legal 0> 1047 */ 1048 1049 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 1050 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 1051 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 1052 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 1053 1054 1055 1056 #endif // REO_UPDATE_RX_REO_QUEUE 1057