1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 18 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_reo_status_header.h" 23 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 24 25 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 26 27 28 struct reo_update_rx_reo_queue_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_reo_status_header status_header; 31 uint32_t reserved_2a : 32; // [31:0] 32 uint32_t reserved_3a : 32; // [31:0] 33 uint32_t reserved_4a : 32; // [31:0] 34 uint32_t reserved_5a : 32; // [31:0] 35 uint32_t reserved_6a : 32; // [31:0] 36 uint32_t reserved_7a : 32; // [31:0] 37 uint32_t reserved_8a : 32; // [31:0] 38 uint32_t reserved_9a : 32; // [31:0] 39 uint32_t reserved_10a : 32; // [31:0] 40 uint32_t reserved_11a : 32; // [31:0] 41 uint32_t reserved_12a : 32; // [31:0] 42 uint32_t reserved_13a : 32; // [31:0] 43 uint32_t reserved_14a : 32; // [31:0] 44 uint32_t reserved_15a : 32; // [31:0] 45 uint32_t reserved_16a : 32; // [31:0] 46 uint32_t reserved_17a : 32; // [31:0] 47 uint32_t reserved_18a : 32; // [31:0] 48 uint32_t reserved_19a : 32; // [31:0] 49 uint32_t reserved_20a : 32; // [31:0] 50 uint32_t reserved_21a : 32; // [31:0] 51 uint32_t reserved_22a : 32; // [31:0] 52 uint32_t reserved_23a : 32; // [31:0] 53 uint32_t reserved_24a : 32; // [31:0] 54 uint32_t reserved_25a : 28, // [27:0] 55 looping_count : 4; // [31:28] 56 #else 57 struct uniform_reo_status_header status_header; 58 uint32_t reserved_2a : 32; // [31:0] 59 uint32_t reserved_3a : 32; // [31:0] 60 uint32_t reserved_4a : 32; // [31:0] 61 uint32_t reserved_5a : 32; // [31:0] 62 uint32_t reserved_6a : 32; // [31:0] 63 uint32_t reserved_7a : 32; // [31:0] 64 uint32_t reserved_8a : 32; // [31:0] 65 uint32_t reserved_9a : 32; // [31:0] 66 uint32_t reserved_10a : 32; // [31:0] 67 uint32_t reserved_11a : 32; // [31:0] 68 uint32_t reserved_12a : 32; // [31:0] 69 uint32_t reserved_13a : 32; // [31:0] 70 uint32_t reserved_14a : 32; // [31:0] 71 uint32_t reserved_15a : 32; // [31:0] 72 uint32_t reserved_16a : 32; // [31:0] 73 uint32_t reserved_17a : 32; // [31:0] 74 uint32_t reserved_18a : 32; // [31:0] 75 uint32_t reserved_19a : 32; // [31:0] 76 uint32_t reserved_20a : 32; // [31:0] 77 uint32_t reserved_21a : 32; // [31:0] 78 uint32_t reserved_22a : 32; // [31:0] 79 uint32_t reserved_23a : 32; // [31:0] 80 uint32_t reserved_24a : 32; // [31:0] 81 uint32_t looping_count : 4, // [31:28] 82 reserved_25a : 28; // [27:0] 83 #endif 84 }; 85 86 87 /* Description STATUS_HEADER 88 89 Consumer: SW 90 Producer: REO 91 92 Details that can link this status with the original command. 93 It also contains info on how long REO took to execute this 94 command. 95 */ 96 97 98 /* Description REO_STATUS_NUMBER 99 100 Consumer: SW , DEBUG 101 Producer: REO 102 103 The value in this field is equal to value of the 'REO_CMD_Number' 104 field the REO command 105 106 This field helps to correlate the statuses with the REO 107 commands. 108 109 <legal all> 110 */ 111 112 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 113 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 114 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 115 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff 116 117 118 /* Description CMD_EXECUTION_TIME 119 120 Consumer: DEBUG 121 Producer: REO 122 123 The amount of time REO took to excecute the command. Note 124 that this time does not include the duration of the command 125 waiting in the command ring, before the execution started. 126 127 128 In us. 129 130 <legal all> 131 */ 132 133 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 134 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 135 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 136 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 137 138 139 /* Description REO_CMD_EXECUTION_STATUS 140 141 Consumer: DEBUG 142 Producer: REO 143 144 Execution status of the command. 145 146 <enum 0 reo_successful_execution> Command has successfully 147 be executed 148 <enum 1 reo_blocked_execution> Command could not be executed 149 as the queue or cache was blocked 150 <enum 2 reo_failed_execution> Command has encountered problems 151 when executing, like the queue descriptor not being valid. 152 None of the status fields in the entire STATUS TLV are valid. 153 154 <enum 3 reo_resource_blocked> Command is NOT executed because 155 one or more descriptors were blocked. This is SW programming 156 mistake. 157 None of the status fields in the entire STATUS TLV are valid. 158 159 160 <legal 0-3> 161 */ 162 163 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 164 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 165 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 166 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 167 168 169 /* Description RESERVED_0A 170 171 <legal 0> 172 */ 173 174 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 175 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 176 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 177 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 178 179 180 /* Description TIMESTAMP 181 182 Timestamp at the moment that this status report is written. 183 184 185 <legal all> 186 */ 187 188 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 189 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 190 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 191 #define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 192 193 194 /* Description RESERVED_2A 195 196 <legal 0> 197 */ 198 199 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 200 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 201 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 202 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff 203 204 205 /* Description RESERVED_3A 206 207 <legal 0> 208 */ 209 210 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 211 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 212 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 213 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 214 215 216 /* Description RESERVED_4A 217 218 <legal 0> 219 */ 220 221 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 222 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 223 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 224 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff 225 226 227 /* Description RESERVED_5A 228 229 <legal 0> 230 */ 231 232 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 233 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 234 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 235 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 236 237 238 /* Description RESERVED_6A 239 240 <legal 0> 241 */ 242 243 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 244 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 245 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 246 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff 247 248 249 /* Description RESERVED_7A 250 251 <legal 0> 252 */ 253 254 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 255 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 256 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 257 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 258 259 260 /* Description RESERVED_8A 261 262 <legal 0> 263 */ 264 265 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 266 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 267 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 268 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff 269 270 271 /* Description RESERVED_9A 272 273 <legal 0> 274 */ 275 276 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 277 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 278 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 279 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 280 281 282 /* Description RESERVED_10A 283 284 <legal 0> 285 */ 286 287 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 288 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 289 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 290 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff 291 292 293 /* Description RESERVED_11A 294 295 <legal 0> 296 */ 297 298 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 299 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 300 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 301 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 302 303 304 /* Description RESERVED_12A 305 306 <legal 0> 307 */ 308 309 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 310 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 311 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 312 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff 313 314 315 /* Description RESERVED_13A 316 317 <legal 0> 318 */ 319 320 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 321 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 322 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 323 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 324 325 326 /* Description RESERVED_14A 327 328 <legal 0> 329 */ 330 331 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 332 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 333 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 334 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff 335 336 337 /* Description RESERVED_15A 338 339 <legal 0> 340 */ 341 342 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 343 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 344 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 345 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 346 347 348 /* Description RESERVED_16A 349 350 <legal 0> 351 */ 352 353 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 354 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 355 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 356 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff 357 358 359 /* Description RESERVED_17A 360 361 <legal 0> 362 */ 363 364 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 365 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 366 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 367 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 368 369 370 /* Description RESERVED_18A 371 372 <legal 0> 373 */ 374 375 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 376 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 377 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 378 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff 379 380 381 /* Description RESERVED_19A 382 383 <legal 0> 384 */ 385 386 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 387 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 388 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 389 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 390 391 392 /* Description RESERVED_20A 393 394 <legal 0> 395 */ 396 397 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 398 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 399 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 400 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff 401 402 403 /* Description RESERVED_21A 404 405 <legal 0> 406 */ 407 408 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 409 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 410 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 411 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 412 413 414 /* Description RESERVED_22A 415 416 <legal 0> 417 */ 418 419 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 420 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 421 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 422 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff 423 424 425 /* Description RESERVED_23A 426 427 <legal 0> 428 */ 429 430 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 431 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 432 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 433 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 434 435 436 /* Description RESERVED_24A 437 438 <legal 0> 439 */ 440 441 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 442 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 443 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 444 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff 445 446 447 /* Description RESERVED_25A 448 449 <legal 0> 450 */ 451 452 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 453 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 454 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 455 #define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 456 457 458 /* Description LOOPING_COUNT 459 460 A count value that indicates the number of times the producer 461 of entries into this Ring has looped around the ring. 462 At initialization time, this value is set to 0. On the first 463 loop, this value is set to 1. After the max value is reached 464 allowed by the number of bits for this field, the count 465 value continues with 0 again. 466 467 In case SW is the consumer of the ring entries, it can use 468 this field to figure out up to where the producer of entries 469 has created new entries. This eliminates the need to check 470 where the "head pointer' of the ring is located once the 471 SW starts processing an interrupt indicating that new entries 472 have been put into this ring... 473 474 Also note that SW if it wants only needs to look at the 475 LSB bit of this count value. 476 <legal all> 477 */ 478 479 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 480 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 481 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 482 #define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 483 484 485 486 #endif // REO_UPDATE_RX_REO_QUEUE_STATUS 487