1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RESPONSE_END_STATUS_H_ 18 #define _RESPONSE_END_STATUS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phytx_abort_request_info.h" 23 #define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 24 25 #define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 26 27 28 struct response_end_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 uint32_t coex_bt_tx_while_wlan_tx : 1, // [0:0] 31 coex_wan_tx_while_wlan_tx : 1, // [1:1] 32 coex_wlan_tx_while_wlan_tx : 1, // [2:2] 33 global_data_underflow_warning : 1, // [3:3] 34 response_transmit_status : 4, // [7:4] 35 phytx_pkt_end_info_valid : 1, // [8:8] 36 phytx_abort_request_info_valid : 1, // [9:9] 37 generated_response : 3, // [12:10] 38 mba_user_count : 7, // [19:13] 39 mba_fake_bitmap_count : 7, // [26:20] 40 coex_based_tx_bw : 3, // [29:27] 41 trig_response_related : 1, // [30:30] 42 dpdtrain_done : 1; // [31:31] 43 struct phytx_abort_request_info phytx_abort_request_info_details; 44 uint16_t cbf_segment_request_mask : 8, // [23:16] 45 cbf_segment_sent_mask : 8; // [31:24] 46 uint32_t underflow_mpdu_count : 9, // [8:0] 47 data_underflow_warning : 2, // [10:9] 48 phy_tx_gain_setting : 8, // [18:11] 49 timing_status : 2, // [20:19] 50 only_null_delim_sent : 1, // [21:21] 51 brp_info_valid : 1, // [22:22] 52 reserved_2a : 9; // [31:23] 53 uint32_t mu_response_bitmap_31_0 : 32; // [31:0] 54 uint32_t mu_response_bitmap_36_32 : 5, // [4:0] 55 reserved_4a : 11, // [15:5] 56 transmit_delay : 16; // [31:16] 57 uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] 58 start_of_frame_timestamp_31_16 : 16; // [31:16] 59 uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] 60 end_of_frame_timestamp_31_16 : 16; // [31:16] 61 uint32_t tx_group_delay : 12, // [11:0] 62 reserved_7a : 4, // [15:12] 63 tpc_dbg_info_cmn_15_0 : 16; // [31:16] 64 uint32_t tpc_dbg_info_31_16 : 16, // [15:0] 65 tpc_dbg_info_47_32 : 16; // [31:16] 66 uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] 67 tpc_dbg_info_chn1_31_16 : 16; // [31:16] 68 uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] 69 tpc_dbg_info_chn1_63_48 : 16; // [31:16] 70 uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] 71 tpc_dbg_info_chn2_15_0 : 16; // [31:16] 72 uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] 73 tpc_dbg_info_chn2_47_32 : 16; // [31:16] 74 uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] 75 tpc_dbg_info_chn2_79_64 : 16; // [31:16] 76 uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] 77 phytx_tx_end_sw_info_31_16 : 16; // [31:16] 78 uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] 79 phytx_tx_end_sw_info_63_48 : 16; // [31:16] 80 uint32_t addr1_31_0 : 32; // [31:0] 81 uint32_t addr1_47_32 : 16, // [15:0] 82 addr2_15_0 : 16; // [31:16] 83 uint32_t addr2_47_16 : 32; // [31:0] 84 uint32_t addr3_31_0 : 32; // [31:0] 85 uint32_t addr3_47_32 : 16, // [15:0] 86 ranging : 1, // [16:16] 87 secure : 1, // [17:17] 88 ranging_ftm_frame_sent : 1, // [18:18] 89 reserved_20a : 13; // [31:19] 90 uint32_t tlv64_padding : 32; // [31:0] 91 #else 92 uint32_t dpdtrain_done : 1, // [31:31] 93 trig_response_related : 1, // [30:30] 94 coex_based_tx_bw : 3, // [29:27] 95 mba_fake_bitmap_count : 7, // [26:20] 96 mba_user_count : 7, // [19:13] 97 generated_response : 3, // [12:10] 98 phytx_abort_request_info_valid : 1, // [9:9] 99 phytx_pkt_end_info_valid : 1, // [8:8] 100 response_transmit_status : 4, // [7:4] 101 global_data_underflow_warning : 1, // [3:3] 102 coex_wlan_tx_while_wlan_tx : 1, // [2:2] 103 coex_wan_tx_while_wlan_tx : 1, // [1:1] 104 coex_bt_tx_while_wlan_tx : 1; // [0:0] 105 uint32_t cbf_segment_sent_mask : 8, // [31:24] 106 cbf_segment_request_mask : 8; // [23:16] 107 struct phytx_abort_request_info phytx_abort_request_info_details; 108 uint32_t reserved_2a : 9, // [31:23] 109 brp_info_valid : 1, // [22:22] 110 only_null_delim_sent : 1, // [21:21] 111 timing_status : 2, // [20:19] 112 phy_tx_gain_setting : 8, // [18:11] 113 data_underflow_warning : 2, // [10:9] 114 underflow_mpdu_count : 9; // [8:0] 115 uint32_t mu_response_bitmap_31_0 : 32; // [31:0] 116 uint32_t transmit_delay : 16, // [31:16] 117 reserved_4a : 11, // [15:5] 118 mu_response_bitmap_36_32 : 5; // [4:0] 119 uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] 120 start_of_frame_timestamp_15_0 : 16; // [15:0] 121 uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] 122 end_of_frame_timestamp_15_0 : 16; // [15:0] 123 uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] 124 reserved_7a : 4, // [15:12] 125 tx_group_delay : 12; // [11:0] 126 uint32_t tpc_dbg_info_47_32 : 16, // [31:16] 127 tpc_dbg_info_31_16 : 16; // [15:0] 128 uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] 129 tpc_dbg_info_chn1_15_0 : 16; // [15:0] 130 uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] 131 tpc_dbg_info_chn1_47_32 : 16; // [15:0] 132 uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] 133 tpc_dbg_info_chn1_79_64 : 16; // [15:0] 134 uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] 135 tpc_dbg_info_chn2_31_16 : 16; // [15:0] 136 uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] 137 tpc_dbg_info_chn2_63_48 : 16; // [15:0] 138 uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] 139 phytx_tx_end_sw_info_15_0 : 16; // [15:0] 140 uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] 141 phytx_tx_end_sw_info_47_32 : 16; // [15:0] 142 uint32_t addr1_31_0 : 32; // [31:0] 143 uint32_t addr2_15_0 : 16, // [31:16] 144 addr1_47_32 : 16; // [15:0] 145 uint32_t addr2_47_16 : 32; // [31:0] 146 uint32_t addr3_31_0 : 32; // [31:0] 147 uint32_t reserved_20a : 13, // [31:19] 148 ranging_ftm_frame_sent : 1, // [18:18] 149 secure : 1, // [17:17] 150 ranging : 1, // [16:16] 151 addr3_47_32 : 16; // [15:0] 152 uint32_t tlv64_padding : 32; // [31:0] 153 #endif 154 }; 155 156 157 /* Description COEX_BT_TX_WHILE_WLAN_TX 158 159 When set, a BT tx coex event started while wlan was in the 160 middle of response transmission. 161 162 Field set when coex_status_broadcast TLV received with bt 163 tx activity set and WLAN tx ongoing. 164 <legal all> 165 */ 166 167 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 168 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 169 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 170 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 171 172 173 /* Description COEX_WAN_TX_WHILE_WLAN_TX 174 175 When set, a WAN tx coex event started while wlan was in 176 the middle of response transmission. 177 178 Field set when coex_status_broadcast TLV received with WAN 179 tx activity set and WLAN tx ongoing 180 <legal all> 181 */ 182 183 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 184 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 185 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 186 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 187 188 189 /* Description COEX_WLAN_TX_WHILE_WLAN_TX 190 191 When set, a WLAN tx coex event started while wlan was in 192 the middle of response transmission. 193 194 Field set when coex_status_broadcast TLV received with WLAN 195 tx activity set and WLAN tx ongoing 196 <legal all> 197 */ 198 199 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 200 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 201 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 202 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 203 204 205 /* Description GLOBAL_DATA_UNDERFLOW_WARNING 206 207 Consumer: SCH/SW 208 Producer: TXPCU 209 210 When set, during response transmission a data underflow 211 occurred for one or more users.<legal all> 212 */ 213 214 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 215 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 216 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 217 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 218 219 220 /* Description RESPONSE_TRANSMIT_STATUS 221 222 <enum 0 response_ok> Successful transmission of the selfgen 223 response frame 224 <enum 1 response_coex_soft_abort> Set if transmission is 225 terminated because of the coex soft abort. 226 <enum 2 response_phy_err> Set if transmission is terminated 227 because PHY generated an abort request 228 <enum 3 response_flush_received> Set if transmission is 229 terminated because RXPCU received a flush request 230 <enum 4 response_other_err> Set if transmission is terminated 231 because of other errors within the RXPCU 232 <legal 0-4> 233 */ 234 235 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 236 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 237 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 238 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 239 240 241 /* Description PHYTX_PKT_END_INFO_VALID 242 243 All the fields originating from PHYTX_PKT_END TLV contain 244 valid info 245 246 Note that when "trig_response_related" is set, this bit 247 will often not be set as the trigger response contents might 248 have come from a scheduling command which is not reported 249 as part of the 'response' transmission. 250 */ 251 252 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 253 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 254 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 255 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 256 257 258 /* Description PHYTX_ABORT_REQUEST_INFO_VALID 259 260 Field Phytx_abort_request_info_details contains valid info 261 262 */ 263 264 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 265 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 266 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 267 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 268 269 270 /* Description GENERATED_RESPONSE 271 272 The generated response frame 273 274 <enum 0 selfgen_ACK> TXPCU generated an ACK response. Note 275 that this can be part of a trigger response. In that case 276 bit trig_response_related will be set as well. 277 278 <enum 1 selfgen_CTS> TXPCU generated an CTS response. Note 279 that this can be part of a trigger response. In that case 280 bit trig_response_related will be set as well. 281 282 <enum 2 selfgen_BA> TXPCU generated a BA response. Note 283 that this can be part of a trigger response. In that case 284 bit trig_response_related will be set as well. 285 286 <enum 3 selfgen_MBA> TXPCU generated an M BA response. Note 287 that this can be part of a trigger response. In that case 288 bit trig_response_related will be set as well. 289 290 <enum 4 selfgen_CBF> TXPCU generated a CBF response. Note 291 that this can be part of a trigger response. In that case 292 bit trig_response_related will be set as well. 293 294 <enum 5 selfgen_other_trig_response> 295 TXPCU generated a trigger related response of a type not 296 specified above. Note that in this case bit trig_response_related 297 will be set as well. 298 This e-num will also be used when TXPCU has been programmed 299 to overwrite it's own self gen response generation, and 300 wait for the response to come from SCH.. 301 Also applicable for basic trigger response. 302 303 <enum 6 selfgen_NDP_LMR> TXPCU generated a self-gen NDP 304 followed by a self-gen LMR for the ranging NDPA followed 305 by NDP received by RXPCU. 306 307 <legal 0-6> 308 */ 309 310 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 311 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 312 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 313 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 314 315 316 /* Description MBA_USER_COUNT 317 318 Field only valid in case of selfgen_MBA 319 320 The number of users included in the generated MBA 321 322 Note that this value will be the same as in TLV/field: RESPONSE_START_STATUS.response_STA_count 323 324 325 <legal all> 326 */ 327 328 #define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 329 #define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 330 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 331 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 332 333 334 /* Description MBA_FAKE_BITMAP_COUNT 335 336 Field only valid in case of MU OFDMA selfgen_MBA 337 338 The number of users for which RXPCU did not have a bitmap, 339 and thus provided a 'fake bitmap' 340 <legal all> 341 */ 342 343 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 344 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 345 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 346 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 347 348 349 /* Description COEX_BASED_TX_BW 350 351 This is the transmit bandwidth value 352 that is granted by Coex for the response frame 353 354 <enum 0 20_mhz>20 Mhz BW 355 <enum 1 40_mhz>40 Mhz BW 356 <enum 2 80_mhz>80 Mhz BW 357 <enum 3 160_mhz>160 Mhz BW 358 <enum 4 320_mhz>320 Mhz BW 359 <enum 5 240_mhz>240 Mhz BW 360 */ 361 362 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 363 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 364 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 365 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 366 367 368 /* Description TRIG_RESPONSE_RELATED 369 370 When set, this TLV is generated by TXPCU in the context 371 of a response transmission to a received trigger frame. 372 373 <legal all> 374 */ 375 376 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 377 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 378 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 379 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 380 381 382 /* Description DPDTRAIN_DONE 383 384 Field only valid when PHYTX_PKT_END_info_valid is set 385 386 For DPD Training packets, this bit is set to indicate that 387 DPD Training was successfully run to completion. Also 388 reused by Implicit BF Calibration Packets. This bit is intended 389 for debug purposes. 390 <legal all> 391 */ 392 393 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 394 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 395 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 396 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 397 398 399 /* Description PHYTX_ABORT_REQUEST_INFO_DETAILS 400 401 Field only valid when PHYTX_ABORT_REQUEST_info_valid is 402 set 403 404 The reason why PHYTX is requested an abort 405 */ 406 407 408 /* Description PHYTX_ABORT_REASON 409 410 Reason for early termination of TX packet by the PHY 411 412 <enum_type PHYTX_ABORT_ENUM> 413 */ 414 415 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 416 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 417 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 418 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 419 420 421 /* Description USER_NUMBER 422 423 For some errors, the user for which this error was detected 424 can be indicated in this field. 425 <legal 0-36> 426 */ 427 428 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 429 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 430 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 431 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 432 433 434 /* Description RESERVED 435 436 <legal 0> 437 */ 438 439 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 440 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 441 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 442 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 443 444 445 /* Description CBF_SEGMENT_REQUEST_MASK 446 447 Field only valid when brp_info_valid is set. 448 449 Field equal to the 'Feedback Segment Retransmission Bitmap' 450 from the Beamform Report Poll frame OR Beamform Report Poll 451 Trigger frame 452 453 Bit 0 represents segment 0 454 Bit 1 represents segment 1 455 Etc. 456 457 1'b1: Segment is requested 458 1'b0: Segment is NOT requested 459 460 <legal all> 461 */ 462 463 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 464 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 465 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 466 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 467 468 469 /* Description CBF_SEGMENT_SENT_MASK 470 471 Field only valid when brp_info_valid is set. 472 473 Bit 0 represents segment 0 474 Bit 1 represents segment 1 475 Etc. 476 477 1'b1: Segment is sent 478 1'b0: Segment is not sent 479 480 <legal all> 481 */ 482 483 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 484 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 485 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 486 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 487 488 489 /* Description UNDERFLOW_MPDU_COUNT 490 491 The MPDU count transmitted when the first underrun condition 492 was detected 493 <legal 0-256> 494 */ 495 496 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 497 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 498 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 499 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 500 501 502 /* Description DATA_UNDERFLOW_WARNING 503 504 Mac data underflow warning 505 506 <enum 0 no_data_underrun> No data underflow 507 <enum 1 data_underrun_between_mpdu> PCU experienced data 508 underflow in between MPDUs 509 <enum 2 data_underrun_within_mpdu> PCU experienced data 510 underflow within an MPDU 511 <legal 0-2> 512 */ 513 514 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 515 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 516 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 517 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 518 519 520 /* Description PHY_TX_GAIN_SETTING 521 522 PHYTX_PKT_END info 523 524 Field only valid when PHYTX_PKT_END_info_valid is set 525 526 The gain setting that the PHY used for this last PPDU transmission 527 528 */ 529 530 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 531 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 532 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 533 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 534 535 536 /* Description TIMING_STATUS 537 538 PHYTX_PKT_END info 539 540 Field only valid when PHYTX_PKT_END_info_valid is set 541 542 <enum 0 No_tx_timing_request> The MAC did not request for 543 the transmission to start at a particular time 544 <enum 1 successful_tx_timing > MAC did request for transmission 545 to start at a particular time and PHY was able to do so. 546 547 <enum 2 tx_timing_not_honoured> PHY was not able to honour 548 the requested transmit time by the MAC. The transmission 549 started later, and field transmit_delay indicates how much 550 later. 551 <legal 0-2> 552 */ 553 554 #define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 555 #define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 556 #define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 557 #define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 558 559 560 /* Description ONLY_NULL_DELIM_SENT 561 562 Field only valid when "trig_response_related" is set. 563 564 When set, TXPCU only sent NULL delimiters to the PHY for 565 the entire duration of the trigger response time. 566 567 Note that SCH does not evaluate this field. It is only for 568 SW to look at. 569 570 Setting this bit can only happen when a trigger is received, 571 and either the trigger allocated an incorrectly small duration, 572 or SW had not programmed a response scheduler command in 573 time to respond, which may not comply with the 11ax IEEE 574 spec. 575 576 <legal all> 577 */ 578 579 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 580 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 581 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 582 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 583 584 585 /* Description BRP_INFO_VALID 586 587 When set, TXPCU sent CBF segments. 588 589 Fields cbf_segment_request_mask and cbf_segment_sent_mask 590 contain valid info. 591 592 <legal all> 593 */ 594 595 #define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 596 #define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 597 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 598 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 599 600 601 /* Description RESERVED_2A 602 603 <legal 0> 604 */ 605 606 #define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 607 #define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 608 #define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 609 #define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 610 611 612 /* Description MU_RESPONSE_BITMAP_31_0 613 614 Bit 0 represents user 0 615 Bit 1 represents user 1 616 ... 617 When set, at least 1 MPDU from this user has been properly 618 received => FCS OK 619 620 TODO: remove these 621 Field can not be filled in with the self generated response 622 623 */ 624 625 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 626 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 627 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 628 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 629 630 631 /* Description MU_RESPONSE_BITMAP_36_32 632 633 Bit 0 represents user 32 634 Bit 1 represents user 33 635 ... 636 When set, at least 1 MPDU from this user has been properly 637 received => FCS OK 638 TODO: remove these 639 Field can not be filled in with the self generated response 640 641 Note: Received_response already goes to SW, so probably 642 no need to copy this bitmap info to TX_FES_STATUS TLV. 643 */ 644 645 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 646 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 647 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 648 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f 649 650 651 /* Description RESERVED_4A 652 653 <legal 0> 654 */ 655 656 #define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 657 #define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 658 #define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 659 #define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 660 661 662 /* Description TRANSMIT_DELAY 663 664 PHYTX_PKT_END info 665 666 Field only valid when PHYTX_PKT_END_info_valid is set 667 668 The number of 480 MHz clock cycles that the transmission 669 started after the actual requested transmit start time. 670 671 Value saturates at 0xFFFF 672 <legal all> 673 */ 674 675 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 676 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 677 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 678 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 679 680 681 /* Description START_OF_FRAME_TIMESTAMP_15_0 682 683 PHYTX_PKT_END info 684 685 Field only valid when PHYTX_PKT_END_info_valid is set 686 687 bits 15:0 of a 64 bit time stamp 688 Start of frame in the medium @960 MHz 689 <legal all> 690 */ 691 692 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 693 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 694 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 695 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 696 697 698 /* Description START_OF_FRAME_TIMESTAMP_31_16 699 700 PHYTX_PKT_END info 701 702 Field only valid when PHYTX_PKT_END_info_valid is set 703 704 bits 31:16 of a 64 bit time stamp 705 Start of frame in the medium @960 MHz 706 <legal all> 707 */ 708 709 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 710 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 711 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 712 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 713 714 715 /* Description END_OF_FRAME_TIMESTAMP_15_0 716 717 PHYTX_PKT_END info 718 719 Field only valid when PHYTX_PKT_END_info_valid is set 720 721 bits 15:0 of a 64 bit time stamp 722 End of frame in the medium @960 MHz 723 <legal all> 724 */ 725 726 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 727 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 728 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 729 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 730 731 732 /* Description END_OF_FRAME_TIMESTAMP_31_16 733 734 PHYTX_PKT_END info 735 736 Field only valid when PHYTX_PKT_END_info_valid is set 737 738 bits 31:16 of a 64 bit time stamp 739 End of frame in the medium @960 MHz 740 <legal all> 741 */ 742 743 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 744 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 745 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 746 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 747 748 749 /* Description TX_GROUP_DELAY 750 751 PHYTX_PKT_END info 752 753 Field only valid when PHYTX_PKT_END_info_valid is set 754 755 Group delay on TxTD+PHYRF path for this PPDU (packet BW 756 dependent), useful for RTT 757 758 Unit is 960MHz cycles. 759 <legal all> 760 */ 761 762 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 763 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 764 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 765 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 766 767 768 /* Description RESERVED_7A 769 770 <legal 0> 771 */ 772 773 #define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 774 #define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 775 #define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 776 #define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 777 778 779 /* Description TPC_DBG_INFO_CMN_15_0 780 781 PHYTX_PKT_END info 782 783 Field only valid when PHYTX_PKT_END_info_valid is set 784 785 Some TPC debug info that PHY can pass back to MAC FW 786 <legal all> 787 */ 788 789 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 790 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 791 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 792 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 793 794 795 /* Description TPC_DBG_INFO_31_16 796 797 PHYTX_PKT_END info 798 799 Field only valid when PHYTX_PKT_END_info_valid is set 800 801 Some TPC debug info that PHY can pass back to MAC FW 802 <legal all> 803 */ 804 805 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 806 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 807 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 808 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff 809 810 811 /* Description TPC_DBG_INFO_47_32 812 813 PHYTX_PKT_END info 814 815 Field only valid when PHYTX_PKT_END_info_valid is set 816 817 Some TPC debug infothat PHY can pass back to MAC FW 818 <legal all> 819 */ 820 821 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 822 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 823 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 824 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 825 826 827 /* Description TPC_DBG_INFO_CHN1_15_0 828 829 PHYTX_PKT_END info 830 831 Field only valid when PHYTX_PKT_END_info_valid is set 832 833 Some per-chain TPC debug info for the first selected chain 834 that PHY can pass back to MAC FW 835 <legal all> 836 */ 837 838 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 839 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 840 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 841 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 842 843 844 /* Description TPC_DBG_INFO_CHN1_31_16 845 846 PHYTX_PKT_END info 847 848 Field only valid when PHYTX_PKT_END_info_valid is set 849 850 Some per-chain TPC debug info for the first selected chain 851 that PHY can pass back to MAC FW 852 <legal all> 853 */ 854 855 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 856 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 857 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 858 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 859 860 861 /* Description TPC_DBG_INFO_CHN1_47_32 862 863 PHYTX_PKT_END info 864 865 Field only valid when PHYTX_PKT_END_info_valid is set 866 867 Some per-chain TPC debug info for the first selected chain 868 that PHY can pass back to MAC FW 869 <legal all> 870 */ 871 872 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 873 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 874 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 875 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 876 877 878 /* Description TPC_DBG_INFO_CHN1_63_48 879 880 PHYTX_PKT_END info 881 882 Field only valid when PHYTX_PKT_END_info_valid is set 883 884 Some per-chain TPC debug info for the first selected chain 885 that PHY can pass back to MAC FW 886 <legal all> 887 */ 888 889 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 890 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 891 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 892 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 893 894 895 /* Description TPC_DBG_INFO_CHN1_79_64 896 897 PHYTX_PKT_END info 898 899 Field only valid when PHYTX_PKT_END_info_valid is set 900 901 Some per-chain TPC debug info for the first selected chain 902 that PHY can pass back to MAC FW 903 <legal all> 904 */ 905 906 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 907 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 908 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 909 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 910 911 912 /* Description TPC_DBG_INFO_CHN2_15_0 913 914 PHYTX_PKT_END info 915 916 Field only valid when PHYTX_PKT_END_info_valid is set 917 918 Some per-chain TPC debug info for the second selected chain 919 that PHY can pass back to MAC FW 920 <legal all> 921 */ 922 923 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 924 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 925 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 926 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 927 928 929 /* Description TPC_DBG_INFO_CHN2_31_16 930 931 PHYTX_PKT_END info 932 933 Field only valid when PHYTX_PKT_END_info_valid is set 934 935 Some per-chain TPC debug info for the second selected chain 936 that PHY can pass back to MAC FW 937 <legal all> 938 */ 939 940 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 941 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 942 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 943 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 944 945 946 /* Description TPC_DBG_INFO_CHN2_47_32 947 948 PHYTX_PKT_END info 949 950 Field only valid when PHYTX_PKT_END_info_valid is set 951 952 Some per-chain TPC debug info for the second selected chain 953 that PHY can pass back to MAC FW 954 <legal all> 955 */ 956 957 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 958 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 959 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 960 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 961 962 963 /* Description TPC_DBG_INFO_CHN2_63_48 964 965 PHYTX_PKT_END info 966 967 Field only valid when PHYTX_PKT_END_info_valid is set 968 969 Some per-chain TPC debug info for the second selected chain 970 that PHY can pass back to MAC FW 971 <legal all> 972 */ 973 974 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 975 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 976 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 977 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 978 979 980 /* Description TPC_DBG_INFO_CHN2_79_64 981 982 PHYTX_PKT_END info 983 984 Field only valid when PHYTX_PKT_END_info_valid is set 985 986 Some per-chain TPC debug info for the second selected chain 987 that PHY can pass back to MAC FW 988 <legal all> 989 */ 990 991 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 992 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 993 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 994 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 995 996 997 /* Description PHYTX_TX_END_SW_INFO_15_0 998 999 PHYTX_PKT_END info 1000 1001 Field only valid when PHYTX_PKT_END_info_valid is set 1002 1003 Some PHY status data that PHY microcode can pass back to 1004 MAC FW, for any future requests, e.g. any DMA download 1005 time 1006 <legal all> 1007 */ 1008 1009 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 1010 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 1011 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 1012 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 1013 1014 1015 /* Description PHYTX_TX_END_SW_INFO_31_16 1016 1017 PHYTX_PKT_END info 1018 1019 Field only valid when PHYTX_PKT_END_info_valid is set 1020 1021 Some PHY status data that PHY microcode can pass back to 1022 MAC FW, for any future requests, e.g. any DMA download 1023 time 1024 <legal all> 1025 */ 1026 1027 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 1028 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 1029 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 1030 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 1031 1032 1033 /* Description PHYTX_TX_END_SW_INFO_47_32 1034 1035 PHYTX_PKT_END info 1036 1037 Field only valid when PHYTX_PKT_END_info_valid is set 1038 1039 Some PHY status data that PHY microcode can pass back to 1040 MAC FW, for any future requests, e.g. any DMA download 1041 time 1042 <legal all> 1043 */ 1044 1045 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 1046 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 1047 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 1048 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 1049 1050 1051 /* Description PHYTX_TX_END_SW_INFO_63_48 1052 1053 PHYTX_PKT_END info 1054 1055 Field only valid when PHYTX_PKT_END_info_valid is set 1056 1057 Some PHY status data that PHY microcode can pass back to 1058 MAC FW, for any future requests, e.g. any DMA download 1059 time 1060 <legal all> 1061 */ 1062 1063 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 1064 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 1065 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 1066 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 1067 1068 1069 /* Description ADDR1_31_0 1070 1071 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1072 1073 */ 1074 1075 #define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 1076 #define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 1077 #define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 1078 #define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff 1079 1080 1081 /* Description ADDR1_47_32 1082 1083 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1084 1085 */ 1086 1087 #define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 1088 #define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 1089 #define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 1090 #define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 1091 1092 1093 /* Description ADDR2_15_0 1094 1095 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1096 1097 */ 1098 1099 #define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 1100 #define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 1101 #define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 1102 #define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 1103 1104 1105 /* Description ADDR2_47_16 1106 1107 To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO 1108 1109 */ 1110 1111 #define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 1112 #define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 1113 #define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 1114 #define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff 1115 1116 1117 /* Description ADDR3_31_0 1118 1119 To be copied over from TX_CBF_INFO 1120 */ 1121 1122 #define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 1123 #define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 1124 #define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 1125 #define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 1126 1127 1128 /* Description ADDR3_47_32 1129 1130 To be copied over from TX_CBF_INFO 1131 */ 1132 1133 #define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 1134 #define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 1135 #define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 1136 #define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff 1137 1138 1139 /* Description RANGING 1140 1141 To be copied over from TX_CBF_INFO: Set to 1 if the status 1142 is generated due to an active ranging session (.11az) 1143 */ 1144 1145 #define RESPONSE_END_STATUS_RANGING_OFFSET 0x0000000000000050 1146 #define RESPONSE_END_STATUS_RANGING_LSB 16 1147 #define RESPONSE_END_STATUS_RANGING_MSB 16 1148 #define RESPONSE_END_STATUS_RANGING_MASK 0x0000000000010000 1149 1150 1151 /* Description SECURE 1152 1153 To be copied over from TX_CBF_INFO: Only valid if Ranging 1154 is set to 1, this indicates if the current ranging session 1155 is secure. 1156 */ 1157 1158 #define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 1159 #define RESPONSE_END_STATUS_SECURE_LSB 17 1160 #define RESPONSE_END_STATUS_SECURE_MSB 17 1161 #define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 1162 1163 1164 /* Description RANGING_FTM_FRAME_SENT 1165 1166 Only valid if Ranging is set to 1 1167 1168 TXPCU sets this bit if an FTM frame aggregated with an LMR 1169 was sent. 1170 */ 1171 1172 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 1173 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 1174 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 1175 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 1176 1177 1178 /* Description RESERVED_20A 1179 1180 <legal 0> 1181 */ 1182 1183 #define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 1184 #define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 1185 #define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 1186 #define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 1187 1188 1189 /* Description TLV64_PADDING 1190 1191 Automatic DWORD padding inserted while converting TLV32 1192 to TLV64 for 64 bit ARCH 1193 <legal 0> 1194 */ 1195 1196 #define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 1197 #define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 1198 #define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 1199 #define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 1200 1201 1202 1203 #endif // RESPONSE_END_STATUS 1204