1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_ATTENTION_H_ 18 #define _RX_ATTENTION_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_ATTENTION 4 23 24 #define NUM_OF_QWORDS_RX_ATTENTION 2 25 26 27 struct rx_attention { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 30 sw_frame_group_id : 7, // [8:2] 31 reserved_0 : 7, // [15:9] 32 phy_ppdu_id : 16; // [31:16] 33 uint32_t first_mpdu : 1, // [0:0] 34 reserved_1a : 1, // [1:1] 35 mcast_bcast : 1, // [2:2] 36 ast_index_not_found : 1, // [3:3] 37 ast_index_timeout : 1, // [4:4] 38 power_mgmt : 1, // [5:5] 39 non_qos : 1, // [6:6] 40 null_data : 1, // [7:7] 41 mgmt_type : 1, // [8:8] 42 ctrl_type : 1, // [9:9] 43 more_data : 1, // [10:10] 44 eosp : 1, // [11:11] 45 a_msdu_error : 1, // [12:12] 46 fragment_flag : 1, // [13:13] 47 order : 1, // [14:14] 48 cce_match : 1, // [15:15] 49 overflow_err : 1, // [16:16] 50 msdu_length_err : 1, // [17:17] 51 tcp_udp_chksum_fail : 1, // [18:18] 52 ip_chksum_fail : 1, // [19:19] 53 sa_idx_invalid : 1, // [20:20] 54 da_idx_invalid : 1, // [21:21] 55 reserved_1b : 1, // [22:22] 56 rx_in_tx_decrypt_byp : 1, // [23:23] 57 encrypt_required : 1, // [24:24] 58 directed : 1, // [25:25] 59 buffer_fragment : 1, // [26:26] 60 mpdu_length_err : 1, // [27:27] 61 tkip_mic_err : 1, // [28:28] 62 decrypt_err : 1, // [29:29] 63 unencrypted_frame_err : 1, // [30:30] 64 fcs_err : 1; // [31:31] 65 uint32_t flow_idx_timeout : 1, // [0:0] 66 flow_idx_invalid : 1, // [1:1] 67 wifi_parser_error : 1, // [2:2] 68 amsdu_parser_error : 1, // [3:3] 69 sa_idx_timeout : 1, // [4:4] 70 da_idx_timeout : 1, // [5:5] 71 msdu_limit_error : 1, // [6:6] 72 da_is_valid : 1, // [7:7] 73 da_is_mcbc : 1, // [8:8] 74 sa_is_valid : 1, // [9:9] 75 decrypt_status_code : 3, // [12:10] 76 rx_bitmap_not_updated : 1, // [13:13] 77 reserved_2 : 17, // [30:14] 78 msdu_done : 1; // [31:31] 79 uint32_t tlv64_padding : 32; // [31:0] 80 #else 81 uint32_t phy_ppdu_id : 16, // [31:16] 82 reserved_0 : 7, // [15:9] 83 sw_frame_group_id : 7, // [8:2] 84 rxpcu_mpdu_filter_in_category : 2; // [1:0] 85 uint32_t fcs_err : 1, // [31:31] 86 unencrypted_frame_err : 1, // [30:30] 87 decrypt_err : 1, // [29:29] 88 tkip_mic_err : 1, // [28:28] 89 mpdu_length_err : 1, // [27:27] 90 buffer_fragment : 1, // [26:26] 91 directed : 1, // [25:25] 92 encrypt_required : 1, // [24:24] 93 rx_in_tx_decrypt_byp : 1, // [23:23] 94 reserved_1b : 1, // [22:22] 95 da_idx_invalid : 1, // [21:21] 96 sa_idx_invalid : 1, // [20:20] 97 ip_chksum_fail : 1, // [19:19] 98 tcp_udp_chksum_fail : 1, // [18:18] 99 msdu_length_err : 1, // [17:17] 100 overflow_err : 1, // [16:16] 101 cce_match : 1, // [15:15] 102 order : 1, // [14:14] 103 fragment_flag : 1, // [13:13] 104 a_msdu_error : 1, // [12:12] 105 eosp : 1, // [11:11] 106 more_data : 1, // [10:10] 107 ctrl_type : 1, // [9:9] 108 mgmt_type : 1, // [8:8] 109 null_data : 1, // [7:7] 110 non_qos : 1, // [6:6] 111 power_mgmt : 1, // [5:5] 112 ast_index_timeout : 1, // [4:4] 113 ast_index_not_found : 1, // [3:3] 114 mcast_bcast : 1, // [2:2] 115 reserved_1a : 1, // [1:1] 116 first_mpdu : 1; // [0:0] 117 uint32_t msdu_done : 1, // [31:31] 118 reserved_2 : 17, // [30:14] 119 rx_bitmap_not_updated : 1, // [13:13] 120 decrypt_status_code : 3, // [12:10] 121 sa_is_valid : 1, // [9:9] 122 da_is_mcbc : 1, // [8:8] 123 da_is_valid : 1, // [7:7] 124 msdu_limit_error : 1, // [6:6] 125 da_idx_timeout : 1, // [5:5] 126 sa_idx_timeout : 1, // [4:4] 127 amsdu_parser_error : 1, // [3:3] 128 wifi_parser_error : 1, // [2:2] 129 flow_idx_invalid : 1, // [1:1] 130 flow_idx_timeout : 1; // [0:0] 131 uint32_t tlv64_padding : 32; // [31:0] 132 #endif 133 }; 134 135 136 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 137 138 Field indicates what the reason was that this MPDU frame 139 was allowed to come into the receive path by RXPCU 140 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 141 filter programming of rxpcu 142 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 143 regular frame filter and would have been dropped, were 144 it not for the frame fitting into the 'monitor_client' category. 145 146 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 147 regular frame filter and also did not pass the rxpcu_monitor_client 148 filter. It would have been dropped accept that it did pass 149 the 'monitor_other' category. 150 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 151 the normal frame filter programming of RXPCU but additionally 152 fit into the 'monitor_override_client' category. 153 <legal 0-3> 154 */ 155 156 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 157 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 158 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 159 #define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 160 161 162 /* Description SW_FRAME_GROUP_ID 163 164 SW processes frames based on certain classifications. This 165 field indicates to what sw classification this MPDU is 166 mapped. 167 The classification is given in priority order 168 169 <enum 0 sw_frame_group_NDP_frame> 170 171 <enum 1 sw_frame_group_Multicast_data> 172 <enum 2 sw_frame_group_Unicast_data> 173 <enum 3 sw_frame_group_Null_data > This includes mpdus of 174 type Data Null. 175 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 176 Null frames except in UL MU or TB PPDUs. 177 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 178 QoS Null frames in UL MU or TB PPDUs. 179 180 <enum 4 sw_frame_group_mgmt_0000 > 181 <enum 5 sw_frame_group_mgmt_0001 > 182 <enum 6 sw_frame_group_mgmt_0010 > 183 <enum 7 sw_frame_group_mgmt_0011 > 184 <enum 8 sw_frame_group_mgmt_0100 > 185 <enum 9 sw_frame_group_mgmt_0101 > 186 <enum 10 sw_frame_group_mgmt_0110 > 187 <enum 11 sw_frame_group_mgmt_0111 > 188 <enum 12 sw_frame_group_mgmt_1000 > 189 <enum 13 sw_frame_group_mgmt_1001 > 190 <enum 14 sw_frame_group_mgmt_1010 > 191 <enum 15 sw_frame_group_mgmt_1011 > 192 <enum 16 sw_frame_group_mgmt_1100 > 193 <enum 17 sw_frame_group_mgmt_1101 > 194 <enum 18 sw_frame_group_mgmt_1110 > 195 <enum 19 sw_frame_group_mgmt_1111 > 196 197 <enum 20 sw_frame_group_ctrl_0000 > 198 <enum 21 sw_frame_group_ctrl_0001 > 199 <enum 22 sw_frame_group_ctrl_0010 > 200 <enum 23 sw_frame_group_ctrl_0011 > 201 <enum 24 sw_frame_group_ctrl_0100 > 202 <enum 25 sw_frame_group_ctrl_0101 > 203 <enum 26 sw_frame_group_ctrl_0110 > 204 <enum 27 sw_frame_group_ctrl_0111 > 205 <enum 28 sw_frame_group_ctrl_1000 > 206 <enum 29 sw_frame_group_ctrl_1001 > 207 <enum 30 sw_frame_group_ctrl_1010 > 208 <enum 31 sw_frame_group_ctrl_1011 > 209 <enum 32 sw_frame_group_ctrl_1100 > 210 <enum 33 sw_frame_group_ctrl_1101 > 211 <enum 34 sw_frame_group_ctrl_1110 > 212 <enum 35 sw_frame_group_ctrl_1111 > 213 214 <enum 36 sw_frame_group_unsupported> This covers type 3 215 and protocol version != 0 216 217 <enum 37 sw_frame_group_phy_error> PHY reported an error 218 219 220 <legal 0-39> 221 */ 222 223 #define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 224 #define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 225 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 226 #define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 227 228 229 /* Description RESERVED_0 230 231 <legal 0> 232 */ 233 234 #define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 235 #define RX_ATTENTION_RESERVED_0_LSB 9 236 #define RX_ATTENTION_RESERVED_0_MSB 15 237 #define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 238 239 240 /* Description PHY_PPDU_ID 241 242 A ppdu counter value that PHY increments for every PPDU 243 received. The counter value wraps around 244 <legal all> 245 */ 246 247 #define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 248 #define RX_ATTENTION_PHY_PPDU_ID_LSB 16 249 #define RX_ATTENTION_PHY_PPDU_ID_MSB 31 250 #define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 251 252 253 /* Description FIRST_MPDU 254 255 Indicates the first MSDU of the PPDU. If both first_mpdu 256 and last_mpdu are set in the MSDU then this is a not an 257 A-MPDU frame but a stand alone MPDU. Interior MPDU in 258 an A-MPDU shall have both first_mpdu and last_mpdu bits 259 set to 0. The PPDU start status will only be valid when 260 this bit is set. 261 */ 262 263 #define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 264 #define RX_ATTENTION_FIRST_MPDU_LSB 32 265 #define RX_ATTENTION_FIRST_MPDU_MSB 32 266 #define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 267 268 269 /* Description RESERVED_1A 270 271 <legal 0> 272 */ 273 274 #define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 275 #define RX_ATTENTION_RESERVED_1A_LSB 33 276 #define RX_ATTENTION_RESERVED_1A_MSB 33 277 #define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 278 279 280 /* Description MCAST_BCAST 281 282 Multicast / broadcast indicator. Only set when the MAC 283 address 1 bit 0 is set indicating mcast/bcast and the BSSID 284 matches one of the 4 BSSID registers. Only set when first_msdu 285 is set. 286 */ 287 288 #define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 289 #define RX_ATTENTION_MCAST_BCAST_LSB 34 290 #define RX_ATTENTION_MCAST_BCAST_MSB 34 291 #define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 292 293 294 /* Description AST_INDEX_NOT_FOUND 295 296 Only valid when first_msdu is set. 297 298 Indicates no AST matching entries within the the max search 299 count. 300 */ 301 302 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 303 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 304 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 305 #define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 306 307 308 /* Description AST_INDEX_TIMEOUT 309 310 Only valid when first_msdu is set. 311 312 Indicates an unsuccessful search in the address seach table 313 due to timeout. 314 */ 315 316 #define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 317 #define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 318 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 319 #define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 320 321 322 /* Description POWER_MGMT 323 324 Power management bit set in the 802.11 header. Only set 325 when first_msdu is set. 326 */ 327 328 #define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 329 #define RX_ATTENTION_POWER_MGMT_LSB 37 330 #define RX_ATTENTION_POWER_MGMT_MSB 37 331 #define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 332 333 334 /* Description NON_QOS 335 336 Set if packet is not a non-QoS data frame. Only set when 337 first_msdu is set. 338 */ 339 340 #define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 341 #define RX_ATTENTION_NON_QOS_LSB 38 342 #define RX_ATTENTION_NON_QOS_MSB 38 343 #define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 344 345 346 /* Description NULL_DATA 347 348 Set if frame type indicates either null data or QoS null 349 data format. Only set when first_msdu is set. 350 */ 351 352 #define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 353 #define RX_ATTENTION_NULL_DATA_LSB 39 354 #define RX_ATTENTION_NULL_DATA_MSB 39 355 #define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 356 357 358 /* Description MGMT_TYPE 359 360 Set if packet is a management packet. Only set when first_msdu 361 is set. 362 */ 363 364 #define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 365 #define RX_ATTENTION_MGMT_TYPE_LSB 40 366 #define RX_ATTENTION_MGMT_TYPE_MSB 40 367 #define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 368 369 370 /* Description CTRL_TYPE 371 372 Set if packet is a control packet. Only set when first_msdu 373 is set. 374 */ 375 376 #define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 377 #define RX_ATTENTION_CTRL_TYPE_LSB 41 378 #define RX_ATTENTION_CTRL_TYPE_MSB 41 379 #define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 380 381 382 /* Description MORE_DATA 383 384 Set if more bit in frame control is set. Only set when 385 first_msdu is set. 386 */ 387 388 #define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 389 #define RX_ATTENTION_MORE_DATA_LSB 42 390 #define RX_ATTENTION_MORE_DATA_MSB 42 391 #define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 392 393 394 /* Description EOSP 395 396 Set if the EOSP (end of service period) bit in the QoS control 397 field is set. Only set when first_msdu is set. 398 */ 399 400 #define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 401 #define RX_ATTENTION_EOSP_LSB 43 402 #define RX_ATTENTION_EOSP_MSB 43 403 #define RX_ATTENTION_EOSP_MASK 0x0000080000000000 404 405 406 /* Description A_MSDU_ERROR 407 408 Set if number of MSDUs in A-MSDU is above a threshold or 409 if the size of the MSDU is invalid. This receive buffer 410 will contain all of the remainder of the MSDUs in this 411 MPDU without decapsulation. 412 */ 413 414 #define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 415 #define RX_ATTENTION_A_MSDU_ERROR_LSB 44 416 #define RX_ATTENTION_A_MSDU_ERROR_MSB 44 417 #define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 418 419 420 /* Description FRAGMENT_FLAG 421 422 Indicates that this is an 802.11 fragment frame. This is 423 set when either the more_frag bit is set in the frame control 424 or the fragment number is not zero. Only set when first_msdu 425 is set. 426 */ 427 428 #define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 429 #define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 430 #define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 431 #define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 432 433 434 /* Description ORDER 435 436 Set if the order bit in the frame control is set. Only 437 set when first_msdu is set. 438 */ 439 440 #define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 441 #define RX_ATTENTION_ORDER_LSB 46 442 #define RX_ATTENTION_ORDER_MSB 46 443 #define RX_ATTENTION_ORDER_MASK 0x0000400000000000 444 445 446 /* Description CCE_MATCH 447 448 Indicates that this status has a corresponding MSDU that 449 requires FW processing. The OLE will have classification 450 ring mask registers which will indicate the ring(s) for 451 packets and descriptors which need FW attention. 452 */ 453 454 #define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 455 #define RX_ATTENTION_CCE_MATCH_LSB 47 456 #define RX_ATTENTION_CCE_MATCH_MSB 47 457 #define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 458 459 460 /* Description OVERFLOW_ERR 461 462 RXPCU Receive FIFO ran out of space to receive the full 463 MPDU. Therefor this MPDU is terminated early and is thus 464 corrupted. 465 466 This MPDU will not be ACKed. 467 RXPCU might still be able to correctly receive the following 468 MPDUs in the PPDU if enough fifo space became available 469 in time 470 */ 471 472 #define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 473 #define RX_ATTENTION_OVERFLOW_ERR_LSB 48 474 #define RX_ATTENTION_OVERFLOW_ERR_MSB 48 475 #define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 476 477 478 /* Description MSDU_LENGTH_ERR 479 480 Indicates that the MSDU length from the 802.3 encapsulated 481 length field extends beyond the MPDU boundary or if the 482 length is less than 14 bytes. 483 Merged with original "other_msdu_err": Indicates that the 484 MSDU threshold was exceeded and thus all the rest of the 485 MSDUs will not be scattered and will not be decasulated 486 but will be DMA'ed in RAW format as a single MSDU buffer 487 488 */ 489 490 #define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 491 #define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 492 #define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 493 #define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 494 495 496 /* Description TCP_UDP_CHKSUM_FAIL 497 498 Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') 499 did not match the checksum in the TCP/UDP header. 500 */ 501 502 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 503 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 504 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 505 #define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 506 507 508 /* Description IP_CHKSUM_FAIL 509 510 Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') 511 did not match the checksum in the IP header. 512 */ 513 514 #define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 515 #define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 516 #define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 517 #define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 518 519 520 /* Description SA_IDX_INVALID 521 522 Indicates no matching entry was found in the address search 523 table for the source MAC address. 524 */ 525 526 #define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 527 #define RX_ATTENTION_SA_IDX_INVALID_LSB 52 528 #define RX_ATTENTION_SA_IDX_INVALID_MSB 52 529 #define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 530 531 532 /* Description DA_IDX_INVALID 533 534 Indicates no matching entry was found in the address search 535 table for the destination MAC address. 536 */ 537 538 #define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 539 #define RX_ATTENTION_DA_IDX_INVALID_LSB 53 540 #define RX_ATTENTION_DA_IDX_INVALID_MSB 53 541 #define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 542 543 544 /* Description RESERVED_1B 545 546 <legal 0> 547 */ 548 549 #define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 550 #define RX_ATTENTION_RESERVED_1B_LSB 54 551 #define RX_ATTENTION_RESERVED_1B_MSB 54 552 #define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 553 554 555 /* Description RX_IN_TX_DECRYPT_BYP 556 557 Indicates that RX packet is not decrypted as Crypto is busy 558 with TX packet processing. 559 */ 560 561 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 562 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 563 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 564 #define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 565 566 567 /* Description ENCRYPT_REQUIRED 568 569 Indicates that this data type frame is not encrypted even 570 if the policy for this MPDU requires encryption as indicated 571 in the peer entry key type. 572 */ 573 574 #define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 575 #define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 576 #define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 577 #define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 578 579 580 /* Description DIRECTED 581 582 MPDU is a directed packet which means that the RA matched 583 our STA addresses. In proxySTA it means that the TA matched 584 an entry in our address search table with the corresponding 585 "no_ack" bit is the address search entry cleared. 586 */ 587 588 #define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 589 #define RX_ATTENTION_DIRECTED_LSB 57 590 #define RX_ATTENTION_DIRECTED_MSB 57 591 #define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 592 593 594 /* Description BUFFER_FRAGMENT 595 596 Indicates that at least one of the rx buffers has been fragmented. 597 If set the FW should look at the rx_frag_info descriptor 598 described below. 599 */ 600 601 #define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 602 #define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 603 #define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 604 #define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 605 606 607 /* Description MPDU_LENGTH_ERR 608 609 Indicates that the MPDU was pre-maturely terminated resulting 610 in a truncated MPDU. Don't trust the MPDU length field. 611 612 */ 613 614 #define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 615 #define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 616 #define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 617 #define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 618 619 620 /* Description TKIP_MIC_ERR 621 622 Indicates that the MPDU Michael integrity check failed 623 */ 624 625 #define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 626 #define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 627 #define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 628 #define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 629 630 631 /* Description DECRYPT_ERR 632 633 Indicates that the MPDU decrypt integrity check failed or 634 CRYPTO received an encrypted frame, but did not get a valid 635 corresponding key id in the peer entry. 636 */ 637 638 #define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 639 #define RX_ATTENTION_DECRYPT_ERR_LSB 61 640 #define RX_ATTENTION_DECRYPT_ERR_MSB 61 641 #define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 642 643 644 /* Description UNENCRYPTED_FRAME_ERR 645 646 Copied here by RX OLE from the RX_MPDU_END TLV 647 */ 648 649 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 650 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 651 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 652 #define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 653 654 655 /* Description FCS_ERR 656 657 Indicates that the MPDU FCS check failed 658 */ 659 660 #define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 661 #define RX_ATTENTION_FCS_ERR_LSB 63 662 #define RX_ATTENTION_FCS_ERR_MSB 63 663 #define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 664 665 666 /* Description FLOW_IDX_TIMEOUT 667 668 Indicates an unsuccessful flow search due to the expiring 669 of the search timer. 670 <legal all> 671 */ 672 673 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 674 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 675 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 676 #define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 677 678 679 /* Description FLOW_IDX_INVALID 680 681 flow id is not valid 682 <legal all> 683 */ 684 685 #define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 686 #define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 687 #define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 688 #define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 689 690 691 /* Description WIFI_PARSER_ERROR 692 693 Indicates that the WiFi frame has one of the following errors 694 695 o has less than minimum allowed bytes as per standard 696 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 697 <legal all> 698 */ 699 700 #define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 701 #define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 702 #define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 703 #define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 704 705 706 /* Description AMSDU_PARSER_ERROR 707 708 A-MSDU could not be properly de-agregated. 709 <legal all> 710 */ 711 712 #define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 713 #define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 714 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 715 #define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 716 717 718 /* Description SA_IDX_TIMEOUT 719 720 Indicates an unsuccessful MAC source address search due 721 to the expiring of the search timer. 722 */ 723 724 #define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 725 #define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 726 #define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 727 #define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 728 729 730 /* Description DA_IDX_TIMEOUT 731 732 Indicates an unsuccessful MAC destination address search 733 due to the expiring of the search timer. 734 */ 735 736 #define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 737 #define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 738 #define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 739 #define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 740 741 742 /* Description MSDU_LIMIT_ERROR 743 744 Indicates that the MSDU threshold was exceeded and thus 745 all the rest of the MSDUs will not be scattered and will 746 not be decasulated but will be DMA'ed in RAW format as 747 a single MSDU buffer 748 */ 749 750 #define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 751 #define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 752 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 753 #define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 754 755 756 /* Description DA_IS_VALID 757 758 Indicates that OLE found a valid DA entry 759 */ 760 761 #define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 762 #define RX_ATTENTION_DA_IS_VALID_LSB 7 763 #define RX_ATTENTION_DA_IS_VALID_MSB 7 764 #define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 765 766 767 /* Description DA_IS_MCBC 768 769 Field Only valid if "da_is_valid" is set 770 771 Indicates the DA address was a Multicast of Broadcast address. 772 773 */ 774 775 #define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 776 #define RX_ATTENTION_DA_IS_MCBC_LSB 8 777 #define RX_ATTENTION_DA_IS_MCBC_MSB 8 778 #define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 779 780 781 /* Description SA_IS_VALID 782 783 Indicates that OLE found a valid SA entry 784 */ 785 786 #define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 787 #define RX_ATTENTION_SA_IS_VALID_LSB 9 788 #define RX_ATTENTION_SA_IS_VALID_MSB 9 789 #define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 790 791 792 /* Description DECRYPT_STATUS_CODE 793 794 Field provides insight into the decryption performed 795 796 <enum 0 decrypt_ok> Frame had protection enabled and decrypted 797 properly 798 <enum 1 decrypt_unprotected_frame > Frame is unprotected 799 and hence bypassed 800 <enum 2 decrypt_data_err > Frame has protection enabled 801 and could not be properly decrypted due to MIC/ICV mismatch 802 etc. 803 <enum 3 decrypt_key_invalid > Frame has protection enabled 804 but the key that was required to decrypt this frame was 805 not valid 806 <enum 4 decrypt_peer_entry_invalid > Frame has protection 807 enabled but the key that was required to decrypt this frame 808 was not valid 809 <enum 5 decrypt_other > Reserved for other indications 810 811 <legal 0 - 5> 812 */ 813 814 #define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 815 #define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 816 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 817 #define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 818 819 820 /* Description RX_BITMAP_NOT_UPDATED 821 822 Frame is received, but RXPCU could not update the receive 823 bitmap due to (temporary) fifo contraints. 824 <legal all> 825 */ 826 827 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 828 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 829 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 830 #define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 831 832 833 /* Description RESERVED_2 834 835 <legal 0> 836 */ 837 838 #define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 839 #define RX_ATTENTION_RESERVED_2_LSB 14 840 #define RX_ATTENTION_RESERVED_2_MSB 30 841 #define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 842 843 844 /* Description MSDU_DONE 845 846 If set indicates that the RX packet data, RX header data, 847 RX PPDU start descriptor, RX MPDU start/end descriptor, 848 RX MSDU start/end descriptors and RX Attention descriptor 849 are all valid. This bit must be in the last octet of the 850 descriptor. 851 */ 852 853 #define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 854 #define RX_ATTENTION_MSDU_DONE_LSB 31 855 #define RX_ATTENTION_MSDU_DONE_MSB 31 856 #define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 857 858 859 /* Description TLV64_PADDING 860 861 Automatic DWORD padding inserted while converting TLV32 862 to TLV64 for 64 bit ARCH 863 <legal 0> 864 */ 865 866 #define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 867 #define RX_ATTENTION_TLV64_PADDING_LSB 32 868 #define RX_ATTENTION_TLV64_PADDING_MSB 63 869 #define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 870 871 872 873 #endif // RX_ATTENTION 874