1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_FLOW_SEARCH_ENTRY_H_ 18 #define _RX_FLOW_SEARCH_ENTRY_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 23 24 25 struct rx_flow_search_entry { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t src_ip_127_96 : 32; // [31:0] 28 uint32_t src_ip_95_64 : 32; // [31:0] 29 uint32_t src_ip_63_32 : 32; // [31:0] 30 uint32_t src_ip_31_0 : 32; // [31:0] 31 uint32_t dest_ip_127_96 : 32; // [31:0] 32 uint32_t dest_ip_95_64 : 32; // [31:0] 33 uint32_t dest_ip_63_32 : 32; // [31:0] 34 uint32_t dest_ip_31_0 : 32; // [31:0] 35 uint32_t src_port : 16, // [15:0] 36 dest_port : 16; // [31:16] 37 uint32_t l4_protocol : 8, // [7:0] 38 valid : 1, // [8:8] 39 reserved_9 : 4, // [12:9] 40 service_code : 9, // [21:13] 41 priority_valid : 1, // [22:22] 42 use_ppe : 1, // [23:23] 43 reo_destination_indication : 5, // [28:24] 44 msdu_drop : 1, // [29:29] 45 reo_destination_handler : 2; // [31:30] 46 uint32_t metadata : 32; // [31:0] 47 uint32_t aggregation_count : 7, // [6:0] 48 lro_eligible : 1, // [7:7] 49 msdu_count : 24; // [31:8] 50 uint32_t msdu_byte_count : 32; // [31:0] 51 uint32_t timestamp : 32; // [31:0] 52 uint32_t cumulative_ip_length_pmac1 : 16, // [15:0] 53 cumulative_ip_length : 16; // [31:16] 54 uint32_t tcp_sequence_number : 32; // [31:0] 55 #else 56 uint32_t src_ip_127_96 : 32; // [31:0] 57 uint32_t src_ip_95_64 : 32; // [31:0] 58 uint32_t src_ip_63_32 : 32; // [31:0] 59 uint32_t src_ip_31_0 : 32; // [31:0] 60 uint32_t dest_ip_127_96 : 32; // [31:0] 61 uint32_t dest_ip_95_64 : 32; // [31:0] 62 uint32_t dest_ip_63_32 : 32; // [31:0] 63 uint32_t dest_ip_31_0 : 32; // [31:0] 64 uint32_t dest_port : 16, // [31:16] 65 src_port : 16; // [15:0] 66 uint32_t reo_destination_handler : 2, // [31:30] 67 msdu_drop : 1, // [29:29] 68 reo_destination_indication : 5, // [28:24] 69 use_ppe : 1, // [23:23] 70 priority_valid : 1, // [22:22] 71 service_code : 9, // [21:13] 72 reserved_9 : 4, // [12:9] 73 valid : 1, // [8:8] 74 l4_protocol : 8; // [7:0] 75 uint32_t metadata : 32; // [31:0] 76 uint32_t msdu_count : 24, // [31:8] 77 lro_eligible : 1, // [7:7] 78 aggregation_count : 7; // [6:0] 79 uint32_t msdu_byte_count : 32; // [31:0] 80 uint32_t timestamp : 32; // [31:0] 81 uint32_t cumulative_ip_length : 16, // [31:16] 82 cumulative_ip_length_pmac1 : 16; // [15:0] 83 uint32_t tcp_sequence_number : 32; // [31:0] 84 #endif 85 }; 86 87 88 /* Description SRC_IP_127_96 89 90 Uppermost 32 bits of source IPv6 address or prefix as per 91 Common Parser register field IP_DA_SA_PREFIX (with the 92 first byte in the MSB and the last byte in the LSB, i.e. 93 requiring a byte-swap for little-endian SW w.r.t. the byte 94 order in an IPv6 packet) 95 <legal all> 96 */ 97 98 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 99 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 100 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 101 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff 102 103 104 /* Description SRC_IP_95_64 105 106 Next 32 bits of source IPv6 address or prefix (requiring 107 a byte-swap for little-endian SW) <legal all> 108 */ 109 110 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 111 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 112 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 113 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff 114 115 116 /* Description SRC_IP_63_32 117 118 Next 32 bits of source IPv6 address or lowest 32 bits of 119 prefix (requiring a byte-swap for little-endian SW) 120 <legal all> 121 */ 122 123 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 124 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 125 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 126 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff 127 128 129 /* Description SRC_IP_31_0 130 131 Lowest 32 bits of source IPv6 address, or source IPv4 address 132 (requiring a byte-swap for little-endian SW w.r.t. the 133 byte order in an IPv6 or IPv4 packet) 134 <legal all> 135 */ 136 137 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c 138 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 139 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 140 #define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff 141 142 143 /* Description DEST_IP_127_96 144 145 Uppermost 32 bits of destination IPv6 address or prefix 146 as per Common Parser register field IP_DA_SA_PREFIX (with 147 the first byte in the MSB and the last byte in the LSB, 148 i.e. requiring a byte-swap for little-endian SW w.r.t. the 149 byte order as in an IPv6 packet) 150 <legal all> 151 */ 152 153 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 154 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 155 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 156 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff 157 158 159 /* Description DEST_IP_95_64 160 161 Next 32 bits of destination IPv6 address or prefix (requiring 162 a byte-swap for little-endian SW) 163 <legal all> 164 */ 165 166 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 167 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 168 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 169 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff 170 171 172 /* Description DEST_IP_63_32 173 174 Next 32 bits of destination IPv6 address or lowest 32 bits 175 of prefix (requiring a byte-swap for little-endian SW) 176 <legal all> 177 */ 178 179 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 180 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 181 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 182 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff 183 184 185 /* Description DEST_IP_31_0 186 187 Lowest 32 bits of destination IPv6 address, or destination 188 IPv4 address (requiring a byte-swap for little-endian SW 189 w.r.t. the byte order in an IPv6 or IPv4 packet) 190 <legal all> 191 */ 192 193 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c 194 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 195 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 196 #define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff 197 198 199 /* Description SRC_PORT 200 201 LSB of SPI in case of ESP/AH 202 else source port in case of TCP/UDP without IPsec, 203 else zeros in case of ICMP (with the first/third byte in 204 the MSB and the second/fourth byte in the LSB, i.e. requiring 205 a byte-swap for little-endian SW w.r.t. the byte order 206 as in an IPv6 or IPv4 packet) <legal all> 207 */ 208 209 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 210 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 211 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 212 #define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff 213 214 215 /* Description DEST_PORT 216 217 MSB of SPI in case of ESP/AH 218 else destination port in case of TCP/UDP without IPsec, 219 else zeros in case of ICMP (with the first byte in the MSB 220 and the second byte in the LSB, i.e. requiring a byte-swap 221 for little-endian SW w.r.t. the byte order as in an IPv6 222 or IPv4 packet) 223 <legal all> 224 */ 225 226 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 227 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 228 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 229 #define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 230 231 232 /* Description L4_PROTOCOL 233 234 IPsec or L4 protocol 235 236 <enum 1 ICMPV4> 237 <enum 6 TCP> 238 <enum 17 UDP> 239 <enum 50 ESP> 240 <enum 51 AH> 241 <enum 58 ICMPV6> 242 <legal 1, 6, 17, 50, 51, 58> 243 */ 244 245 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 246 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 247 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 248 #define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff 249 250 251 /* Description VALID 252 253 Indicates validity of entry 254 <legal all> 255 */ 256 257 #define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 258 #define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 259 #define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 260 #define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 261 262 263 /* Description RESERVED_9 264 265 <legal 0> 266 */ 267 268 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 269 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 270 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 271 #define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 272 273 274 /* Description SERVICE_CODE 275 276 Opaque service code between PPE and Wi-Fi 277 278 This field gets passed on by REO to PPE in the EDMA descriptor 279 ('REO_TO_PPE_RING'). 280 281 <legal all> 282 */ 283 284 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 285 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 286 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 287 #define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 288 289 290 /* Description PRIORITY_VALID 291 292 This field gets passed on by REO to PPE in the EDMA descriptor 293 ('REO_TO_PPE_RING'). 294 295 <legal all> 296 */ 297 298 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 299 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 300 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 301 #define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 302 303 304 /* Description USE_PPE 305 306 Indicates to RXDMA to ignore the REO_destination_indication 307 and use a programmed value corresponding to the REO2PPE 308 ring 309 310 This override to REO2PPE for packets requiring multiple 311 buffers shall be disabled based on an RXDMA configuration, 312 as PPE may not support such packets. 313 314 <legal all> 315 */ 316 317 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 318 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 319 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 320 #define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 321 322 323 /* Description REO_DESTINATION_INDICATION 324 325 The ID of the REO exit ring where the MSDU frame shall push 326 after (MPDU level) reordering has finished. 327 328 <enum 0 reo_destination_sw0> Reo will push the frame into 329 the REO2SW0 ring 330 <enum 1 reo_destination_sw1> Reo will push the frame into 331 the REO2SW1 ring 332 <enum 2 reo_destination_sw2> Reo will push the frame into 333 the REO2SW2 ring 334 <enum 3 reo_destination_sw3> Reo will push the frame into 335 the REO2SW3 ring 336 <enum 4 reo_destination_sw4> Reo will push the frame into 337 the REO2SW4 ring 338 <enum 5 reo_destination_release> Reo will push the frame 339 into the REO_release ring 340 <enum 6 reo_destination_fw> Reo will push the frame into 341 the REO2FW ring 342 <enum 7 reo_destination_sw5> Reo will push the frame into 343 the REO2SW5 ring (REO remaps this in chips without REO2SW5 344 ring) 345 <enum 8 reo_destination_sw6> Reo will push the frame into 346 the REO2SW6 ring (REO remaps this in chips without REO2SW6 347 ring) 348 <enum 9 reo_destination_sw7> Reo will push the frame into 349 the REO2SW7 ring (REO remaps this in chips without REO2SW7 350 ring) 351 <enum 10 reo_destination_sw8> Reo will push the frame into 352 the REO2SW8 ring (REO remaps this in chips without REO2SW8 353 ring) 354 <enum 11 reo_destination_11> REO remaps this 355 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 356 REO remaps this 357 <enum 14 reo_destination_14> REO remaps this 358 <enum 15 reo_destination_15> REO remaps this 359 <enum 16 reo_destination_16> REO remaps this 360 <enum 17 reo_destination_17> REO remaps this 361 <enum 18 reo_destination_18> REO remaps this 362 <enum 19 reo_destination_19> REO remaps this 363 <enum 20 reo_destination_20> REO remaps this 364 <enum 21 reo_destination_21> REO remaps this 365 <enum 22 reo_destination_22> REO remaps this 366 <enum 23 reo_destination_23> REO remaps this 367 <enum 24 reo_destination_24> REO remaps this 368 <enum 25 reo_destination_25> REO remaps this 369 <enum 26 reo_destination_26> REO remaps this 370 <enum 27 reo_destination_27> REO remaps this 371 <enum 28 reo_destination_28> REO remaps this 372 <enum 29 reo_destination_29> REO remaps this 373 <enum 30 reo_destination_30> REO remaps this 374 <enum 31 reo_destination_31> REO remaps this 375 376 <legal all> 377 */ 378 379 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 380 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 381 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 382 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 383 384 385 /* Description MSDU_DROP 386 387 Overriding indication to REO to forward to REO release ring 388 389 <legal all> 390 */ 391 392 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 393 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 394 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 395 #define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 396 397 398 /* Description REO_DESTINATION_HANDLER 399 400 Indicates how to decide the REO destination indication 401 <enum 0 RXFT_USE_FT> Follow this entry 402 <enum 1 RXFT_USE_ASPT> Use address search+peer table entry 403 404 <enum 2 RXFT_USE_FT2> Follow this entry 405 <enum 3 RXFT_USE_CCE> Use CCE super-rule 406 <legal all> 407 */ 408 409 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 410 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 411 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 412 #define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 413 414 415 /* Description METADATA 416 417 Value to be passed to SW if this flow search entry matches 418 419 <legal all> 420 */ 421 422 #define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 423 #define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 424 #define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 425 #define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff 426 427 428 /* Description AGGREGATION_COUNT 429 430 FISA: Number'of MSDU's aggregated so far 431 432 Based on an RXOLE register, this can be changed to reflect 433 aggregation of MSDUs from PMAC0 only. 434 435 Set to zero in chips not supporting FISA 436 <legal all> 437 */ 438 439 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c 440 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 441 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 442 #define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f 443 444 445 /* Description LRO_ELIGIBLE 446 447 FISA: 448 To indicate whether the previous MSDU for this flow is eligible 449 for LRO/FISA 450 451 Based on an RXOLE register, this can be changed to reflect 452 the LRO/FISA eligibility for MSDUs from PMAC0 only. 453 454 This bit is also known as RDI_invalid. 455 When RXOLE is configured to enable flow search (but ignore 456 the REO_destination_indication) for the first fragment, 457 it will set this bit if a flow entry matches. 458 Subsequently when RXOLE matches this flow entry for any 459 other packet, the REO_destination_indication in this entry 460 is considered invalid and w.r.t. REO routing the flow search 461 is considered to have failed. 462 <legal all> 463 */ 464 465 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c 466 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 467 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 468 #define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 469 470 471 /* Description MSDU_COUNT 472 473 Number of Rx MSDUs matching this flow 474 475 Based on an RXOLE register, this can be changed to reflect 476 the number of Rx MSDUs from PMAC0 matching the flow. 477 <legal all> 478 */ 479 480 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c 481 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 482 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 483 #define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 484 485 486 /* Description MSDU_BYTE_COUNT 487 488 Number of bytes in Rx MSDUs matching this flow 489 490 Based on an RXOLE register, this can be changed to reflect 491 the number of Rx MSDUs from PMAC1 matching the flow. 492 493 Based on an RXOLE register, the MSB 8 bits can be changed 494 to reflect the 'aggregation_count' and 'LRO_eligible' of 495 MSDUs from PMAC1. 496 <legal all> 497 */ 498 499 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 500 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 501 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 502 #define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff 503 504 505 /* Description TIMESTAMP 506 507 Time of last reception (as measured at Rx OLE) matching 508 this flow 509 <legal all> 510 */ 511 512 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 513 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 514 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 515 #define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff 516 517 518 /* Description CUMULATIVE_IP_LENGTH_PMAC1 519 520 Based on an RXOLE register, this can be changed to reflect 521 the 'cumulative_IP_length' for MSDUs from PMAC1. 522 <legal all> 523 */ 524 525 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 526 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 527 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 528 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff 529 530 531 /* Description CUMULATIVE_IP_LENGTH 532 533 FISA: Total MSDU length that is part of this flow aggregated 534 so far 535 536 Based on an RXOLE register, this can be changed to reflect 537 aggregation of MSDUs from PMAC0 only. 538 539 Set to zero in chips not supporting FISA 540 <legal all> 541 */ 542 543 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 544 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 545 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 546 #define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 547 548 549 /* Description TCP_SEQUENCE_NUMBER 550 551 FISA: TCP Sequence number of the last packet in this flow 552 to detect sequence number jump 553 554 Based on an RXOLE register, this can be changed so that 555 the bottom half of this field reflects the LSBs of the TCP 556 sequence number of the last packet from PMAC0 and the top 557 half reflects the LSBs of the TCP sequence number of the 558 last packet from PMAC1. 559 560 Set to zero in chips not supporting FISA 561 <legal all> 562 */ 563 564 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c 565 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 566 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 567 #define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff 568 569 570 571 #endif // RX_FLOW_SEARCH_ENTRY 572