1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_FRAME_BITMAP_ACK_H_ 18 #define _RX_FRAME_BITMAP_ACK_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 23 24 #define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 25 26 27 struct rx_frame_bitmap_ack { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t no_bitmap_available : 1, // [0:0] 30 explicit_ack : 1, // [1:1] 31 explict_ack_type : 3, // [4:2] 32 ba_bitmap_size : 2, // [6:5] 33 reserved_0a : 3, // [9:7] 34 ba_tid : 4, // [13:10] 35 sta_full_aid : 13, // [26:14] 36 reserved_0b : 5; // [31:27] 37 uint32_t addr1_31_0 : 32; // [31:0] 38 uint32_t addr1_47_32 : 16, // [15:0] 39 addr2_15_0 : 16; // [31:16] 40 uint32_t addr2_47_16 : 32; // [31:0] 41 uint32_t ba_ts_ctrl : 16, // [15:0] 42 ba_ts_seq : 16; // [31:16] 43 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 44 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 45 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 46 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 47 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 48 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 49 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 50 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 51 uint32_t tlv64_padding : 32; // [31:0] 52 #else 53 uint32_t reserved_0b : 5, // [31:27] 54 sta_full_aid : 13, // [26:14] 55 ba_tid : 4, // [13:10] 56 reserved_0a : 3, // [9:7] 57 ba_bitmap_size : 2, // [6:5] 58 explict_ack_type : 3, // [4:2] 59 explicit_ack : 1, // [1:1] 60 no_bitmap_available : 1; // [0:0] 61 uint32_t addr1_31_0 : 32; // [31:0] 62 uint32_t addr2_15_0 : 16, // [31:16] 63 addr1_47_32 : 16; // [15:0] 64 uint32_t addr2_47_16 : 32; // [31:0] 65 uint32_t ba_ts_seq : 16, // [31:16] 66 ba_ts_ctrl : 16; // [15:0] 67 uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] 68 uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] 69 uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] 70 uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] 71 uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] 72 uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] 73 uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] 74 uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] 75 uint32_t tlv64_padding : 32; // [31:0] 76 #endif 77 }; 78 79 80 /* Description NO_BITMAP_AVAILABLE 81 82 When set, RXPCU does not have any info available for the 83 requested user. 84 85 RXPCU will set the TA/RA, addresses with the devices OWN 86 address. 87 All other fields are set to 0 88 89 TXPCU will just blindly follow RXPCUs info. 90 (only for status reporting is TXPCU using this). 91 92 Note that this field and field "Explicit_ack" can not be 93 simultaneously set. 94 <legal all> 95 */ 96 97 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 98 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 99 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 100 #define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 101 102 103 /* Description EXPLICIT_ACK 104 105 When set, no BA is needed for this STA. Instead just a single 106 ACK indication 107 108 Note that this field and field "No_bitmap_available" can 109 not be simultaneously set. 110 111 Also note that RXPCU might not know if the response that 112 TXPCU is generating is a single ACK or M(sta) BA. 113 For that reason, RXPCU shall also properly fill in all the 114 BA related fields. TXPCU will based on the explicit ack 115 type and in case of BA type response, blindely copy the 116 required BA related fields and not change their contents: 117 118 The related fields are: 119 Ba_tid 120 ba_ts_ctrl 121 ba_ts_seq 122 ba_ts_bitmap_... 123 124 <legal all> 125 */ 126 127 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 128 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 129 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 130 #define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 131 132 133 /* Description EXPLICT_ACK_TYPE 134 135 Field only valid when Explicit_ack is set 136 137 Note that TXPCU only needs to evaluate this field in case 138 of generating a multi (STA) BA 139 140 <enum 0 ack_for_single_data_frame> set when only a single 141 data frame was received that indicated explicitly a 'normal' 142 ack (no BA) to be sent. 143 <enum 1 ack_for_management> set when a management frame 144 was received 145 <enum 2 ack_for_PSPOLL> set when a PS_POLL frame was received 146 147 <enum 3 ack_for_assoc_request> set when an association request 148 was received from an unassociated STA. 149 <enum 4 ack_for_all_frames> set when RXPCU determined that 150 all frames have been properly received. 151 <legal 0-4> 152 */ 153 154 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 155 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 156 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 157 #define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c 158 159 160 /* Description BA_BITMAP_SIZE 161 162 Field not valid when "No_bitmap_available" or "Explicit_ack" 163 is set. 164 165 166 <enum 0 BA_bitmap_32 > Bitmap size set to window of 32 167 <enum 1 BA_bitmap_64 > Bitmap size set to window of 64 168 <enum 2 BA_bitmap_128 > Bitmap size set to window of 128 169 170 <enum 3 BA_bitmap_256 > Bitmap size set to window of 256 171 172 173 <legal 0-3> 174 */ 175 176 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 177 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 178 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 179 #define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 180 181 182 /* Description RESERVED_0A 183 184 <legal 0> 185 */ 186 187 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 188 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 189 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 190 #define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 191 192 193 /* Description BA_TID 194 195 The tid for the BA 196 */ 197 198 #define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 199 #define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 200 #define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 201 #define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 202 203 204 /* Description STA_FULL_AID 205 206 The full AID of this station. 207 */ 208 209 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 210 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 211 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 212 #define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 213 214 215 /* Description RESERVED_0B 216 217 <legal 0> 218 */ 219 220 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 221 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 222 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 223 #define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 224 225 226 /* Description ADDR1_31_0 227 228 lower 32 bits of addr1 of the received frame 229 */ 230 231 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 232 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 233 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 234 #define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 235 236 237 /* Description ADDR1_47_32 238 239 upper 16 bits of addr1 of the received frame 240 */ 241 242 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 243 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 244 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 245 #define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 246 247 248 /* Description ADDR2_15_0 249 250 lower 16 bits of addr2 of the received frame 251 */ 252 253 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 254 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 255 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 256 #define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 257 258 259 /* Description ADDR2_47_16 260 261 upper 32 bits of addr2 of the received frame 262 */ 263 264 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 265 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 266 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 267 #define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 268 269 270 /* Description BA_TS_CTRL 271 272 Transmit BA control 273 RXPCU assumes the C-BA format, NOT M-BA format. 274 In case TXPCU is responding with M-BA, TXPCU will ignore 275 this field. TXPCU will generate it 276 */ 277 278 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 279 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 280 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 281 #define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 282 283 284 /* Description BA_TS_SEQ 285 286 Transmit BA sequence number. 287 */ 288 289 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 290 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 291 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 292 #define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 293 294 295 /* Description BA_TS_BITMAP_31_0 296 297 Transmit BA bitmap[31:0] 298 */ 299 300 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 301 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 302 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 303 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 304 305 306 /* Description BA_TS_BITMAP_63_32 307 308 Transmit BA bitmap[63:32] 309 */ 310 311 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 312 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 313 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 314 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 315 316 317 /* Description BA_TS_BITMAP_95_64 318 319 Transmit BA bitmap[95:64] 320 */ 321 322 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 323 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 324 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 325 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 326 327 328 /* Description BA_TS_BITMAP_127_96 329 330 Transmit BA bitmap[127:96] 331 */ 332 333 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 334 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 335 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 336 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 337 338 339 /* Description BA_TS_BITMAP_159_128 340 341 Transmit BA bitmap[159:128] 342 */ 343 344 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 345 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 346 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 347 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 348 349 350 /* Description BA_TS_BITMAP_191_160 351 352 Transmit BA bitmap[191:160] 353 */ 354 355 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 356 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 357 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 358 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 359 360 361 /* Description BA_TS_BITMAP_223_192 362 363 Transmit BA bitmap[223:192] 364 */ 365 366 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 367 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 368 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 369 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 370 371 372 /* Description BA_TS_BITMAP_255_224 373 374 Transmit BA bitmap[255:224] 375 */ 376 377 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 378 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 379 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 380 #define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 381 382 383 /* Description TLV64_PADDING 384 385 Automatic DWORD padding inserted while converting TLV32 386 to TLV64 for 64 bit ARCH 387 <legal 0> 388 */ 389 390 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 391 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 392 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 393 #define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 394 395 396 397 #endif // RX_FRAME_BITMAP_ACK 398