1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_DETAILS_H_ 18 #define _RX_MPDU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_desc_info.h" 23 #include "buffer_addr_info.h" 24 #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 25 26 27 struct rx_mpdu_details { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 struct buffer_addr_info msdu_link_desc_addr_info; 30 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 31 #else 32 struct buffer_addr_info msdu_link_desc_addr_info; 33 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 34 #endif 35 }; 36 37 38 /* Description MSDU_LINK_DESC_ADDR_INFO 39 40 Consumer: REO/SW/FW 41 Producer: RXDMA 42 43 Details of the physical address of the MSDU link descriptor 44 that contains pointers to MSDUs related to this MPDU 45 */ 46 47 48 /* Description BUFFER_ADDR_31_0 49 50 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 51 descriptor OR Link Descriptor 52 53 In case of 'NULL' pointer, this field is set to 0 54 <legal all> 55 */ 56 57 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 58 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 59 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 60 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 61 62 63 /* Description BUFFER_ADDR_39_32 64 65 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 66 descriptor OR Link Descriptor 67 68 In case of 'NULL' pointer, this field is set to 0 69 <legal all> 70 */ 71 72 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 73 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 74 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 75 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 76 77 78 /* Description RETURN_BUFFER_MANAGER 79 80 Consumer: WBM 81 Producer: SW/FW 82 83 In case of 'NULL' pointer, this field is set to 0 84 85 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 86 descriptor OR link descriptor that is being pointed to 87 shall be returned after the frame has been processed. It 88 is used by WBM for routing purposes. 89 90 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 91 to the WMB buffer idle list 92 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 93 to the WBM idle link descriptor idle list, where the chip 94 0 WBM is chosen in case of a multi-chip config 95 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 96 to the chip 1 WBM idle link descriptor idle list 97 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 98 to the chip 2 WBM idle link descriptor idle list 99 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 100 returned to chip 3 WBM idle link descriptor idle list 101 <enum 4 FW_BM> This buffer shall be returned to the FW 102 <enum 5 SW0_BM> This buffer shall be returned to the SW, 103 ring 0 104 <enum 6 SW1_BM> This buffer shall be returned to the SW, 105 ring 1 106 <enum 7 SW2_BM> This buffer shall be returned to the SW, 107 ring 2 108 <enum 8 SW3_BM> This buffer shall be returned to the SW, 109 ring 3 110 <enum 9 SW4_BM> This buffer shall be returned to the SW, 111 ring 4 112 <enum 10 SW5_BM> This buffer shall be returned to the SW, 113 ring 5 114 <enum 11 SW6_BM> This buffer shall be returned to the SW, 115 ring 6 116 117 <legal 0-12> 118 */ 119 120 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 121 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 122 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 123 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 124 125 126 /* Description SW_BUFFER_COOKIE 127 128 Cookie field exclusively used by SW. 129 130 In case of 'NULL' pointer, this field is set to 0 131 132 HW ignores the contents, accept that it passes the programmed 133 value on to other descriptors together with the physical 134 address 135 136 Field can be used by SW to for example associate the buffers 137 physical address with the virtual address 138 The bit definitions as used by SW are within SW HLD specification 139 140 141 NOTE1: 142 The three most significant bits can have a special meaning 143 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 144 and field transmit_bw_restriction is set 145 146 In case of NON punctured transmission: 147 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 148 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 149 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 150 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 151 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 152 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 153 Sw_buffer_cookie[19:18] = 2'b11: reserved 154 155 In case of punctured transmission: 156 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 157 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 158 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 159 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 160 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 161 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 162 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 163 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 164 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 165 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 166 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 167 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 168 Sw_buffer_cookie[19:18] = 2'b11: reserved 169 170 Note: a punctured transmission is indicated by the presence 171 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 172 173 <legal all> 174 */ 175 176 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 177 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 178 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 179 #define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 180 181 182 /* Description RX_MPDU_DESC_INFO_DETAILS 183 184 Consumer: REO/SW/FW 185 Producer: RXDMA 186 187 General information related to the MPDU that should be passed 188 on from REO entrance ring to the REO destination ring 189 */ 190 191 192 /* Description MSDU_COUNT 193 194 Consumer: REO/SW/FW 195 Producer: RXDMA 196 197 The number of MSDUs within the MPDU 198 <legal all> 199 */ 200 201 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 202 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 203 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 204 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 205 206 207 /* Description FRAGMENT_FLAG 208 209 Consumer: REO/SW/FW 210 Producer: RXDMA 211 212 When set, this MPDU is a fragment and REO should forward 213 this fragment MPDU to the REO destination ring without 214 any reorder checks, pn checks or bitmap update. This implies 215 that REO is forwarding the pointer to the MSDU link descriptor. 216 The destination ring is coming from a programmable register 217 setting in REO 218 219 <legal all> 220 */ 221 222 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 223 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 224 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 225 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 226 227 228 /* Description MPDU_RETRY_BIT 229 230 Consumer: REO/SW/FW 231 Producer: RXDMA 232 233 The retry bit setting from the MPDU header of the received 234 frame 235 <legal all> 236 */ 237 238 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 239 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 240 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 241 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 242 243 244 /* Description AMPDU_FLAG 245 246 Consumer: REO/SW/FW 247 Producer: RXDMA 248 249 When set, the MPDU was received as part of an A-MPDU. 250 <legal all> 251 */ 252 253 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 254 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 255 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 256 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 257 258 259 /* Description BAR_FRAME 260 261 Consumer: REO/SW/FW 262 Producer: RXDMA 263 264 When set, the received frame is a BAR frame. After processing, 265 this frame shall be pushed to SW or deleted. 266 <legal all> 267 */ 268 269 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 270 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 271 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 272 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 273 274 275 /* Description PN_FIELDS_CONTAIN_VALID_INFO 276 277 Consumer: REO/SW/FW 278 Producer: RXDMA 279 280 Copied here by RXDMA from RX_MPDU_END 281 When not set, REO will Not perform a PN sequence number 282 check 283 */ 284 285 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 286 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 287 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 288 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 289 290 291 /* Description RAW_MPDU 292 293 Field only valid when first_msdu_in_mpdu_flag is set. 294 295 When set, the contents in the MSDU buffer contains a 'RAW' 296 MPDU. This 'RAW' MPDU might be spread out over multiple 297 MSDU buffers. 298 <legal all> 299 */ 300 301 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 302 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 303 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 304 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 305 306 307 /* Description MORE_FRAGMENT_FLAG 308 309 The More Fragment bit setting from the MPDU header of the 310 received frame 311 312 <legal all> 313 */ 314 315 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 316 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 317 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 318 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 319 320 321 /* Description SRC_INFO 322 323 Source (virtual) device/interface info. associated with 324 this peer 325 326 This field gets passed on by REO to PPE in the EDMA descriptor 327 ('REO_TO_PPE_RING'). 328 329 <legal all> 330 */ 331 332 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 333 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 334 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 335 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 336 337 338 /* Description MPDU_QOS_CONTROL_VALID 339 340 When set, the MPDU has a QoS control field. 341 342 In case of ndp or phy_err, this field will never be set. 343 344 <legal all> 345 */ 346 347 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 348 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 349 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 350 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 351 352 353 /* Description TID 354 355 Field only valid when mpdu_qos_control_valid is set 356 357 The TID field in the QoS control field 358 <legal all> 359 */ 360 361 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 362 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 363 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 364 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 365 366 367 /* Description PEER_META_DATA 368 369 Meta data that SW has programmed in the Peer table entry 370 of the transmitting STA. 371 <legal all> 372 */ 373 374 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 375 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 376 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 377 #define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 378 379 380 381 #endif // RX_MPDU_DETAILS 382