1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_END_H_ 18 #define _RX_MPDU_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_MPDU_END 4 23 24 #define NUM_OF_QWORDS_RX_MPDU_END 2 25 26 27 struct rx_mpdu_end { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 30 sw_frame_group_id : 7, // [8:2] 31 reserved_0 : 7, // [15:9] 32 phy_ppdu_id : 16; // [31:16] 33 uint32_t reserved_1a : 11, // [10:0] 34 unsup_ktype_short_frame : 1, // [11:11] 35 rx_in_tx_decrypt_byp : 1, // [12:12] 36 overflow_err : 1, // [13:13] 37 mpdu_length_err : 1, // [14:14] 38 tkip_mic_err : 1, // [15:15] 39 decrypt_err : 1, // [16:16] 40 unencrypted_frame_err : 1, // [17:17] 41 pn_fields_contain_valid_info : 1, // [18:18] 42 fcs_err : 1, // [19:19] 43 msdu_length_err : 1, // [20:20] 44 rxdma0_destination_ring : 3, // [23:21] 45 rxdma1_destination_ring : 3, // [26:24] 46 decrypt_status_code : 3, // [29:27] 47 rx_bitmap_not_updated : 1, // [30:30] 48 reserved_1b : 1; // [31:31] 49 uint32_t reserved_2a : 15, // [14:0] 50 rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] 51 rxpcu_mgmt_sequence_nr : 16; // [31:16] 52 uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] 53 #else 54 uint32_t phy_ppdu_id : 16, // [31:16] 55 reserved_0 : 7, // [15:9] 56 sw_frame_group_id : 7, // [8:2] 57 rxpcu_mpdu_filter_in_category : 2; // [1:0] 58 uint32_t reserved_1b : 1, // [31:31] 59 rx_bitmap_not_updated : 1, // [30:30] 60 decrypt_status_code : 3, // [29:27] 61 rxdma1_destination_ring : 3, // [26:24] 62 rxdma0_destination_ring : 3, // [23:21] 63 msdu_length_err : 1, // [20:20] 64 fcs_err : 1, // [19:19] 65 pn_fields_contain_valid_info : 1, // [18:18] 66 unencrypted_frame_err : 1, // [17:17] 67 decrypt_err : 1, // [16:16] 68 tkip_mic_err : 1, // [15:15] 69 mpdu_length_err : 1, // [14:14] 70 overflow_err : 1, // [13:13] 71 rx_in_tx_decrypt_byp : 1, // [12:12] 72 unsup_ktype_short_frame : 1, // [11:11] 73 reserved_1a : 11; // [10:0] 74 uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16] 75 rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] 76 reserved_2a : 15; // [14:0] 77 uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] 78 #endif 79 }; 80 81 82 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 83 84 Field indicates what the reason was that this MPDU frame 85 was allowed to come into the receive path by RXPCU 86 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 87 filter programming of rxpcu 88 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 89 regular frame filter and would have been dropped, were 90 it not for the frame fitting into the 'monitor_client' category. 91 92 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 93 regular frame filter and also did not pass the rxpcu_monitor_client 94 filter. It would have been dropped accept that it did pass 95 the 'monitor_other' category. 96 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 97 the normal frame filter programming of RXPCU but additionally 98 fit into the 'monitor_override_client' category. 99 <legal 0-3> 100 */ 101 102 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 103 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 104 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 105 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 106 107 108 /* Description SW_FRAME_GROUP_ID 109 110 SW processes frames based on certain classifications. This 111 field indicates to what sw classification this MPDU is 112 mapped. 113 The classification is given in priority order 114 115 <enum 0 sw_frame_group_NDP_frame> 116 117 <enum 1 sw_frame_group_Multicast_data> 118 <enum 2 sw_frame_group_Unicast_data> 119 <enum 3 sw_frame_group_Null_data > This includes mpdus of 120 type Data Null. 121 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 122 Null frames except in UL MU or TB PPDUs. 123 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 124 QoS Null frames in UL MU or TB PPDUs. 125 126 <enum 4 sw_frame_group_mgmt_0000 > 127 <enum 5 sw_frame_group_mgmt_0001 > 128 <enum 6 sw_frame_group_mgmt_0010 > 129 <enum 7 sw_frame_group_mgmt_0011 > 130 <enum 8 sw_frame_group_mgmt_0100 > 131 <enum 9 sw_frame_group_mgmt_0101 > 132 <enum 10 sw_frame_group_mgmt_0110 > 133 <enum 11 sw_frame_group_mgmt_0111 > 134 <enum 12 sw_frame_group_mgmt_1000 > 135 <enum 13 sw_frame_group_mgmt_1001 > 136 <enum 14 sw_frame_group_mgmt_1010 > 137 <enum 15 sw_frame_group_mgmt_1011 > 138 <enum 16 sw_frame_group_mgmt_1100 > 139 <enum 17 sw_frame_group_mgmt_1101 > 140 <enum 18 sw_frame_group_mgmt_1110 > 141 <enum 19 sw_frame_group_mgmt_1111 > 142 143 <enum 20 sw_frame_group_ctrl_0000 > 144 <enum 21 sw_frame_group_ctrl_0001 > 145 <enum 22 sw_frame_group_ctrl_0010 > 146 <enum 23 sw_frame_group_ctrl_0011 > 147 <enum 24 sw_frame_group_ctrl_0100 > 148 <enum 25 sw_frame_group_ctrl_0101 > 149 <enum 26 sw_frame_group_ctrl_0110 > 150 <enum 27 sw_frame_group_ctrl_0111 > 151 <enum 28 sw_frame_group_ctrl_1000 > 152 <enum 29 sw_frame_group_ctrl_1001 > 153 <enum 30 sw_frame_group_ctrl_1010 > 154 <enum 31 sw_frame_group_ctrl_1011 > 155 <enum 32 sw_frame_group_ctrl_1100 > 156 <enum 33 sw_frame_group_ctrl_1101 > 157 <enum 34 sw_frame_group_ctrl_1110 > 158 <enum 35 sw_frame_group_ctrl_1111 > 159 160 <enum 36 sw_frame_group_unsupported> This covers type 3 161 and protocol version != 0 162 163 <enum 37 sw_frame_group_phy_error> PHY reported an error 164 165 166 <legal 0-39> 167 */ 168 169 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 170 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 171 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 172 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 173 174 175 /* Description RESERVED_0 176 177 <legal 0> 178 */ 179 180 #define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 181 #define RX_MPDU_END_RESERVED_0_LSB 9 182 #define RX_MPDU_END_RESERVED_0_MSB 15 183 #define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 184 185 186 /* Description PHY_PPDU_ID 187 188 A ppdu counter value that PHY increments for every PPDU 189 received. The counter value wraps around 190 <legal all> 191 */ 192 193 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 194 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 195 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 196 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 197 198 199 /* Description RESERVED_1A 200 201 <legal 0> 202 */ 203 204 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 205 #define RX_MPDU_END_RESERVED_1A_LSB 32 206 #define RX_MPDU_END_RESERVED_1A_MSB 42 207 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 208 209 210 /* Description UNSUP_KTYPE_SHORT_FRAME 211 212 This bit will be '1' when WEP or TKIP or WAPI key type is 213 received for 11ah short frame. Crypto will bypass the 214 received packet without decryption to RxOLE after setting 215 this bit. 216 */ 217 218 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 219 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 220 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 221 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 222 223 224 /* Description RX_IN_TX_DECRYPT_BYP 225 226 Indicates that RX packet is not decrypted as Crypto is busy 227 with TX packet processing. 228 */ 229 230 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 231 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 232 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 233 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 234 235 236 /* Description OVERFLOW_ERR 237 238 RXPCU Receive FIFO ran out of space to receive the full 239 MPDU. Therefor this MPDU is terminated early and is thus 240 corrupted. 241 242 This MPDU will not be ACKed. 243 RXPCU might still be able to correctly receive the following 244 MPDUs in the PPDU if enough fifo space became available 245 in time 246 */ 247 248 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 249 #define RX_MPDU_END_OVERFLOW_ERR_LSB 45 250 #define RX_MPDU_END_OVERFLOW_ERR_MSB 45 251 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 252 253 254 /* Description MPDU_LENGTH_ERR 255 256 Set by RXPCU if the expected MPDU length does not correspond 257 with the actually received number of bytes in the MPDU. 258 259 */ 260 261 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 262 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 263 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 264 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 265 266 267 /* Description TKIP_MIC_ERR 268 269 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for 270 this MPDU 271 */ 272 273 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 274 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 275 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 276 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 277 278 279 /* Description DECRYPT_ERR 280 281 Set by RX CRYPTO when CRYPTO detected a decrypt error for 282 this MPDU or CRYPTO received an encrypted frame, but did 283 not get a valid corresponding key id in the peer entry. 284 285 */ 286 287 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 288 #define RX_MPDU_END_DECRYPT_ERR_LSB 48 289 #define RX_MPDU_END_DECRYPT_ERR_MSB 48 290 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 291 292 293 /* Description UNENCRYPTED_FRAME_ERR 294 295 Set by RX CRYPTO when CRYPTO detected an unencrypted frame 296 while in the peer entry field 'All_frames_shall_be_encrypted' 297 is set. 298 */ 299 300 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 301 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 302 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 303 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 304 305 306 /* Description PN_FIELDS_CONTAIN_VALID_INFO 307 308 Set by RX CRYPTO to indicate that there is a valid PN field 309 present in this MPDU 310 */ 311 312 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 313 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 314 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 315 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 316 317 318 /* Description FCS_ERR 319 320 Set by RXPCU when there is an FCS error detected for this 321 MPDU 322 NOTE that when this field is set, all other (error) field 323 settings should be ignored as modules could have made wrong 324 decisions based on the corrupted data. 325 */ 326 327 #define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 328 #define RX_MPDU_END_FCS_ERR_LSB 51 329 #define RX_MPDU_END_FCS_ERR_MSB 51 330 #define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 331 332 333 /* Description MSDU_LENGTH_ERR 334 335 Set by RXOLE when there is an msdu length error detected 336 in at least 1 of the MSDUs embedded within the MPDU 337 */ 338 339 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 340 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 341 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 342 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 343 344 345 /* Description RXDMA0_DESTINATION_RING 346 347 The ring to which RXDMA0 shall push the frame, assuming 348 no MPDU level errors are detected. In case of MPDU level 349 errors, RXDMA0 might change the RXDMA0 destination 350 351 <enum 0 rxdma_release_ring > RXDMA0 shall push the frame 352 to the Release ring. Effectively this means the frame needs 353 to be dropped. 354 355 <enum 1 rxdma2fw_pmac0_ring > RXDMA0 shall push the frame 356 to the FW ring for PMAC0. 357 358 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 359 the SW ring 360 361 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame to 362 the REO entrance ring 363 364 <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 365 to the FW ring for PMAC1. 366 367 <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 368 to the first MLO REO entrance ring. 369 370 <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 371 to the second MLO REO entrance ring. 372 373 <legal 0 - 6> 374 */ 375 376 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 377 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 378 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 379 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 380 381 382 /* Description RXDMA1_DESTINATION_RING 383 384 The ring to which RXDMA1 shall push the frame, assuming 385 no MPDU level errors are detected. In case of MPDU level 386 errors, RXDMA1 might change the RXDMA destination 387 388 <enum 0 rxdma_release_ring > DO NOT USE. 389 390 <enum 1 rxdma2fw_pmac0_ring > DO NOT USE. 391 392 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 393 the SW ring 394 395 <enum 3 rxdma2reo_ring > DO NOT USE. 396 397 <enum 4 rxdma2fw_pmac1_ring> DO NOT USE. 398 399 <enum 5 rxdma2reo_remote0_ring> DO NOT USE. 400 401 <enum 6 rxdma2reo_remote1_ring> DO NOT USE. 402 403 <legal 0 - 6> 404 */ 405 406 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 407 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 408 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 409 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 410 411 412 /* Description DECRYPT_STATUS_CODE 413 414 Field provides insight into the decryption performed 415 416 <enum 0 decrypt_ok> Frame had protection enabled and decrypted 417 properly 418 <enum 1 decrypt_unprotected_frame > Frame is unprotected 419 and hence bypassed 420 <enum 2 decrypt_data_err > Frame has protection enabled 421 and could not be properly decrypted due to MIC/ICV mismatch 422 etc. 423 <enum 3 decrypt_key_invalid > Frame has protection enabled 424 but the key that was required to decrypt this frame was 425 not valid 426 <enum 4 decrypt_peer_entry_invalid > Frame has protection 427 enabled but the key that was required to decrypt this frame 428 was not valid 429 <enum 5 decrypt_other > Reserved for other indications 430 431 <legal 0 - 5> 432 */ 433 434 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 435 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 436 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 437 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 438 439 440 /* Description RX_BITMAP_NOT_UPDATED 441 442 Frame is received, but RXPCU could not update the receive 443 bitmap due to (temporary) fifo contraints. 444 <legal all> 445 */ 446 447 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 448 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 449 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 450 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 451 452 453 /* Description RESERVED_1B 454 455 <legal 0> 456 */ 457 458 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 459 #define RX_MPDU_END_RESERVED_1B_LSB 63 460 #define RX_MPDU_END_RESERVED_1B_MSB 63 461 #define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 462 463 464 /* Description RESERVED_2A 465 466 <legal 0> 467 */ 468 469 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 470 #define RX_MPDU_END_RESERVED_2A_LSB 0 471 #define RX_MPDU_END_RESERVED_2A_MSB 14 472 #define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff 473 474 475 /* Description RXPCU_MGMT_SEQUENCE_NR_VALID 476 477 This field gets set by RXPCU when the received management 478 frame is destined to this device, passes FCS and is categorized 479 as one for which RXPCU should assign a rxpcu_mgmt_sequence_number. 480 After assigning a number, the RXPCU will increment the sequence 481 number for the next management frame that meets these criteria. 482 483 484 <legal all> 485 */ 486 487 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 488 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 489 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 490 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 491 492 493 /* Description RXPCU_MGMT_SEQUENCE_NR 494 495 Field only valid when rxpcu_mgmt_sequence_nr_valid is set 496 497 498 This RXPCU generated sequence number is assigned to this 499 management frame. It is used by FW and host SW for management 500 frame reordering across multiple bands/links. 501 502 <legal all> 503 */ 504 505 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 506 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 507 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 508 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 509 510 511 /* Description RXFRAME_ASSERT_MLO_TIMESTAMP 512 513 'mlo_global_timestamp' that indicates when for the PPDU 514 that contained this MPDU, the 'rx_frame' signal got asserted. 515 516 517 This field is always valid, irrespective of the frame being 518 related to MLO reception or not. It is used by FW and host 519 SW for management frame reordering purposes. 520 521 <legal all> 522 */ 523 524 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 525 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 526 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 527 #define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 528 529 530 531 #endif // RX_MPDU_END 532