1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_INFO_H_ 18 #define _RX_MPDU_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rxpt_classify_info.h" 23 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 24 25 26 struct rx_mpdu_info { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct rxpt_classify_info rxpt_classify_info_details; 29 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 30 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 31 receive_queue_number : 16, // [23:8] 32 pre_delim_err_warning : 1, // [24:24] 33 first_delim_err : 1, // [25:25] 34 reserved_2a : 6; // [31:26] 35 uint32_t pn_31_0 : 32; // [31:0] 36 uint32_t pn_63_32 : 32; // [31:0] 37 uint32_t pn_95_64 : 32; // [31:0] 38 uint32_t pn_127_96 : 32; // [31:0] 39 uint32_t epd_en : 1, // [0:0] 40 all_frames_shall_be_encrypted : 1, // [1:1] 41 encrypt_type : 4, // [5:2] 42 wep_key_width_for_variable_key : 2, // [7:6] 43 mesh_sta : 2, // [9:8] 44 bssid_hit : 1, // [10:10] 45 bssid_number : 4, // [14:11] 46 tid : 4, // [18:15] 47 reserved_7a : 13; // [31:19] 48 uint32_t peer_meta_data : 32; // [31:0] 49 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 50 sw_frame_group_id : 7, // [8:2] 51 ndp_frame : 1, // [9:9] 52 phy_err : 1, // [10:10] 53 phy_err_during_mpdu_header : 1, // [11:11] 54 protocol_version_err : 1, // [12:12] 55 ast_based_lookup_valid : 1, // [13:13] 56 ranging : 1, // [14:14] 57 reserved_9a : 1, // [15:15] 58 phy_ppdu_id : 16; // [31:16] 59 uint32_t ast_index : 16, // [15:0] 60 sw_peer_id : 16; // [31:16] 61 uint32_t mpdu_frame_control_valid : 1, // [0:0] 62 mpdu_duration_valid : 1, // [1:1] 63 mac_addr_ad1_valid : 1, // [2:2] 64 mac_addr_ad2_valid : 1, // [3:3] 65 mac_addr_ad3_valid : 1, // [4:4] 66 mac_addr_ad4_valid : 1, // [5:5] 67 mpdu_sequence_control_valid : 1, // [6:6] 68 mpdu_qos_control_valid : 1, // [7:7] 69 mpdu_ht_control_valid : 1, // [8:8] 70 frame_encryption_info_valid : 1, // [9:9] 71 mpdu_fragment_number : 4, // [13:10] 72 more_fragment_flag : 1, // [14:14] 73 reserved_11a : 1, // [15:15] 74 fr_ds : 1, // [16:16] 75 to_ds : 1, // [17:17] 76 encrypted : 1, // [18:18] 77 mpdu_retry : 1, // [19:19] 78 mpdu_sequence_number : 12; // [31:20] 79 uint32_t key_id_octet : 8, // [7:0] 80 new_peer_entry : 1, // [8:8] 81 decrypt_needed : 1, // [9:9] 82 decap_type : 2, // [11:10] 83 rx_insert_vlan_c_tag_padding : 1, // [12:12] 84 rx_insert_vlan_s_tag_padding : 1, // [13:13] 85 strip_vlan_c_tag_decap : 1, // [14:14] 86 strip_vlan_s_tag_decap : 1, // [15:15] 87 pre_delim_count : 12, // [27:16] 88 ampdu_flag : 1, // [28:28] 89 bar_frame : 1, // [29:29] 90 raw_mpdu : 1, // [30:30] 91 reserved_12 : 1; // [31:31] 92 uint32_t mpdu_length : 14, // [13:0] 93 first_mpdu : 1, // [14:14] 94 mcast_bcast : 1, // [15:15] 95 ast_index_not_found : 1, // [16:16] 96 ast_index_timeout : 1, // [17:17] 97 power_mgmt : 1, // [18:18] 98 non_qos : 1, // [19:19] 99 null_data : 1, // [20:20] 100 mgmt_type : 1, // [21:21] 101 ctrl_type : 1, // [22:22] 102 more_data : 1, // [23:23] 103 eosp : 1, // [24:24] 104 fragment_flag : 1, // [25:25] 105 order : 1, // [26:26] 106 u_apsd_trigger : 1, // [27:27] 107 encrypt_required : 1, // [28:28] 108 directed : 1, // [29:29] 109 amsdu_present : 1, // [30:30] 110 reserved_13 : 1; // [31:31] 111 uint32_t mpdu_frame_control_field : 16, // [15:0] 112 mpdu_duration_field : 16; // [31:16] 113 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 114 uint32_t mac_addr_ad1_47_32 : 16, // [15:0] 115 mac_addr_ad2_15_0 : 16; // [31:16] 116 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 117 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 118 uint32_t mac_addr_ad3_47_32 : 16, // [15:0] 119 mpdu_sequence_control_field : 16; // [31:16] 120 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 121 uint32_t mac_addr_ad4_47_32 : 16, // [15:0] 122 mpdu_qos_control_field : 16; // [31:16] 123 uint32_t mpdu_ht_control_field : 32; // [31:0] 124 uint32_t vdev_id : 8, // [7:0] 125 service_code : 9, // [16:8] 126 priority_valid : 1, // [17:17] 127 src_info : 12, // [29:18] 128 reserved_23a : 1, // [30:30] 129 multi_link_addr_ad1_ad2_valid : 1; // [31:31] 130 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 131 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 132 multi_link_addr_ad2_15_0 : 16; // [31:16] 133 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 134 uint32_t authorized_to_send_wds : 1, // [0:0] 135 reserved_27a : 31; // [31:1] 136 uint32_t reserved_28a : 32; // [31:0] 137 uint32_t reserved_29a : 32; // [31:0] 138 #else 139 struct rxpt_classify_info rxpt_classify_info_details; 140 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 141 uint32_t reserved_2a : 6, // [31:26] 142 first_delim_err : 1, // [25:25] 143 pre_delim_err_warning : 1, // [24:24] 144 receive_queue_number : 16, // [23:8] 145 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 146 uint32_t pn_31_0 : 32; // [31:0] 147 uint32_t pn_63_32 : 32; // [31:0] 148 uint32_t pn_95_64 : 32; // [31:0] 149 uint32_t pn_127_96 : 32; // [31:0] 150 uint32_t reserved_7a : 13, // [31:19] 151 tid : 4, // [18:15] 152 bssid_number : 4, // [14:11] 153 bssid_hit : 1, // [10:10] 154 mesh_sta : 2, // [9:8] 155 wep_key_width_for_variable_key : 2, // [7:6] 156 encrypt_type : 4, // [5:2] 157 all_frames_shall_be_encrypted : 1, // [1:1] 158 epd_en : 1; // [0:0] 159 uint32_t peer_meta_data : 32; // [31:0] 160 uint32_t phy_ppdu_id : 16, // [31:16] 161 reserved_9a : 1, // [15:15] 162 ranging : 1, // [14:14] 163 ast_based_lookup_valid : 1, // [13:13] 164 protocol_version_err : 1, // [12:12] 165 phy_err_during_mpdu_header : 1, // [11:11] 166 phy_err : 1, // [10:10] 167 ndp_frame : 1, // [9:9] 168 sw_frame_group_id : 7, // [8:2] 169 rxpcu_mpdu_filter_in_category : 2; // [1:0] 170 uint32_t sw_peer_id : 16, // [31:16] 171 ast_index : 16; // [15:0] 172 uint32_t mpdu_sequence_number : 12, // [31:20] 173 mpdu_retry : 1, // [19:19] 174 encrypted : 1, // [18:18] 175 to_ds : 1, // [17:17] 176 fr_ds : 1, // [16:16] 177 reserved_11a : 1, // [15:15] 178 more_fragment_flag : 1, // [14:14] 179 mpdu_fragment_number : 4, // [13:10] 180 frame_encryption_info_valid : 1, // [9:9] 181 mpdu_ht_control_valid : 1, // [8:8] 182 mpdu_qos_control_valid : 1, // [7:7] 183 mpdu_sequence_control_valid : 1, // [6:6] 184 mac_addr_ad4_valid : 1, // [5:5] 185 mac_addr_ad3_valid : 1, // [4:4] 186 mac_addr_ad2_valid : 1, // [3:3] 187 mac_addr_ad1_valid : 1, // [2:2] 188 mpdu_duration_valid : 1, // [1:1] 189 mpdu_frame_control_valid : 1; // [0:0] 190 uint32_t reserved_12 : 1, // [31:31] 191 raw_mpdu : 1, // [30:30] 192 bar_frame : 1, // [29:29] 193 ampdu_flag : 1, // [28:28] 194 pre_delim_count : 12, // [27:16] 195 strip_vlan_s_tag_decap : 1, // [15:15] 196 strip_vlan_c_tag_decap : 1, // [14:14] 197 rx_insert_vlan_s_tag_padding : 1, // [13:13] 198 rx_insert_vlan_c_tag_padding : 1, // [12:12] 199 decap_type : 2, // [11:10] 200 decrypt_needed : 1, // [9:9] 201 new_peer_entry : 1, // [8:8] 202 key_id_octet : 8; // [7:0] 203 uint32_t reserved_13 : 1, // [31:31] 204 amsdu_present : 1, // [30:30] 205 directed : 1, // [29:29] 206 encrypt_required : 1, // [28:28] 207 u_apsd_trigger : 1, // [27:27] 208 order : 1, // [26:26] 209 fragment_flag : 1, // [25:25] 210 eosp : 1, // [24:24] 211 more_data : 1, // [23:23] 212 ctrl_type : 1, // [22:22] 213 mgmt_type : 1, // [21:21] 214 null_data : 1, // [20:20] 215 non_qos : 1, // [19:19] 216 power_mgmt : 1, // [18:18] 217 ast_index_timeout : 1, // [17:17] 218 ast_index_not_found : 1, // [16:16] 219 mcast_bcast : 1, // [15:15] 220 first_mpdu : 1, // [14:14] 221 mpdu_length : 14; // [13:0] 222 uint32_t mpdu_duration_field : 16, // [31:16] 223 mpdu_frame_control_field : 16; // [15:0] 224 uint32_t mac_addr_ad1_31_0 : 32; // [31:0] 225 uint32_t mac_addr_ad2_15_0 : 16, // [31:16] 226 mac_addr_ad1_47_32 : 16; // [15:0] 227 uint32_t mac_addr_ad2_47_16 : 32; // [31:0] 228 uint32_t mac_addr_ad3_31_0 : 32; // [31:0] 229 uint32_t mpdu_sequence_control_field : 16, // [31:16] 230 mac_addr_ad3_47_32 : 16; // [15:0] 231 uint32_t mac_addr_ad4_31_0 : 32; // [31:0] 232 uint32_t mpdu_qos_control_field : 16, // [31:16] 233 mac_addr_ad4_47_32 : 16; // [15:0] 234 uint32_t mpdu_ht_control_field : 32; // [31:0] 235 uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] 236 reserved_23a : 1, // [30:30] 237 src_info : 12, // [29:18] 238 priority_valid : 1, // [17:17] 239 service_code : 9, // [16:8] 240 vdev_id : 8; // [7:0] 241 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 242 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 243 multi_link_addr_ad1_47_32 : 16; // [15:0] 244 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 245 uint32_t reserved_27a : 31, // [31:1] 246 authorized_to_send_wds : 1; // [0:0] 247 uint32_t reserved_28a : 32; // [31:0] 248 uint32_t reserved_29a : 32; // [31:0] 249 #endif 250 }; 251 252 253 /* Description RXPT_CLASSIFY_INFO_DETAILS 254 255 In case of ndp or phy_err or AST_based_lookup_valid == 0, 256 this field will be set to 0 257 258 RXOLE related classification info 259 <legal all 260 */ 261 262 263 /* Description REO_DESTINATION_INDICATION 264 265 The ID of the REO exit ring where the MSDU frame shall push 266 after (MPDU level) reordering has finished. 267 268 <enum 0 reo_destination_sw0> Reo will push the frame into 269 the REO2SW0 ring 270 <enum 1 reo_destination_sw1> Reo will push the frame into 271 the REO2SW1 ring 272 <enum 2 reo_destination_sw2> Reo will push the frame into 273 the REO2SW2 ring 274 <enum 3 reo_destination_sw3> Reo will push the frame into 275 the REO2SW3 ring 276 <enum 4 reo_destination_sw4> Reo will push the frame into 277 the REO2SW4 ring 278 <enum 5 reo_destination_release> Reo will push the frame 279 into the REO_release ring 280 <enum 6 reo_destination_fw> Reo will push the frame into 281 the REO2FW ring 282 <enum 7 reo_destination_sw5> Reo will push the frame into 283 the REO2SW5 ring (REO remaps this in chips without REO2SW5 284 ring) 285 <enum 8 reo_destination_sw6> Reo will push the frame into 286 the REO2SW6 ring (REO remaps this in chips without REO2SW6 287 ring) 288 <enum 9 reo_destination_sw7> Reo will push the frame into 289 the REO2SW7 ring (REO remaps this in chips without REO2SW7 290 ring) 291 <enum 10 reo_destination_sw8> Reo will push the frame into 292 the REO2SW8 ring (REO remaps this in chips without REO2SW8 293 ring) 294 <enum 11 reo_destination_11> REO remaps this 295 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 296 REO remaps this 297 <enum 14 reo_destination_14> REO remaps this 298 <enum 15 reo_destination_15> REO remaps this 299 <enum 16 reo_destination_16> REO remaps this 300 <enum 17 reo_destination_17> REO remaps this 301 <enum 18 reo_destination_18> REO remaps this 302 <enum 19 reo_destination_19> REO remaps this 303 <enum 20 reo_destination_20> REO remaps this 304 <enum 21 reo_destination_21> REO remaps this 305 <enum 22 reo_destination_22> REO remaps this 306 <enum 23 reo_destination_23> REO remaps this 307 <enum 24 reo_destination_24> REO remaps this 308 <enum 25 reo_destination_25> REO remaps this 309 <enum 26 reo_destination_26> REO remaps this 310 <enum 27 reo_destination_27> REO remaps this 311 <enum 28 reo_destination_28> REO remaps this 312 <enum 29 reo_destination_29> REO remaps this 313 <enum 30 reo_destination_30> REO remaps this 314 <enum 31 reo_destination_31> REO remaps this 315 316 <legal all> 317 */ 318 319 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 320 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 321 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 322 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 323 324 325 /* Description LMAC_PEER_ID_MSB 326 327 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 328 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 329 hash[3:0]} using the chosen Toeplitz hash from Common Parser 330 if flow search fails. 331 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 332 's not 2'b00, Rx OLE uses a REO desination indication of 333 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz 334 hash from Common Parser if flow search fails. 335 <legal all> 336 */ 337 338 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 339 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 340 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 341 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 342 343 344 /* Description USE_FLOW_ID_TOEPLITZ_CLFY 345 346 Indication to Rx OLE to enable REO destination routing based 347 on the chosen Toeplitz hash from Common Parser, in case 348 flow search fails 349 <legal all> 350 */ 351 352 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 353 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 354 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 355 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 356 357 358 /* Description PKT_SELECTION_FP_UCAST_DATA 359 360 Filter pass Unicast data frame (matching rxpcu_filter_pass 361 and sw_frame_group_Unicast_data) routing selection 362 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 363 364 1'b0: source and destination rings are selected from the 365 RxOLE register settings for the packet type 366 367 1'b1: source ring and destination ring is selected from 368 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 369 fields in this STRUCT 370 <legal all> 371 */ 372 373 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 374 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 375 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 376 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 377 378 379 /* Description PKT_SELECTION_FP_MCAST_DATA 380 381 Filter pass Multicast data frame (matching rxpcu_filter_pass 382 and sw_frame_group_Multicast_data) routing selection 383 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 384 385 1'b0: source and destination rings are selected from the 386 RxOLE register settings for the packet type 387 388 1'b1: source ring and destination ring is selected from 389 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 390 fields in this STRUCT 391 <legal all> 392 */ 393 394 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 395 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 396 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 397 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 398 399 400 /* Description PKT_SELECTION_FP_1000 401 402 Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) 403 routing selection 404 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 405 406 1'b0: source and destination rings are selected from the 407 RxOLE register settings for the packet type 408 409 1'b1: source ring and destination ring is selected from 410 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 411 fields in this STRUCT 412 <legal all> 413 */ 414 415 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 416 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 417 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 418 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 419 420 421 /* Description RXDMA0_SOURCE_RING_SELECTION 422 423 Field only valid when for the received frame type the corresponding 424 pkt_selection_fp_... bit is set 425 426 <enum 0 sw2rxdma0_0_buf_source_ring> The data buffer for 427 this frame shall be sourced by sw2rxdma0 buffer source 428 ring. 429 <enum 1 fw2rxdma0_pmac0_buf_source_ring> The data buffer 430 for this frame shall be sourced by fw2rxdma buffer source 431 ring for PMAC0. 432 <enum 2 sw2rxdma0_1_buf_source_ring> The data buffer for 433 this frame shall be sourced by sw2rxdma1 buffer source 434 ring. 435 <enum 3 no_buffer_rxdma0_ring> The frame shall not be written 436 to any data buffer. 437 <enum 4 sw2rxdma0_exception_buf_source_ring> The data buffer 438 for this frame shall be sourced by sw2rxdma_exception buffer 439 source ring. 440 <enum 5 fw2rxdma0_pmac1_buf_source_ring> The data buffer 441 for this frame shall be sourced by fw2rxdma buffer source 442 ring for PMAC1. 443 444 <legal 0-5> 445 */ 446 447 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 448 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 449 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 450 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 451 452 453 /* Description RXDMA0_DESTINATION_RING_SELECTION 454 455 Field only valid when for the received frame type the corresponding 456 pkt_selection_fp_... bit is set 457 458 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 459 to the Release ring. Effectively this means the frame needs 460 to be dropped. 461 <enum 1 rxdma2fw_pmac0_ring> RXDMA0 shall push the frame 462 to the FW ring for PMAC0. 463 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to the 464 SW ring. 465 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 466 the REO entrance ring. 467 <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 468 to the FW ring for PMAC1. 469 <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 470 to the first MLO REO entrance ring. 471 <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 472 to the second MLO REO entrance ring. 473 474 <legal 0-6> 475 */ 476 477 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 478 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 479 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 480 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 481 482 483 /* Description MCAST_ECHO_DROP_ENABLE 484 485 If set, for multicast packets, multicast echo check (i.e. 486 SA search with mcast_echo_check = 1) shall be performed 487 by RXOLE, and any multicast echo packets should be indicated 488 to RXDMA for release to WBM 489 490 <legal all> 491 */ 492 493 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 494 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 495 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 496 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 497 498 499 /* Description WDS_LEARNING_DETECT_EN 500 501 If set, WDS learning detection based on SA search and notification 502 to FW (using RXDMA0 status ring) is enabled and the "timestamp" 503 field in address search failure cache-only entry should 504 be used to avoid multiple WDS learning notifications. 505 506 <legal all> 507 */ 508 509 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 510 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 511 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 512 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 513 514 515 /* Description INTRABSS_CHECK_EN 516 517 If set, intra-BSS routing detection is enabled 518 519 <legal all> 520 */ 521 522 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 523 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 524 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 525 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 526 527 528 /* Description USE_PPE 529 530 Indicates to RXDMA to ignore the REO_destination_indication 531 and use a programmed value corresponding to the REO2PPE 532 ring 533 534 This override to REO2PPE for packets requiring multiple 535 buffers shall be disabled based on an RXDMA configuration, 536 as PPE may not support such packets. 537 538 <legal all> 539 */ 540 541 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 542 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 543 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 544 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 545 546 547 /* Description PPE_ROUTING_ENABLE 548 549 Global enable/disable bit for routing to PPE, used to disable 550 PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' 551 552 553 This is set by SW for peers which are being handled by a 554 host SW/accelerator subsystem that also handles packet 555 buffer management for WiFi-to-PPE routing. 556 557 This is cleared by SW for peers which are being handled 558 by a different subsystem, completely disabling WiFi-to-PPE 559 routing for such peers. 560 561 <legal all> 562 */ 563 564 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 565 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 566 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 567 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 568 569 570 /* Description RESERVED_0B 571 572 <legal 0> 573 */ 574 575 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 576 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 577 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 578 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 579 580 581 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 582 583 In case of ndp or phy_err or AST_based_lookup_valid == 0, 584 this field will be set to 0 585 586 Address (lower 32 bits) of the REO queue descriptor. 587 588 If no Peer entry lookup happened for this frame, the value 589 wil be set to 0, and the frame shall never be pushed to 590 REO entrance ring. 591 <legal all> 592 */ 593 594 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 595 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 596 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 597 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 598 599 600 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 601 602 In case of ndp or phy_err or AST_based_lookup_valid == 0, 603 this field will be set to 0 604 605 Address (upper 8 bits) of the REO queue descriptor. 606 607 If no Peer entry lookup happened for this frame, the value 608 wil be set to 0, and the frame shall never be pushed to 609 REO entrance ring. 610 <legal all> 611 */ 612 613 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 614 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 615 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 616 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 617 618 619 /* Description RECEIVE_QUEUE_NUMBER 620 621 In case of ndp or phy_err or AST_based_lookup_valid == 0, 622 this field will be set to 0 623 624 Indicates the MPDU queue ID to which this MPDU link descriptor 625 belongs 626 Used for tracking and debugging 627 <legal all> 628 */ 629 630 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 631 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 632 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 633 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 634 635 636 /* Description PRE_DELIM_ERR_WARNING 637 638 Indicates that a delimiter FCS error was found in between 639 the Previous MPDU and this MPDU. 640 641 Note that this is just a warning, and does not mean that 642 this MPDU is corrupted in any way. If it is, there will 643 be other errors indicated such as FCS or decrypt errors 644 645 646 In case of ndp or phy_err, this field will indicate at least 647 one of delimiters located after the last MPDU in the previous 648 PPDU has been corrupted. 649 */ 650 651 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 652 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 653 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 654 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 655 656 657 /* Description FIRST_DELIM_ERR 658 659 Indicates that the first delimiter had a FCS failure. Only 660 valid when first_mpdu and first_msdu are set. 661 662 In case of ndp or phy_err, this field will never be set. 663 664 */ 665 666 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 667 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 668 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 669 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 670 671 672 /* Description RESERVED_2A 673 674 <legal 0> 675 */ 676 677 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 678 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 679 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 680 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 681 682 683 /* Description PN_31_0 684 685 Field only valid when Frame_encryption_info_valid is set 686 687 688 Bits [31:0] of the PN number extracted from the IV field 689 690 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 691 is valid. 692 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], 693 pn1}. Only pn[47:0] is valid. 694 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 695 pn0}. Only pn[47:0] is valid. 696 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 697 pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 698 pn[127:0] are valid. 699 700 In case of ndp or phy_err, this field will never be set. 701 702 */ 703 704 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c 705 #define RX_MPDU_INFO_PN_31_0_LSB 0 706 #define RX_MPDU_INFO_PN_31_0_MSB 31 707 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 708 709 710 /* Description PN_63_32 711 712 Field only valid when Frame_encryption_info_valid is set 713 714 715 Bits [63:32] of the PN number. See description for pn_31_0. 716 717 718 In case of ndp or phy_err, this field will never be set. 719 720 */ 721 722 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 723 #define RX_MPDU_INFO_PN_63_32_LSB 0 724 #define RX_MPDU_INFO_PN_63_32_MSB 31 725 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 726 727 728 /* Description PN_95_64 729 730 Field only valid when Frame_encryption_info_valid is set 731 732 733 Bits [95:64] of the PN number. See description for pn_31_0. 734 735 736 In case of ndp or phy_err, this field will never be set. 737 738 */ 739 740 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 741 #define RX_MPDU_INFO_PN_95_64_LSB 0 742 #define RX_MPDU_INFO_PN_95_64_MSB 31 743 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 744 745 746 /* Description PN_127_96 747 748 Field only valid when Frame_encryption_info_valid is set 749 750 751 Bits [127:96] of the PN number. See description for pn_31_0. 752 753 754 In case of ndp or phy_err, this field will never be set. 755 756 */ 757 758 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 759 #define RX_MPDU_INFO_PN_127_96_LSB 0 760 #define RX_MPDU_INFO_PN_127_96_MSB 31 761 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 762 763 764 /* Description EPD_EN 765 766 Field only valid when AST_based_lookup_valid == 1. 767 768 769 In case of ndp or phy_err or AST_based_lookup_valid == 0, 770 this field will be set to 0 771 772 If set to one use EPD instead of LPD 773 774 In case of ndp or phy_err, this field will never be set. 775 776 <legal all> 777 */ 778 779 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c 780 #define RX_MPDU_INFO_EPD_EN_LSB 0 781 #define RX_MPDU_INFO_EPD_EN_MSB 0 782 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 783 784 785 /* Description ALL_FRAMES_SHALL_BE_ENCRYPTED 786 787 In case of ndp or phy_err or AST_based_lookup_valid == 0, 788 this field will be set to 0 789 790 When set, all frames (data only ?) shall be encrypted. If 791 not, RX CRYPTO shall set an error flag. 792 <legal all> 793 */ 794 795 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 796 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 797 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 798 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 799 800 801 /* Description ENCRYPT_TYPE 802 803 In case of ndp or phy_err or AST_based_lookup_valid == 0, 804 this field will be set to 0 805 806 Indicates type of decrypt cipher used (as defined in the 807 peer entry) 808 809 <enum 0 wep_40> WEP 40-bit 810 <enum 1 wep_104> WEP 104-bit 811 <enum 2 tkip_no_mic> TKIP without MIC 812 <enum 3 wep_128> WEP 128-bit 813 <enum 4 tkip_with_mic> TKIP with MIC 814 <enum 5 wapi> WAPI 815 <enum 6 aes_ccmp_128> AES CCMP 128 816 <enum 7 no_cipher> No crypto 817 <enum 8 aes_ccmp_256> AES CCMP 256 818 <enum 9 aes_gcmp_128> AES CCMP 128 819 <enum 10 aes_gcmp_256> AES CCMP 256 820 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 821 822 <enum 12 wep_varied_width> WEP encryption. As for WEP per 823 keyid the key bit width can vary, the key bit width for 824 this MPDU will be indicated in field wep_key_width_for_variable 825 key 826 <legal 0-12> 827 */ 828 829 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c 830 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 831 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 832 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 833 834 835 /* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY 836 837 Field only valid when key_type is set to wep_varied_width. 838 839 840 This field indicates the size of the wep key for this MPDU. 841 842 843 <enum 0 wep_varied_width_40> WEP 40-bit 844 <enum 1 wep_varied_width_104> WEP 104-bit 845 <enum 2 wep_varied_width_128> WEP 128-bit 846 847 <legal 0-2> 848 */ 849 850 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 851 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 852 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 853 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 854 855 856 /* Description MESH_STA 857 858 In case of ndp or phy_err or AST_based_lookup_valid == 0, 859 this field will be set to 0 860 861 When set, this is a Mesh (11s) STA. 862 863 The interpretation of the A-MSDU 'Length' field in the MPDU 864 (if any) is decided by the e-numerations below. 865 866 <enum 0 MESH_DISABLE> 867 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes 868 the length of Mesh Control. 869 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes 870 the length of Mesh Control. 871 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and 872 excludes the length of Mesh Control. This is 802.11s-compliant. 873 874 <legal all> 875 */ 876 877 #define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c 878 #define RX_MPDU_INFO_MESH_STA_LSB 8 879 #define RX_MPDU_INFO_MESH_STA_MSB 9 880 #define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 881 882 883 /* Description BSSID_HIT 884 885 In case of ndp or phy_err or AST_based_lookup_valid == 0, 886 this field will be set to 0 887 888 When set, the BSSID of the incoming frame matched one of 889 the 8 BSSID register values 890 891 <legal all> 892 */ 893 894 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c 895 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 896 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 897 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 898 899 900 /* Description BSSID_NUMBER 901 902 Field only valid when bssid_hit is set. 903 904 This number indicates which one out of the 8 BSSID register 905 values matched the incoming frame 906 <legal all> 907 */ 908 909 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c 910 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 911 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 912 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 913 914 915 /* Description TID 916 917 Field only valid when mpdu_qos_control_valid is set 918 919 The TID field in the QoS control field 920 <legal all> 921 */ 922 923 #define RX_MPDU_INFO_TID_OFFSET 0x0000001c 924 #define RX_MPDU_INFO_TID_LSB 15 925 #define RX_MPDU_INFO_TID_MSB 18 926 #define RX_MPDU_INFO_TID_MASK 0x00078000 927 928 929 /* Description RESERVED_7A 930 931 <legal 0> 932 */ 933 934 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c 935 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 936 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 937 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 938 939 940 /* Description PEER_META_DATA 941 942 In case of ndp or phy_err or AST_based_lookup_valid == 0, 943 this field will be set to 0 944 945 Meta data that SW has programmed in the Peer table entry 946 of the transmitting STA. 947 <legal all> 948 */ 949 950 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 951 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 952 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 953 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 954 955 956 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 957 958 Field indicates what the reason was that this MPDU frame 959 was allowed to come into the receive path by RXPCU 960 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 961 filter programming of rxpcu 962 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 963 regular frame filter and would have been dropped, were 964 it not for the frame fitting into the 'monitor_client' category. 965 966 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 967 regular frame filter and also did not pass the rxpcu_monitor_client 968 filter. It would have been dropped accept that it did pass 969 the 'monitor_other' category. 970 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 971 the normal frame filter programming of RXPCU but additionally 972 fit into the 'monitor_override_client' category. 973 974 Note: for ndp frame, if it was expected because the preceding 975 NDPA was filter_pass, the setting rxpcu_filter_pass will 976 be used. This setting will also be used for every ndp frame 977 in case Promiscuous mode is enabled. 978 979 In case promiscuous is not enabled, and an NDP is not preceded 980 by a NPDA filter pass frame, the only other setting that 981 could appear here for the NDP is rxpcu_monitor_other. 982 (rxpcu has a configuration bit specifically for this scenario) 983 984 985 Note: for 986 <legal 0-3> 987 */ 988 989 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 990 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 991 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 992 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 993 994 995 /* Description SW_FRAME_GROUP_ID 996 997 SW processes frames based on certain classifications. This 998 field indicates to what sw classification this MPDU is 999 mapped. 1000 The classification is given in priority order 1001 1002 <enum 0 sw_frame_group_NDP_frame> Note: The corresponding 1003 Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass 1004 or rxpcu_monitor_other 1005 1006 <enum 1 sw_frame_group_Multicast_data> 1007 <enum 2 sw_frame_group_Unicast_data> 1008 <enum 3 sw_frame_group_Null_data > This includes mpdus of 1009 type Data Null. 1010 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 1011 Null frames except in UL MU or TB PPDUs. 1012 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 1013 QoS Null frames in UL MU or TB PPDUs. 1014 1015 <enum 4 sw_frame_group_mgmt_0000 > 1016 <enum 5 sw_frame_group_mgmt_0001 > 1017 <enum 6 sw_frame_group_mgmt_0010 > 1018 <enum 7 sw_frame_group_mgmt_0011 > 1019 <enum 8 sw_frame_group_mgmt_0100 > 1020 <enum 9 sw_frame_group_mgmt_0101 > 1021 <enum 10 sw_frame_group_mgmt_0110 > 1022 <enum 11 sw_frame_group_mgmt_0111 > 1023 <enum 12 sw_frame_group_mgmt_1000 > 1024 <enum 13 sw_frame_group_mgmt_1001 > 1025 <enum 14 sw_frame_group_mgmt_1010 > 1026 <enum 15 sw_frame_group_mgmt_1011 > 1027 <enum 16 sw_frame_group_mgmt_1100 > 1028 <enum 17 sw_frame_group_mgmt_1101 > 1029 <enum 18 sw_frame_group_mgmt_1110 > 1030 <enum 19 sw_frame_group_mgmt_1111 > 1031 1032 <enum 20 sw_frame_group_ctrl_0000 > 1033 <enum 21 sw_frame_group_ctrl_0001 > 1034 <enum 22 sw_frame_group_ctrl_0010 > 1035 <enum 23 sw_frame_group_ctrl_0011 > 1036 <enum 24 sw_frame_group_ctrl_0100 > 1037 <enum 25 sw_frame_group_ctrl_0101 > 1038 <enum 26 sw_frame_group_ctrl_0110 > 1039 <enum 27 sw_frame_group_ctrl_0111 > 1040 <enum 28 sw_frame_group_ctrl_1000 > 1041 <enum 29 sw_frame_group_ctrl_1001 > 1042 <enum 30 sw_frame_group_ctrl_1010 > 1043 <enum 31 sw_frame_group_ctrl_1011 > 1044 <enum 32 sw_frame_group_ctrl_1100 > 1045 <enum 33 sw_frame_group_ctrl_1101 > 1046 <enum 34 sw_frame_group_ctrl_1110 > 1047 <enum 35 sw_frame_group_ctrl_1111 > 1048 1049 <enum 36 sw_frame_group_unsupported> This covers type 3 1050 and protocol version != 0 1051 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 1052 only be rxpcu_monitor_other 1053 1054 <enum 37 sw_frame_group_phy_error> PHY reported an error 1055 1056 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 1057 be rxpcu_filter_pass 1058 1059 <legal 0-39> 1060 */ 1061 1062 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 1063 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 1064 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 1065 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 1066 1067 1068 /* Description NDP_FRAME 1069 1070 When set, the received frame was an NDP frame, and thus 1071 there will be no MPDU data. 1072 TODO: Should this be extended to 2-bit e-num? 1073 <legal all> 1074 */ 1075 1076 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 1077 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 1078 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 1079 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 1080 1081 1082 /* Description PHY_ERR 1083 1084 When set, a PHY error was received before MAC received any 1085 data, and thus there will be no MPDU data. 1086 <legal all> 1087 */ 1088 1089 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 1090 #define RX_MPDU_INFO_PHY_ERR_LSB 10 1091 #define RX_MPDU_INFO_PHY_ERR_MSB 10 1092 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 1093 1094 1095 /* Description PHY_ERR_DURING_MPDU_HEADER 1096 1097 When set, a PHY error was received before MAC received the 1098 complete MPDU header which was needed for proper decoding 1099 1100 <legal all> 1101 */ 1102 1103 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 1104 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 1105 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 1106 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 1107 1108 1109 /* Description PROTOCOL_VERSION_ERR 1110 1111 Set when RXPCU detected a version error in the Frame control 1112 field 1113 <legal all> 1114 */ 1115 1116 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 1117 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 1118 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 1119 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 1120 1121 1122 /* Description AST_BASED_LOOKUP_VALID 1123 1124 When set, AST based lookup for this frame has found a valid 1125 result. 1126 1127 Note that for NDP frame this will never be set 1128 <legal all> 1129 */ 1130 1131 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 1132 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 1133 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 1134 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 1135 1136 1137 /* Description RANGING 1138 1139 When set, a ranging NDPA or a ranging NDP was received. 1140 1141 This field is only for FW visibility. HW is not expected 1142 to take any action on this. 1143 <legal all> 1144 */ 1145 1146 #define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 1147 #define RX_MPDU_INFO_RANGING_LSB 14 1148 #define RX_MPDU_INFO_RANGING_MSB 14 1149 #define RX_MPDU_INFO_RANGING_MASK 0x00004000 1150 1151 1152 /* Description RESERVED_9A 1153 1154 <legal 0> 1155 */ 1156 1157 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 1158 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 1159 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 1160 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 1161 1162 1163 /* Description PHY_PPDU_ID 1164 1165 A ppdu counter value that PHY increments for every PPDU 1166 received. The counter value wraps around 1167 <legal all> 1168 */ 1169 1170 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 1171 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 1172 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 1173 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 1174 1175 1176 /* Description AST_INDEX 1177 1178 This field indicates the index of the AST entry corresponding 1179 to this MPDU. It is provided by the GSE module instantiated 1180 in RXPCU. 1181 A value of 0xFFFF indicates an invalid AST index, meaning 1182 that No AST entry was found or NO AST search was performed 1183 1184 1185 In case of ndp or phy_err, this field will be set to 0xFFFF 1186 1187 <legal all> 1188 */ 1189 1190 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 1191 #define RX_MPDU_INFO_AST_INDEX_LSB 0 1192 #define RX_MPDU_INFO_AST_INDEX_MSB 15 1193 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 1194 1195 1196 /* Description SW_PEER_ID 1197 1198 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1199 this field will be set to 0 1200 1201 This field indicates a unique peer identifier. It is set 1202 equal to field 'sw_peer_id' from the AST entry 1203 1204 <legal all> 1205 */ 1206 1207 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 1208 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 1209 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 1210 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 1211 1212 1213 /* Description MPDU_FRAME_CONTROL_VALID 1214 1215 When set, the field Mpdu_Frame_control_field has valid information 1216 1217 1218 In case of ndp or phy_err, this field will never be set. 1219 1220 <legal all> 1221 */ 1222 1223 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 1224 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 1225 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 1226 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 1227 1228 1229 /* Description MPDU_DURATION_VALID 1230 1231 When set, the field Mpdu_duration_field has valid information 1232 1233 1234 In case of ndp or phy_err, this field will never be set. 1235 1236 <legal all> 1237 */ 1238 1239 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c 1240 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 1241 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 1242 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 1243 1244 1245 /* Description MAC_ADDR_AD1_VALID 1246 1247 When set, the fields mac_addr_ad1_..... have valid information 1248 1249 1250 In case of ndp or phy_err, this field will never be set. 1251 1252 <legal all> 1253 */ 1254 1255 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 1256 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 1257 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 1258 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 1259 1260 1261 /* Description MAC_ADDR_AD2_VALID 1262 1263 When set, the fields mac_addr_ad2_..... have valid information 1264 1265 1266 For MPDUs without Address 2, this field will not be set. 1267 1268 1269 In case of ndp or phy_err, this field will never be set. 1270 1271 <legal all> 1272 */ 1273 1274 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 1275 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 1276 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 1277 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 1278 1279 1280 /* Description MAC_ADDR_AD3_VALID 1281 1282 When set, the fields mac_addr_ad3_..... have valid information 1283 1284 1285 For MPDUs without Address 3, this field will not be set. 1286 1287 1288 In case of ndp or phy_err, this field will never be set. 1289 1290 <legal all> 1291 */ 1292 1293 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 1294 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 1295 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 1296 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 1297 1298 1299 /* Description MAC_ADDR_AD4_VALID 1300 1301 When set, the fields mac_addr_ad4_..... have valid information 1302 1303 1304 For MPDUs without Address 4, this field will not be set. 1305 1306 1307 In case of ndp or phy_err, this field will never be set. 1308 1309 <legal all> 1310 */ 1311 1312 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 1313 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 1314 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 1315 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 1316 1317 1318 /* Description MPDU_SEQUENCE_CONTROL_VALID 1319 1320 When set, the fields mpdu_sequence_control_field and mpdu_sequence_number 1321 have valid information as well as field 1322 1323 For MPDUs without a sequence control field, this field will 1324 not be set. 1325 1326 In case of ndp or phy_err, this field will never be set. 1327 1328 <legal all> 1329 */ 1330 1331 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 1332 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 1333 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 1334 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 1335 1336 1337 /* Description MPDU_QOS_CONTROL_VALID 1338 1339 When set, the field mpdu_qos_control_field has valid information 1340 1341 1342 For MPDUs without a QoS control field, this field will not 1343 be set. 1344 1345 In case of ndp or phy_err, this field will never be set. 1346 1347 <legal all> 1348 */ 1349 1350 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 1351 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 1352 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 1353 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 1354 1355 1356 /* Description MPDU_HT_CONTROL_VALID 1357 1358 When set, the field mpdu_HT_control_field has valid information 1359 1360 1361 For MPDUs without a HT control field, this field will not 1362 be set. 1363 1364 In case of ndp or phy_err, this field will never be set. 1365 1366 <legal all> 1367 */ 1368 1369 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 1370 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 1371 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 1372 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 1373 1374 1375 /* Description FRAME_ENCRYPTION_INFO_VALID 1376 1377 When set, the encryption related info fields, like IV and 1378 PN are valid 1379 1380 For MPDUs that are not encrypted, this will not be set. 1381 1382 In case of ndp or phy_err, this field will never be set. 1383 1384 <legal all> 1385 */ 1386 1387 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 1388 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 1389 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 1390 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 1391 1392 1393 /* Description MPDU_FRAGMENT_NUMBER 1394 1395 Field only valid when Mpdu_sequence_control_valid is set 1396 AND Fragment_flag is set 1397 1398 The fragment number from the 802.11 header 1399 1400 <legal all> 1401 */ 1402 1403 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 1404 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 1405 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 1406 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 1407 1408 1409 /* Description MORE_FRAGMENT_FLAG 1410 1411 The More Fragment bit setting from the MPDU header of the 1412 received frame 1413 1414 <legal all> 1415 */ 1416 1417 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 1418 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 1419 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 1420 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 1421 1422 1423 /* Description RESERVED_11A 1424 1425 <legal 0> 1426 */ 1427 1428 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c 1429 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 1430 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 1431 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 1432 1433 1434 /* Description FR_DS 1435 1436 Field only valid when Mpdu_frame_control_valid is set 1437 1438 Set if the from DS bit is set in the frame control. 1439 <legal all> 1440 */ 1441 1442 #define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c 1443 #define RX_MPDU_INFO_FR_DS_LSB 16 1444 #define RX_MPDU_INFO_FR_DS_MSB 16 1445 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 1446 1447 1448 /* Description TO_DS 1449 1450 Field only valid when Mpdu_frame_control_valid is set 1451 1452 Set if the to DS bit is set in the frame control. 1453 <legal all> 1454 */ 1455 1456 #define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c 1457 #define RX_MPDU_INFO_TO_DS_LSB 17 1458 #define RX_MPDU_INFO_TO_DS_MSB 17 1459 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 1460 1461 1462 /* Description ENCRYPTED 1463 1464 Field only valid when Mpdu_frame_control_valid is set. 1465 1466 Protected bit from the frame control. 1467 <legal all> 1468 */ 1469 1470 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c 1471 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 1472 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 1473 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 1474 1475 1476 /* Description MPDU_RETRY 1477 1478 Field only valid when Mpdu_frame_control_valid is set. 1479 1480 Retry bit from the frame control. Only valid when first_msdu 1481 is set. 1482 <legal all> 1483 */ 1484 1485 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c 1486 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 1487 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 1488 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 1489 1490 1491 /* Description MPDU_SEQUENCE_NUMBER 1492 1493 Field only valid when Mpdu_sequence_control_valid is set. 1494 1495 1496 The sequence number from the 802.11 header. 1497 <legal all> 1498 */ 1499 1500 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 1501 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 1502 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 1503 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 1504 1505 1506 /* Description KEY_ID_OCTET 1507 1508 Field only valid when Frame_encryption_info_valid is set 1509 1510 1511 The key ID octet from the IV. 1512 1513 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1514 this field will be set to 0 1515 <legal all> 1516 */ 1517 1518 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 1519 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 1520 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 1521 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 1522 1523 1524 /* Description NEW_PEER_ENTRY 1525 1526 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1527 this field will be set to 0 1528 1529 Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 1530 doesn't follow so RX DECRYPTION module either uses old 1531 peer entry or not decrypt. 1532 <legal all> 1533 */ 1534 1535 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 1536 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 1537 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 1538 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 1539 1540 1541 /* Description DECRYPT_NEEDED 1542 1543 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1544 this field will be set to 0 1545 1546 Set if decryption is needed. 1547 1548 Note: 1549 When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', 1550 RXPCU will also ensure that this bit is NOT set 1551 CRYPTO for that reason only needs to evaluate this bit and 1552 non of the other ones. 1553 <legal all> 1554 */ 1555 1556 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 1557 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 1558 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 1559 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 1560 1561 1562 /* Description DECAP_TYPE 1563 1564 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1565 this field will be set to 0 1566 1567 Used by the OLE during decapsulation. 1568 1569 Indicates the decapsulation that HW will perform: 1570 1571 <enum 0 RAW> No encapsulation 1572 <enum 1 Native_WiFi> 1573 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1574 1575 <enum 3 802_3> Indicate Ethernet 1576 1577 <legal all> 1578 */ 1579 1580 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 1581 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 1582 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 1583 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 1584 1585 1586 /* Description RX_INSERT_VLAN_C_TAG_PADDING 1587 1588 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1589 this field will be set to 0 1590 1591 Insert 4 byte of all zeros as VLAN tag if the rx payload 1592 does not have VLAN. Used during decapsulation. 1593 <legal all> 1594 */ 1595 1596 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 1597 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1598 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 1599 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 1600 1601 1602 /* Description RX_INSERT_VLAN_S_TAG_PADDING 1603 1604 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1605 this field will be set to 0 1606 1607 Insert 4 byte of all zeros as double VLAN tag if the rx 1608 payload does not have VLAN. Used during 1609 <legal all> 1610 */ 1611 1612 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 1613 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1614 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 1615 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 1616 1617 1618 /* Description STRIP_VLAN_C_TAG_DECAP 1619 1620 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1621 this field will be set to 0 1622 1623 Strip the VLAN during decapsulation. Used by the OLE. 1624 <legal all> 1625 */ 1626 1627 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 1628 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 1629 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 1630 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 1631 1632 1633 /* Description STRIP_VLAN_S_TAG_DECAP 1634 1635 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1636 this field will be set to 0 1637 1638 Strip the double VLAN during decapsulation. Used by the 1639 OLE. 1640 <legal all> 1641 */ 1642 1643 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 1644 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 1645 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 1646 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 1647 1648 1649 /* Description PRE_DELIM_COUNT 1650 1651 The number of delimiters before this MPDU. 1652 1653 Note that this number is cleared at PPDU start. 1654 1655 If this MPDU is the first received MPDU in the PPDU and 1656 this MPDU gets filtered-in, this field will indicate the 1657 number of delimiters located after the last MPDU in the 1658 previous PPDU. 1659 1660 If this MPDU is located after the first received MPDU in 1661 an PPDU, this field will indicate the number of delimiters 1662 located between the previous MPDU and this MPDU. 1663 1664 In case of ndp or phy_err, this field will indicate the 1665 number of delimiters located after the last MPDU in the 1666 previous PPDU. 1667 <legal all> 1668 */ 1669 1670 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 1671 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 1672 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 1673 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 1674 1675 1676 /* Description AMPDU_FLAG 1677 1678 When set, received frame was part of an A-MPDU. 1679 1680 In case of ndp or phy_err, this field will never be set. 1681 1682 <legal all> 1683 */ 1684 1685 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 1686 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 1687 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 1688 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 1689 1690 1691 /* Description BAR_FRAME 1692 1693 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1694 this field will be set to 0 1695 1696 When set, received frame is a BAR frame 1697 <legal all> 1698 */ 1699 1700 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 1701 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 1702 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 1703 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 1704 1705 1706 /* Description RAW_MPDU 1707 1708 Consumer: SW 1709 Producer: RXOLE 1710 1711 RXPCU sets this field to 0 and RXOLE overwrites it. 1712 1713 Set to 1 by RXOLE when it has not performed any 802.11 to 1714 Ethernet/Natvie WiFi header conversion on this MPDU. 1715 <legal all> 1716 */ 1717 1718 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 1719 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 1720 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 1721 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 1722 1723 1724 /* Description RESERVED_12 1725 1726 <legal 0> 1727 */ 1728 1729 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 1730 #define RX_MPDU_INFO_RESERVED_12_LSB 31 1731 #define RX_MPDU_INFO_RESERVED_12_MSB 31 1732 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 1733 1734 1735 /* Description MPDU_LENGTH 1736 1737 In case of ndp or phy_err this field will be set to 0 1738 1739 MPDU length before decapsulation. 1740 <legal all> 1741 */ 1742 1743 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 1744 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 1745 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 1746 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 1747 1748 1749 /* Description FIRST_MPDU 1750 1751 See definition in RX attention descriptor 1752 1753 In case of ndp or phy_err, this field will be set. Note 1754 however that there will not actually be any data contents 1755 in the MPDU. 1756 <legal all> 1757 */ 1758 1759 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 1760 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 1761 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 1762 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 1763 1764 1765 /* Description MCAST_BCAST 1766 1767 In case of ndp or phy_err or Phy_err_during_mpdu_header 1768 this field will be set to 0 1769 1770 See definition in RX attention descriptor 1771 <legal all> 1772 */ 1773 1774 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 1775 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 1776 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 1777 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 1778 1779 1780 /* Description AST_INDEX_NOT_FOUND 1781 1782 In case of ndp or phy_err or Phy_err_during_mpdu_header 1783 this field will be set to 0 1784 1785 See definition in RX attention descriptor 1786 <legal all> 1787 */ 1788 1789 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 1790 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 1791 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 1792 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 1793 1794 1795 /* Description AST_INDEX_TIMEOUT 1796 1797 In case of ndp or phy_err or Phy_err_during_mpdu_header 1798 this field will be set to 0 1799 1800 See definition in RX attention descriptor 1801 <legal all> 1802 */ 1803 1804 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 1805 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 1806 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 1807 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 1808 1809 1810 /* Description POWER_MGMT 1811 1812 In case of ndp or phy_err or Phy_err_during_mpdu_header 1813 this field will be set to 0 1814 1815 See definition in RX attention descriptor 1816 <legal all> 1817 */ 1818 1819 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 1820 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 1821 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 1822 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 1823 1824 1825 /* Description NON_QOS 1826 1827 In case of ndp or phy_err or Phy_err_during_mpdu_header 1828 this field will be set to 1 1829 1830 See definition in RX attention descriptor 1831 <legal all> 1832 */ 1833 1834 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 1835 #define RX_MPDU_INFO_NON_QOS_LSB 19 1836 #define RX_MPDU_INFO_NON_QOS_MSB 19 1837 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 1838 1839 1840 /* Description NULL_DATA 1841 1842 In case of ndp or phy_err or Phy_err_during_mpdu_header 1843 this field will be set to 0 1844 1845 See definition in RX attention descriptor 1846 <legal all> 1847 */ 1848 1849 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 1850 #define RX_MPDU_INFO_NULL_DATA_LSB 20 1851 #define RX_MPDU_INFO_NULL_DATA_MSB 20 1852 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 1853 1854 1855 /* Description MGMT_TYPE 1856 1857 In case of ndp or phy_err or Phy_err_during_mpdu_header 1858 this field will be set to 0 1859 1860 See definition in RX attention descriptor 1861 <legal all> 1862 */ 1863 1864 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 1865 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 1866 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 1867 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 1868 1869 1870 /* Description CTRL_TYPE 1871 1872 In case of ndp or phy_err or Phy_err_during_mpdu_header 1873 this field will be set to 0 1874 1875 See definition in RX attention descriptor 1876 <legal all> 1877 */ 1878 1879 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 1880 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 1881 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 1882 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 1883 1884 1885 /* Description MORE_DATA 1886 1887 In case of ndp or phy_err or Phy_err_during_mpdu_header 1888 this field will be set to 0 1889 1890 See definition in RX attention descriptor 1891 <legal all> 1892 */ 1893 1894 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 1895 #define RX_MPDU_INFO_MORE_DATA_LSB 23 1896 #define RX_MPDU_INFO_MORE_DATA_MSB 23 1897 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 1898 1899 1900 /* Description EOSP 1901 1902 In case of ndp or phy_err or Phy_err_during_mpdu_header 1903 this field will be set to 0 1904 1905 See definition in RX attention descriptor 1906 <legal all> 1907 */ 1908 1909 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 1910 #define RX_MPDU_INFO_EOSP_LSB 24 1911 #define RX_MPDU_INFO_EOSP_MSB 24 1912 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 1913 1914 1915 /* Description FRAGMENT_FLAG 1916 1917 In case of ndp or phy_err or Phy_err_during_mpdu_header 1918 this field will be set to 0 1919 1920 See definition in RX attention descriptor 1921 <legal all> 1922 */ 1923 1924 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 1925 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 1926 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 1927 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 1928 1929 1930 /* Description ORDER 1931 1932 In case of ndp or phy_err or Phy_err_during_mpdu_header 1933 this field will be set to 0 1934 1935 See definition in RX attention descriptor 1936 1937 <legal all> 1938 */ 1939 1940 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 1941 #define RX_MPDU_INFO_ORDER_LSB 26 1942 #define RX_MPDU_INFO_ORDER_MSB 26 1943 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 1944 1945 1946 /* Description U_APSD_TRIGGER 1947 1948 In case of ndp or phy_err or Phy_err_during_mpdu_header 1949 this field will be set to 0 1950 1951 See definition in RX attention descriptor 1952 <legal all> 1953 */ 1954 1955 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 1956 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 1957 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 1958 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 1959 1960 1961 /* Description ENCRYPT_REQUIRED 1962 1963 In case of ndp or phy_err or Phy_err_during_mpdu_header 1964 this field will be set to 0 1965 1966 See definition in RX attention descriptor 1967 <legal all> 1968 */ 1969 1970 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 1971 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 1972 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 1973 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 1974 1975 1976 /* Description DIRECTED 1977 1978 In case of ndp or phy_err or Phy_err_during_mpdu_header 1979 this field will be set to 0 1980 1981 See definition in RX attention descriptor 1982 <legal all> 1983 */ 1984 1985 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 1986 #define RX_MPDU_INFO_DIRECTED_LSB 29 1987 #define RX_MPDU_INFO_DIRECTED_MSB 29 1988 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 1989 1990 1991 /* Description AMSDU_PRESENT 1992 1993 Field only valid when Mpdu_qos_control_valid is set 1994 1995 The 'amsdu_present' bit within the QoS control field of 1996 the MPDU 1997 <legal all> 1998 */ 1999 2000 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 2001 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 2002 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 2003 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 2004 2005 2006 /* Description RESERVED_13 2007 2008 Field only valid when Mpdu_qos_control_valid is set 2009 2010 This indicates whether the 'Ack policy' field within the 2011 QoS control field of the MPDU indicates 'no-Ack.' 2012 <legal all> 2013 */ 2014 2015 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 2016 #define RX_MPDU_INFO_RESERVED_13_LSB 31 2017 #define RX_MPDU_INFO_RESERVED_13_MSB 31 2018 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 2019 2020 2021 /* Description MPDU_FRAME_CONTROL_FIELD 2022 2023 Field only valid when Mpdu_frame_control_valid is set 2024 2025 The frame control field of this received MPDU. 2026 2027 Field only valid when Ndp_frame and phy_err are NOT set 2028 2029 Bytes 0 + 1 of the received MPDU 2030 <legal all> 2031 */ 2032 2033 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 2034 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 2035 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 2036 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 2037 2038 2039 /* Description MPDU_DURATION_FIELD 2040 2041 Field only valid when Mpdu_duration_valid is set 2042 2043 The duration field of this received MPDU. 2044 <legal all> 2045 */ 2046 2047 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 2048 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 2049 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 2050 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 2051 2052 2053 /* Description MAC_ADDR_AD1_31_0 2054 2055 Field only valid when mac_addr_ad1_valid is set 2056 2057 The Least Significant 4 bytes of the Received Frames MAC 2058 Address AD1 2059 <legal all> 2060 */ 2061 2062 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 2063 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 2064 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 2065 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 2066 2067 2068 /* Description MAC_ADDR_AD1_47_32 2069 2070 Field only valid when mac_addr_ad1_valid is set 2071 2072 The 2 most significant bytes of the Received Frames MAC 2073 Address AD1 2074 <legal all> 2075 */ 2076 2077 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 2078 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 2079 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 2080 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 2081 2082 2083 /* Description MAC_ADDR_AD2_15_0 2084 2085 Field only valid when mac_addr_ad2_valid is set 2086 2087 The Least Significant 2 bytes of the Received Frames MAC 2088 Address AD2 2089 <legal all> 2090 */ 2091 2092 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 2093 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 2094 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 2095 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 2096 2097 2098 /* Description MAC_ADDR_AD2_47_16 2099 2100 Field only valid when mac_addr_ad2_valid is set 2101 2102 The 4 most significant bytes of the Received Frames MAC 2103 Address AD2 2104 <legal all> 2105 */ 2106 2107 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 2108 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 2109 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 2110 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 2111 2112 2113 /* Description MAC_ADDR_AD3_31_0 2114 2115 Field only valid when mac_addr_ad3_valid is set 2116 2117 The Least Significant 4 bytes of the Received Frames MAC 2118 Address AD3 2119 <legal all> 2120 */ 2121 2122 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 2123 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 2124 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 2125 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 2126 2127 2128 /* Description MAC_ADDR_AD3_47_32 2129 2130 Field only valid when mac_addr_ad3_valid is set 2131 2132 The 2 most significant bytes of the Received Frames MAC 2133 Address AD3 2134 <legal all> 2135 */ 2136 2137 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 2138 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 2139 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 2140 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 2141 2142 2143 /* Description MPDU_SEQUENCE_CONTROL_FIELD 2144 2145 Field only valid when mpdu_sequence_control_valid is set 2146 2147 2148 The sequence control field of the MPDU 2149 <legal all> 2150 */ 2151 2152 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 2153 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 2154 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 2155 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 2156 2157 2158 /* Description MAC_ADDR_AD4_31_0 2159 2160 Field only valid when mac_addr_ad4_valid is set 2161 2162 The Least Significant 4 bytes of the Received Frames MAC 2163 Address AD4 2164 <legal all> 2165 */ 2166 2167 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 2168 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 2169 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 2170 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 2171 2172 2173 /* Description MAC_ADDR_AD4_47_32 2174 2175 Field only valid when mac_addr_ad4_valid is set 2176 2177 The 2 most significant bytes of the Received Frames MAC 2178 Address AD4 2179 <legal all> 2180 */ 2181 2182 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 2183 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 2184 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 2185 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 2186 2187 2188 /* Description MPDU_QOS_CONTROL_FIELD 2189 2190 Field only valid when mpdu_qos_control_valid is set 2191 2192 The sequence control field of the MPDU 2193 <legal all> 2194 */ 2195 2196 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 2197 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 2198 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 2199 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 2200 2201 2202 /* Description MPDU_HT_CONTROL_FIELD 2203 2204 Field only valid when mpdu_qos_control_valid is set 2205 2206 The HT control field of the MPDU 2207 <legal all> 2208 */ 2209 2210 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 2211 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 2212 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 2213 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 2214 2215 2216 /* Description VDEV_ID 2217 2218 Consumer: RXOLE 2219 Producer: FW 2220 2221 Virtual device associated with this peer 2222 2223 RXOLE uses this to determine intra-BSS routing. 2224 2225 <legal all> 2226 */ 2227 2228 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 2229 #define RX_MPDU_INFO_VDEV_ID_LSB 0 2230 #define RX_MPDU_INFO_VDEV_ID_MSB 7 2231 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 2232 2233 2234 /* Description SERVICE_CODE 2235 2236 Opaque service code between PPE and Wi-Fi 2237 2238 This field gets passed on by REO to PPE in the EDMA descriptor 2239 ('REO_TO_PPE_RING'). 2240 2241 <legal all> 2242 */ 2243 2244 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 2245 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 2246 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 2247 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 2248 2249 2250 /* Description PRIORITY_VALID 2251 2252 This field gets passed on by REO to PPE in the EDMA descriptor 2253 ('REO_TO_PPE_RING'). 2254 2255 <legal all> 2256 */ 2257 2258 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 2259 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 2260 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 2261 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 2262 2263 2264 /* Description SRC_INFO 2265 2266 Source (virtual) device/interface info. associated with 2267 this peer 2268 2269 This field gets passed on by REO to PPE in the EDMA descriptor 2270 ('REO_TO_PPE_RING'). 2271 2272 <legal all> 2273 */ 2274 2275 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 2276 #define RX_MPDU_INFO_SRC_INFO_LSB 18 2277 #define RX_MPDU_INFO_SRC_INFO_MSB 29 2278 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 2279 2280 2281 /* Description RESERVED_23A 2282 2283 <legal 0> 2284 */ 2285 2286 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 2287 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 2288 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 2289 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 2290 2291 2292 /* Description MULTI_LINK_ADDR_AD1_AD2_VALID 2293 2294 If set, Rx OLE shall convert Address1 and Address2 of received 2295 data frames to multi-link addresses during decapsulation 2296 to Ethernet or Native WiFi 2297 <legal all> 2298 */ 2299 2300 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c 2301 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 2302 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 2303 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 2304 2305 2306 /* Description MULTI_LINK_ADDR_AD1_31_0 2307 2308 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2309 2310 2311 Multi-link receiver address (address1), bits [31:0] 2312 */ 2313 2314 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 2315 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 2316 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 2317 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff 2318 2319 2320 /* Description MULTI_LINK_ADDR_AD1_47_32 2321 2322 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2323 2324 2325 Multi-link receiver address (address1), bits [47:32] 2326 */ 2327 2328 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 2329 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 2330 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 2331 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff 2332 2333 2334 /* Description MULTI_LINK_ADDR_AD2_15_0 2335 2336 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2337 2338 2339 Multi-link transmitter address (address2), bits [15:0] 2340 */ 2341 2342 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 2343 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 2344 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 2345 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 2346 2347 2348 /* Description MULTI_LINK_ADDR_AD2_47_16 2349 2350 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2351 2352 2353 Multi-link transmitter address (address2), bits [47:16] 2354 */ 2355 2356 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 2357 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 2358 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 2359 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff 2360 2361 2362 /* Description AUTHORIZED_TO_SEND_WDS 2363 2364 If not set, RXDMA shall perform error-routing for WDS packets 2365 as the sender is not authorized and might misuse WDS frame 2366 format to inject packets with arbitrary DA/SA. 2367 <legal all> 2368 */ 2369 2370 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c 2371 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 2372 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 2373 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 2374 2375 2376 /* Description RESERVED_27A 2377 2378 Bit 1: disallow_mcbc_da_in_unicast_mpdu: 2379 2380 If set, RX OLE shall disallow multicast/broadcast DA in 2381 A-MSDU subframes in case of ToDS=0 MPDUs. This may be enabled 2382 for TDLS peers. 2383 <legal 0-1> 2384 */ 2385 2386 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 2387 #define RX_MPDU_INFO_RESERVED_27A_LSB 1 2388 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 2389 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe 2390 2391 2392 /* Description RESERVED_28A 2393 2394 <legal 0> 2395 */ 2396 2397 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 2398 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 2399 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 2400 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 2401 2402 2403 /* Description RESERVED_29A 2404 2405 <legal 0> 2406 */ 2407 2408 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 2409 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 2410 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 2411 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 2412 2413 2414 2415 #endif // RX_MPDU_INFO 2416