1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_LINK_PTR_H_ 18 #define _RX_MPDU_LINK_PTR_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 24 25 26 struct rx_mpdu_link_ptr { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct buffer_addr_info mpdu_link_desc_addr_info; 29 #else 30 struct buffer_addr_info mpdu_link_desc_addr_info; 31 #endif 32 }; 33 34 35 /* Description MPDU_LINK_DESC_ADDR_INFO 36 37 Details of the physical address of an MPDU link descriptor 38 39 */ 40 41 42 /* Description BUFFER_ADDR_31_0 43 44 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 45 descriptor OR Link Descriptor 46 47 In case of 'NULL' pointer, this field is set to 0 48 <legal all> 49 */ 50 51 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 52 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 53 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 54 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 55 56 57 /* Description BUFFER_ADDR_39_32 58 59 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 60 descriptor OR Link Descriptor 61 62 In case of 'NULL' pointer, this field is set to 0 63 <legal all> 64 */ 65 66 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 67 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 68 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 69 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 70 71 72 /* Description RETURN_BUFFER_MANAGER 73 74 Consumer: WBM 75 Producer: SW/FW 76 77 In case of 'NULL' pointer, this field is set to 0 78 79 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 80 descriptor OR link descriptor that is being pointed to 81 shall be returned after the frame has been processed. It 82 is used by WBM for routing purposes. 83 84 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 85 to the WMB buffer idle list 86 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 87 to the WBM idle link descriptor idle list, where the chip 88 0 WBM is chosen in case of a multi-chip config 89 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 90 to the chip 1 WBM idle link descriptor idle list 91 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 92 to the chip 2 WBM idle link descriptor idle list 93 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 94 returned to chip 3 WBM idle link descriptor idle list 95 <enum 4 FW_BM> This buffer shall be returned to the FW 96 <enum 5 SW0_BM> This buffer shall be returned to the SW, 97 ring 0 98 <enum 6 SW1_BM> This buffer shall be returned to the SW, 99 ring 1 100 <enum 7 SW2_BM> This buffer shall be returned to the SW, 101 ring 2 102 <enum 8 SW3_BM> This buffer shall be returned to the SW, 103 ring 3 104 <enum 9 SW4_BM> This buffer shall be returned to the SW, 105 ring 4 106 <enum 10 SW5_BM> This buffer shall be returned to the SW, 107 ring 5 108 <enum 11 SW6_BM> This buffer shall be returned to the SW, 109 ring 6 110 111 <legal 0-12> 112 */ 113 114 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 115 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 116 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 117 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 118 119 120 /* Description SW_BUFFER_COOKIE 121 122 Cookie field exclusively used by SW. 123 124 In case of 'NULL' pointer, this field is set to 0 125 126 HW ignores the contents, accept that it passes the programmed 127 value on to other descriptors together with the physical 128 address 129 130 Field can be used by SW to for example associate the buffers 131 physical address with the virtual address 132 The bit definitions as used by SW are within SW HLD specification 133 134 135 NOTE1: 136 The three most significant bits can have a special meaning 137 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 138 and field transmit_bw_restriction is set 139 140 In case of NON punctured transmission: 141 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 142 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 143 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 144 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 145 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 146 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 147 Sw_buffer_cookie[19:18] = 2'b11: reserved 148 149 In case of punctured transmission: 150 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 151 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 152 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 153 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 154 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 155 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 156 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 157 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 158 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 159 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 160 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 161 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 162 Sw_buffer_cookie[19:18] = 2'b11: reserved 163 164 Note: a punctured transmission is indicated by the presence 165 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 166 167 <legal all> 168 */ 169 170 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 171 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 172 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 173 #define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 174 175 176 177 #endif // RX_MPDU_LINK_PTR 178