1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_START_H_ 18 #define _RX_MPDU_START_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_info.h" 23 #define NUM_OF_DWORDS_RX_MPDU_START 30 24 25 #define NUM_OF_QWORDS_RX_MPDU_START 15 26 27 28 struct rx_mpdu_start { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct rx_mpdu_info rx_mpdu_info_details; 31 #else 32 struct rx_mpdu_info rx_mpdu_info_details; 33 #endif 34 }; 35 36 37 /* Description RX_MPDU_INFO_DETAILS 38 39 Structure containing all the MPDU header details that might 40 be needed for other modules further down the received path 41 42 */ 43 44 45 /* Description RXPT_CLASSIFY_INFO_DETAILS 46 47 In case of ndp or phy_err or AST_based_lookup_valid == 0, 48 this field will be set to 0 49 50 RXOLE related classification info 51 <legal all 52 */ 53 54 55 /* Description REO_DESTINATION_INDICATION 56 57 The ID of the REO exit ring where the MSDU frame shall push 58 after (MPDU level) reordering has finished. 59 60 <enum 0 reo_destination_sw0> Reo will push the frame into 61 the REO2SW0 ring 62 <enum 1 reo_destination_sw1> Reo will push the frame into 63 the REO2SW1 ring 64 <enum 2 reo_destination_sw2> Reo will push the frame into 65 the REO2SW2 ring 66 <enum 3 reo_destination_sw3> Reo will push the frame into 67 the REO2SW3 ring 68 <enum 4 reo_destination_sw4> Reo will push the frame into 69 the REO2SW4 ring 70 <enum 5 reo_destination_release> Reo will push the frame 71 into the REO_release ring 72 <enum 6 reo_destination_fw> Reo will push the frame into 73 the REO2FW ring 74 <enum 7 reo_destination_sw5> Reo will push the frame into 75 the REO2SW5 ring (REO remaps this in chips without REO2SW5 76 ring) 77 <enum 8 reo_destination_sw6> Reo will push the frame into 78 the REO2SW6 ring (REO remaps this in chips without REO2SW6 79 ring) 80 <enum 9 reo_destination_sw7> Reo will push the frame into 81 the REO2SW7 ring (REO remaps this in chips without REO2SW7 82 ring) 83 <enum 10 reo_destination_sw8> Reo will push the frame into 84 the REO2SW8 ring (REO remaps this in chips without REO2SW8 85 ring) 86 <enum 11 reo_destination_11> REO remaps this 87 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 88 REO remaps this 89 <enum 14 reo_destination_14> REO remaps this 90 <enum 15 reo_destination_15> REO remaps this 91 <enum 16 reo_destination_16> REO remaps this 92 <enum 17 reo_destination_17> REO remaps this 93 <enum 18 reo_destination_18> REO remaps this 94 <enum 19 reo_destination_19> REO remaps this 95 <enum 20 reo_destination_20> REO remaps this 96 <enum 21 reo_destination_21> REO remaps this 97 <enum 22 reo_destination_22> REO remaps this 98 <enum 23 reo_destination_23> REO remaps this 99 <enum 24 reo_destination_24> REO remaps this 100 <enum 25 reo_destination_25> REO remaps this 101 <enum 26 reo_destination_26> REO remaps this 102 <enum 27 reo_destination_27> REO remaps this 103 <enum 28 reo_destination_28> REO remaps this 104 <enum 29 reo_destination_29> REO remaps this 105 <enum 30 reo_destination_30> REO remaps this 106 <enum 31 reo_destination_31> REO remaps this 107 108 <legal all> 109 */ 110 111 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 112 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 113 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 114 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f 115 116 117 /* Description LMAC_PEER_ID_MSB 118 119 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb 120 is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, 121 hash[3:0]} using the chosen Toeplitz hash from Common Parser 122 if flow search fails. 123 If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb 124 's not 2'b00, Rx OLE uses a REO desination indication of 125 {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz 126 hash from Common Parser if flow search fails. 127 <legal all> 128 */ 129 130 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 131 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 132 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 133 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 134 135 136 /* Description USE_FLOW_ID_TOEPLITZ_CLFY 137 138 Indication to Rx OLE to enable REO destination routing based 139 on the chosen Toeplitz hash from Common Parser, in case 140 flow search fails 141 <legal all> 142 */ 143 144 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 145 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 146 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 147 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 148 149 150 /* Description PKT_SELECTION_FP_UCAST_DATA 151 152 Filter pass Unicast data frame (matching rxpcu_filter_pass 153 and sw_frame_group_Unicast_data) routing selection 154 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 155 156 1'b0: source and destination rings are selected from the 157 RxOLE register settings for the packet type 158 159 1'b1: source ring and destination ring is selected from 160 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 161 fields in this STRUCT 162 <legal all> 163 */ 164 165 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 166 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 167 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 168 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 169 170 171 /* Description PKT_SELECTION_FP_MCAST_DATA 172 173 Filter pass Multicast data frame (matching rxpcu_filter_pass 174 and sw_frame_group_Multicast_data) routing selection 175 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 176 177 1'b0: source and destination rings are selected from the 178 RxOLE register settings for the packet type 179 180 1'b1: source ring and destination ring is selected from 181 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 182 fields in this STRUCT 183 <legal all> 184 */ 185 186 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 187 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 188 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 189 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 190 191 192 /* Description PKT_SELECTION_FP_1000 193 194 Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) 195 routing selection 196 TODO: What about 'rxpcu_filter_pass_monior_ovrd'? 197 198 1'b0: source and destination rings are selected from the 199 RxOLE register settings for the packet type 200 201 1'b1: source ring and destination ring is selected from 202 the rxdma0_source_ring_selection and rxdma0_destination_ring_selection 203 fields in this STRUCT 204 <legal all> 205 */ 206 207 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 208 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 209 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 210 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 211 212 213 /* Description RXDMA0_SOURCE_RING_SELECTION 214 215 Field only valid when for the received frame type the corresponding 216 pkt_selection_fp_... bit is set 217 218 <enum 0 sw2rxdma0_0_buf_source_ring> The data buffer for 219 this frame shall be sourced by sw2rxdma0 buffer source 220 ring. 221 <enum 1 fw2rxdma0_pmac0_buf_source_ring> The data buffer 222 for this frame shall be sourced by fw2rxdma buffer source 223 ring for PMAC0. 224 <enum 2 sw2rxdma0_1_buf_source_ring> The data buffer for 225 this frame shall be sourced by sw2rxdma1 buffer source 226 ring. 227 <enum 3 no_buffer_rxdma0_ring> The frame shall not be written 228 to any data buffer. 229 <enum 4 sw2rxdma0_exception_buf_source_ring> The data buffer 230 for this frame shall be sourced by sw2rxdma_exception buffer 231 source ring. 232 <enum 5 fw2rxdma0_pmac1_buf_source_ring> The data buffer 233 for this frame shall be sourced by fw2rxdma buffer source 234 ring for PMAC1. 235 236 <legal 0-5> 237 */ 238 239 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 240 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 241 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 242 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 243 244 245 /* Description RXDMA0_DESTINATION_RING_SELECTION 246 247 Field only valid when for the received frame type the corresponding 248 pkt_selection_fp_... bit is set 249 250 <enum 0 rxdma_release_ring> RXDMA0 shall push the frame 251 to the Release ring. Effectively this means the frame needs 252 to be dropped. 253 <enum 1 rxdma2fw_pmac0_ring> RXDMA0 shall push the frame 254 to the FW ring for PMAC0. 255 <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to the 256 SW ring. 257 <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to 258 the REO entrance ring. 259 <enum 4 rxdma2fw_pmac1_ring> RXDMA0 shall push the frame 260 to the FW ring for PMAC1. 261 <enum 5 rxdma2reo_remote0_ring> RXDMA0 shall push the frame 262 to the first MLO REO entrance ring. 263 <enum 6 rxdma2reo_remote1_ring> RXDMA0 shall push the frame 264 to the second MLO REO entrance ring. 265 266 <legal 0-6> 267 */ 268 269 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 270 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 271 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 272 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 273 274 275 /* Description MCAST_ECHO_DROP_ENABLE 276 277 If set, for multicast packets, multicast echo check (i.e. 278 SA search with mcast_echo_check = 1) shall be performed 279 by RXOLE, and any multicast echo packets should be indicated 280 to RXDMA for release to WBM 281 282 <legal all> 283 */ 284 285 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 286 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 287 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 288 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 289 290 291 /* Description WDS_LEARNING_DETECT_EN 292 293 If set, WDS learning detection based on SA search and notification 294 to FW (using RXDMA0 status ring) is enabled and the "timestamp" 295 field in address search failure cache-only entry should 296 be used to avoid multiple WDS learning notifications. 297 298 <legal all> 299 */ 300 301 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 302 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 303 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 304 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 305 306 307 /* Description INTRABSS_CHECK_EN 308 309 If set, intra-BSS routing detection is enabled 310 311 <legal all> 312 */ 313 314 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 315 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 316 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 317 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 318 319 320 /* Description USE_PPE 321 322 Indicates to RXDMA to ignore the REO_destination_indication 323 and use a programmed value corresponding to the REO2PPE 324 ring 325 326 This override to REO2PPE for packets requiring multiple 327 buffers shall be disabled based on an RXDMA configuration, 328 as PPE may not support such packets. 329 330 <legal all> 331 */ 332 333 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 334 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 335 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 336 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 337 338 339 /* Description PPE_ROUTING_ENABLE 340 341 Global enable/disable bit for routing to PPE, used to disable 342 PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' 343 344 345 This is set by SW for peers which are being handled by a 346 host SW/accelerator subsystem that also handles packet 347 buffer management for WiFi-to-PPE routing. 348 349 This is cleared by SW for peers which are being handled 350 by a different subsystem, completely disabling WiFi-to-PPE 351 routing for such peers. 352 353 <legal all> 354 */ 355 356 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 357 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 358 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 359 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 360 361 362 /* Description RESERVED_0B 363 364 <legal 0> 365 */ 366 367 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 368 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 369 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 370 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000 371 372 373 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 374 375 In case of ndp or phy_err or AST_based_lookup_valid == 0, 376 this field will be set to 0 377 378 Address (lower 32 bits) of the REO queue descriptor. 379 380 If no Peer entry lookup happened for this frame, the value 381 wil be set to 0, and the frame shall never be pushed to 382 REO entrance ring. 383 <legal all> 384 */ 385 386 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 387 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 388 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 389 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 390 391 392 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 393 394 In case of ndp or phy_err or AST_based_lookup_valid == 0, 395 this field will be set to 0 396 397 Address (upper 8 bits) of the REO queue descriptor. 398 399 If no Peer entry lookup happened for this frame, the value 400 wil be set to 0, and the frame shall never be pushed to 401 REO entrance ring. 402 <legal all> 403 */ 404 405 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 406 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 407 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 408 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 409 410 411 /* Description RECEIVE_QUEUE_NUMBER 412 413 In case of ndp or phy_err or AST_based_lookup_valid == 0, 414 this field will be set to 0 415 416 Indicates the MPDU queue ID to which this MPDU link descriptor 417 belongs 418 Used for tracking and debugging 419 <legal all> 420 */ 421 422 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 423 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 424 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 425 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00 426 427 428 /* Description PRE_DELIM_ERR_WARNING 429 430 Indicates that a delimiter FCS error was found in between 431 the Previous MPDU and this MPDU. 432 433 Note that this is just a warning, and does not mean that 434 this MPDU is corrupted in any way. If it is, there will 435 be other errors indicated such as FCS or decrypt errors 436 437 438 In case of ndp or phy_err, this field will indicate at least 439 one of delimiters located after the last MPDU in the previous 440 PPDU has been corrupted. 441 */ 442 443 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 444 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 445 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 446 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000 447 448 449 /* Description FIRST_DELIM_ERR 450 451 Indicates that the first delimiter had a FCS failure. Only 452 valid when first_mpdu and first_msdu are set. 453 454 In case of ndp or phy_err, this field will never be set. 455 456 */ 457 458 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 459 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 460 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 461 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000 462 463 464 /* Description RESERVED_2A 465 466 <legal 0> 467 */ 468 469 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 470 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 471 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 472 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000 473 474 475 /* Description PN_31_0 476 477 Field only valid when Frame_encryption_info_valid is set 478 479 480 Bits [31:0] of the PN number extracted from the IV field 481 482 WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] 483 is valid. 484 TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], 485 pn1}. Only pn[47:0] is valid. 486 AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 487 pn0}. Only pn[47:0] is valid. 488 WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 489 pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 490 pn[127:0] are valid. 491 492 In case of ndp or phy_err, this field will never be set. 493 494 */ 495 496 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008 497 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32 498 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63 499 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000 500 501 502 /* Description PN_63_32 503 504 Field only valid when Frame_encryption_info_valid is set 505 506 507 Bits [63:32] of the PN number. See description for pn_31_0. 508 509 510 In case of ndp or phy_err, this field will never be set. 511 512 */ 513 514 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 515 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 516 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 517 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff 518 519 520 /* Description PN_95_64 521 522 Field only valid when Frame_encryption_info_valid is set 523 524 525 Bits [95:64] of the PN number. See description for pn_31_0. 526 527 528 In case of ndp or phy_err, this field will never be set. 529 530 */ 531 532 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010 533 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32 534 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63 535 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000 536 537 538 /* Description PN_127_96 539 540 Field only valid when Frame_encryption_info_valid is set 541 542 543 Bits [127:96] of the PN number. See description for pn_31_0. 544 545 546 In case of ndp or phy_err, this field will never be set. 547 548 */ 549 550 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 551 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 552 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 553 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff 554 555 556 /* Description EPD_EN 557 558 Field only valid when AST_based_lookup_valid == 1. 559 560 561 In case of ndp or phy_err or AST_based_lookup_valid == 0, 562 this field will be set to 0 563 564 If set to one use EPD instead of LPD 565 566 In case of ndp or phy_err, this field will never be set. 567 568 <legal all> 569 */ 570 571 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018 572 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 573 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 574 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 575 576 577 /* Description ALL_FRAMES_SHALL_BE_ENCRYPTED 578 579 In case of ndp or phy_err or AST_based_lookup_valid == 0, 580 this field will be set to 0 581 582 When set, all frames (data only ?) shall be encrypted. If 583 not, RX CRYPTO shall set an error flag. 584 <legal all> 585 */ 586 587 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018 588 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 589 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 590 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 591 592 593 /* Description ENCRYPT_TYPE 594 595 In case of ndp or phy_err or AST_based_lookup_valid == 0, 596 this field will be set to 0 597 598 Indicates type of decrypt cipher used (as defined in the 599 peer entry) 600 601 <enum 0 wep_40> WEP 40-bit 602 <enum 1 wep_104> WEP 104-bit 603 <enum 2 tkip_no_mic> TKIP without MIC 604 <enum 3 wep_128> WEP 128-bit 605 <enum 4 tkip_with_mic> TKIP with MIC 606 <enum 5 wapi> WAPI 607 <enum 6 aes_ccmp_128> AES CCMP 128 608 <enum 7 no_cipher> No crypto 609 <enum 8 aes_ccmp_256> AES CCMP 256 610 <enum 9 aes_gcmp_128> AES CCMP 128 611 <enum 10 aes_gcmp_256> AES CCMP 256 612 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 613 614 <enum 12 wep_varied_width> WEP encryption. As for WEP per 615 keyid the key bit width can vary, the key bit width for 616 this MPDU will be indicated in field wep_key_width_for_variable 617 key 618 <legal 0-12> 619 */ 620 621 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018 622 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 623 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 624 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 625 626 627 /* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY 628 629 Field only valid when key_type is set to wep_varied_width. 630 631 632 This field indicates the size of the wep key for this MPDU. 633 634 635 <enum 0 wep_varied_width_40> WEP 40-bit 636 <enum 1 wep_varied_width_104> WEP 104-bit 637 <enum 2 wep_varied_width_128> WEP 128-bit 638 639 <legal 0-2> 640 */ 641 642 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018 643 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 644 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 645 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 646 647 648 /* Description MESH_STA 649 650 In case of ndp or phy_err or AST_based_lookup_valid == 0, 651 this field will be set to 0 652 653 When set, this is a Mesh (11s) STA. 654 655 The interpretation of the A-MSDU 'Length' field in the MPDU 656 (if any) is decided by the e-numerations below. 657 658 <enum 0 MESH_DISABLE> 659 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes 660 the length of Mesh Control. 661 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes 662 the length of Mesh Control. 663 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and 664 excludes the length of Mesh Control. This is 802.11s-compliant. 665 666 <legal all> 667 */ 668 669 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000000000018 670 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 40 671 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MSB 41 672 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x0000030000000000 673 674 675 /* Description BSSID_HIT 676 677 In case of ndp or phy_err or AST_based_lookup_valid == 0, 678 this field will be set to 0 679 680 When set, the BSSID of the incoming frame matched one of 681 the 8 BSSID register values 682 683 <legal all> 684 */ 685 686 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018 687 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 688 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 689 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 690 691 692 /* Description BSSID_NUMBER 693 694 Field only valid when bssid_hit is set. 695 696 This number indicates which one out of the 8 BSSID register 697 values matched the incoming frame 698 <legal all> 699 */ 700 701 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018 702 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 703 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 704 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 705 706 707 /* Description TID 708 709 Field only valid when mpdu_qos_control_valid is set 710 711 The TID field in the QoS control field 712 <legal all> 713 */ 714 715 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018 716 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 717 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 718 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 719 720 721 /* Description RESERVED_7A 722 723 <legal 0> 724 */ 725 726 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018 727 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 728 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 729 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 730 731 732 /* Description PEER_META_DATA 733 734 In case of ndp or phy_err or AST_based_lookup_valid == 0, 735 this field will be set to 0 736 737 Meta data that SW has programmed in the Peer table entry 738 of the transmitting STA. 739 <legal all> 740 */ 741 742 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 743 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 744 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 745 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff 746 747 748 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 749 750 Field indicates what the reason was that this MPDU frame 751 was allowed to come into the receive path by RXPCU 752 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 753 filter programming of rxpcu 754 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 755 regular frame filter and would have been dropped, were 756 it not for the frame fitting into the 'monitor_client' category. 757 758 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 759 regular frame filter and also did not pass the rxpcu_monitor_client 760 filter. It would have been dropped accept that it did pass 761 the 'monitor_other' category. 762 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 763 the normal frame filter programming of RXPCU but additionally 764 fit into the 'monitor_override_client' category. 765 766 Note: for ndp frame, if it was expected because the preceding 767 NDPA was filter_pass, the setting rxpcu_filter_pass will 768 be used. This setting will also be used for every ndp frame 769 in case Promiscuous mode is enabled. 770 771 In case promiscuous is not enabled, and an NDP is not preceded 772 by a NPDA filter pass frame, the only other setting that 773 could appear here for the NDP is rxpcu_monitor_other. 774 (rxpcu has a configuration bit specifically for this scenario) 775 776 777 Note: for 778 <legal 0-3> 779 */ 780 781 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020 782 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 783 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 784 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 785 786 787 /* Description SW_FRAME_GROUP_ID 788 789 SW processes frames based on certain classifications. This 790 field indicates to what sw classification this MPDU is 791 mapped. 792 The classification is given in priority order 793 794 <enum 0 sw_frame_group_NDP_frame> Note: The corresponding 795 Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass 796 or rxpcu_monitor_other 797 798 <enum 1 sw_frame_group_Multicast_data> 799 <enum 2 sw_frame_group_Unicast_data> 800 <enum 3 sw_frame_group_Null_data > This includes mpdus of 801 type Data Null. 802 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 803 Null frames except in UL MU or TB PPDUs. 804 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 805 QoS Null frames in UL MU or TB PPDUs. 806 807 <enum 4 sw_frame_group_mgmt_0000 > 808 <enum 5 sw_frame_group_mgmt_0001 > 809 <enum 6 sw_frame_group_mgmt_0010 > 810 <enum 7 sw_frame_group_mgmt_0011 > 811 <enum 8 sw_frame_group_mgmt_0100 > 812 <enum 9 sw_frame_group_mgmt_0101 > 813 <enum 10 sw_frame_group_mgmt_0110 > 814 <enum 11 sw_frame_group_mgmt_0111 > 815 <enum 12 sw_frame_group_mgmt_1000 > 816 <enum 13 sw_frame_group_mgmt_1001 > 817 <enum 14 sw_frame_group_mgmt_1010 > 818 <enum 15 sw_frame_group_mgmt_1011 > 819 <enum 16 sw_frame_group_mgmt_1100 > 820 <enum 17 sw_frame_group_mgmt_1101 > 821 <enum 18 sw_frame_group_mgmt_1110 > 822 <enum 19 sw_frame_group_mgmt_1111 > 823 824 <enum 20 sw_frame_group_ctrl_0000 > 825 <enum 21 sw_frame_group_ctrl_0001 > 826 <enum 22 sw_frame_group_ctrl_0010 > 827 <enum 23 sw_frame_group_ctrl_0011 > 828 <enum 24 sw_frame_group_ctrl_0100 > 829 <enum 25 sw_frame_group_ctrl_0101 > 830 <enum 26 sw_frame_group_ctrl_0110 > 831 <enum 27 sw_frame_group_ctrl_0111 > 832 <enum 28 sw_frame_group_ctrl_1000 > 833 <enum 29 sw_frame_group_ctrl_1001 > 834 <enum 30 sw_frame_group_ctrl_1010 > 835 <enum 31 sw_frame_group_ctrl_1011 > 836 <enum 32 sw_frame_group_ctrl_1100 > 837 <enum 33 sw_frame_group_ctrl_1101 > 838 <enum 34 sw_frame_group_ctrl_1110 > 839 <enum 35 sw_frame_group_ctrl_1111 > 840 841 <enum 36 sw_frame_group_unsupported> This covers type 3 842 and protocol version != 0 843 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 844 only be rxpcu_monitor_other 845 846 <enum 37 sw_frame_group_phy_error> PHY reported an error 847 848 Note: The corresponding Rxpcu_Mpdu_filter_in_category can 849 be rxpcu_filter_pass 850 851 <legal 0-39> 852 */ 853 854 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020 855 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 856 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 857 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 858 859 860 /* Description NDP_FRAME 861 862 When set, the received frame was an NDP frame, and thus 863 there will be no MPDU data. 864 TODO: Should this be extended to 2-bit e-num? 865 <legal all> 866 */ 867 868 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020 869 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 870 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 871 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 872 873 874 /* Description PHY_ERR 875 876 When set, a PHY error was received before MAC received any 877 data, and thus there will be no MPDU data. 878 <legal all> 879 */ 880 881 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020 882 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 883 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 884 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 885 886 887 /* Description PHY_ERR_DURING_MPDU_HEADER 888 889 When set, a PHY error was received before MAC received the 890 complete MPDU header which was needed for proper decoding 891 892 <legal all> 893 */ 894 895 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020 896 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 897 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 898 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 899 900 901 /* Description PROTOCOL_VERSION_ERR 902 903 Set when RXPCU detected a version error in the Frame control 904 field 905 <legal all> 906 */ 907 908 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020 909 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 910 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 911 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 912 913 914 /* Description AST_BASED_LOOKUP_VALID 915 916 When set, AST based lookup for this frame has found a valid 917 result. 918 919 Note that for NDP frame this will never be set 920 <legal all> 921 */ 922 923 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020 924 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 925 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 926 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 927 928 929 /* Description RANGING 930 931 When set, a ranging NDPA or a ranging NDP was received. 932 933 This field is only for FW visibility. HW is not expected 934 to take any action on this. 935 <legal all> 936 */ 937 938 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_OFFSET 0x0000000000000020 939 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_LSB 46 940 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MSB 46 941 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MASK 0x0000400000000000 942 943 944 /* Description RESERVED_9A 945 946 <legal 0> 947 */ 948 949 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020 950 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47 951 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47 952 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000 953 954 955 /* Description PHY_PPDU_ID 956 957 A ppdu counter value that PHY increments for every PPDU 958 received. The counter value wraps around 959 <legal all> 960 */ 961 962 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020 963 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 964 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 965 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 966 967 968 /* Description AST_INDEX 969 970 This field indicates the index of the AST entry corresponding 971 to this MPDU. It is provided by the GSE module instantiated 972 in RXPCU. 973 A value of 0xFFFF indicates an invalid AST index, meaning 974 that No AST entry was found or NO AST search was performed 975 976 977 In case of ndp or phy_err, this field will be set to 0xFFFF 978 979 <legal all> 980 */ 981 982 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 983 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 984 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 985 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff 986 987 988 /* Description SW_PEER_ID 989 990 In case of ndp or phy_err or AST_based_lookup_valid == 0, 991 this field will be set to 0 992 993 This field indicates a unique peer identifier. It is set 994 equal to field 'sw_peer_id' from the AST entry 995 996 <legal all> 997 */ 998 999 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 1000 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 1001 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 1002 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 1003 1004 1005 /* Description MPDU_FRAME_CONTROL_VALID 1006 1007 When set, the field Mpdu_Frame_control_field has valid information 1008 1009 1010 In case of ndp or phy_err, this field will never be set. 1011 1012 <legal all> 1013 */ 1014 1015 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028 1016 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32 1017 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32 1018 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000 1019 1020 1021 /* Description MPDU_DURATION_VALID 1022 1023 When set, the field Mpdu_duration_field has valid information 1024 1025 1026 In case of ndp or phy_err, this field will never be set. 1027 1028 <legal all> 1029 */ 1030 1031 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028 1032 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33 1033 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33 1034 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000 1035 1036 1037 /* Description MAC_ADDR_AD1_VALID 1038 1039 When set, the fields mac_addr_ad1_..... have valid information 1040 1041 1042 In case of ndp or phy_err, this field will never be set. 1043 1044 <legal all> 1045 */ 1046 1047 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028 1048 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34 1049 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34 1050 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000 1051 1052 1053 /* Description MAC_ADDR_AD2_VALID 1054 1055 When set, the fields mac_addr_ad2_..... have valid information 1056 1057 1058 For MPDUs without Address 2, this field will not be set. 1059 1060 1061 In case of ndp or phy_err, this field will never be set. 1062 1063 <legal all> 1064 */ 1065 1066 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028 1067 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35 1068 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35 1069 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000 1070 1071 1072 /* Description MAC_ADDR_AD3_VALID 1073 1074 When set, the fields mac_addr_ad3_..... have valid information 1075 1076 1077 For MPDUs without Address 3, this field will not be set. 1078 1079 1080 In case of ndp or phy_err, this field will never be set. 1081 1082 <legal all> 1083 */ 1084 1085 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028 1086 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36 1087 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36 1088 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000 1089 1090 1091 /* Description MAC_ADDR_AD4_VALID 1092 1093 When set, the fields mac_addr_ad4_..... have valid information 1094 1095 1096 For MPDUs without Address 4, this field will not be set. 1097 1098 1099 In case of ndp or phy_err, this field will never be set. 1100 1101 <legal all> 1102 */ 1103 1104 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028 1105 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37 1106 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37 1107 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000 1108 1109 1110 /* Description MPDU_SEQUENCE_CONTROL_VALID 1111 1112 When set, the fields mpdu_sequence_control_field and mpdu_sequence_number 1113 have valid information as well as field 1114 1115 For MPDUs without a sequence control field, this field will 1116 not be set. 1117 1118 In case of ndp or phy_err, this field will never be set. 1119 1120 <legal all> 1121 */ 1122 1123 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028 1124 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38 1125 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38 1126 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000 1127 1128 1129 /* Description MPDU_QOS_CONTROL_VALID 1130 1131 When set, the field mpdu_qos_control_field has valid information 1132 1133 1134 For MPDUs without a QoS control field, this field will not 1135 be set. 1136 1137 In case of ndp or phy_err, this field will never be set. 1138 1139 <legal all> 1140 */ 1141 1142 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 1143 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39 1144 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39 1145 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000 1146 1147 1148 /* Description MPDU_HT_CONTROL_VALID 1149 1150 When set, the field mpdu_HT_control_field has valid information 1151 1152 1153 For MPDUs without a HT control field, this field will not 1154 be set. 1155 1156 In case of ndp or phy_err, this field will never be set. 1157 1158 <legal all> 1159 */ 1160 1161 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028 1162 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40 1163 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40 1164 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000 1165 1166 1167 /* Description FRAME_ENCRYPTION_INFO_VALID 1168 1169 When set, the encryption related info fields, like IV and 1170 PN are valid 1171 1172 For MPDUs that are not encrypted, this will not be set. 1173 1174 In case of ndp or phy_err, this field will never be set. 1175 1176 <legal all> 1177 */ 1178 1179 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028 1180 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41 1181 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41 1182 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000 1183 1184 1185 /* Description MPDU_FRAGMENT_NUMBER 1186 1187 Field only valid when Mpdu_sequence_control_valid is set 1188 AND Fragment_flag is set 1189 1190 The fragment number from the 802.11 header 1191 1192 <legal all> 1193 */ 1194 1195 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028 1196 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42 1197 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45 1198 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000 1199 1200 1201 /* Description MORE_FRAGMENT_FLAG 1202 1203 The More Fragment bit setting from the MPDU header of the 1204 received frame 1205 1206 <legal all> 1207 */ 1208 1209 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028 1210 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46 1211 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46 1212 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000 1213 1214 1215 /* Description RESERVED_11A 1216 1217 <legal 0> 1218 */ 1219 1220 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028 1221 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47 1222 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47 1223 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000 1224 1225 1226 /* Description FR_DS 1227 1228 Field only valid when Mpdu_frame_control_valid is set 1229 1230 Set if the from DS bit is set in the frame control. 1231 <legal all> 1232 */ 1233 1234 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028 1235 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48 1236 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48 1237 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000 1238 1239 1240 /* Description TO_DS 1241 1242 Field only valid when Mpdu_frame_control_valid is set 1243 1244 Set if the to DS bit is set in the frame control. 1245 <legal all> 1246 */ 1247 1248 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028 1249 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49 1250 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49 1251 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000 1252 1253 1254 /* Description ENCRYPTED 1255 1256 Field only valid when Mpdu_frame_control_valid is set. 1257 1258 Protected bit from the frame control. 1259 <legal all> 1260 */ 1261 1262 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028 1263 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50 1264 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50 1265 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000 1266 1267 1268 /* Description MPDU_RETRY 1269 1270 Field only valid when Mpdu_frame_control_valid is set. 1271 1272 Retry bit from the frame control. Only valid when first_msdu 1273 is set. 1274 <legal all> 1275 */ 1276 1277 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028 1278 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51 1279 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51 1280 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000 1281 1282 1283 /* Description MPDU_SEQUENCE_NUMBER 1284 1285 Field only valid when Mpdu_sequence_control_valid is set. 1286 1287 1288 The sequence number from the 802.11 header. 1289 <legal all> 1290 */ 1291 1292 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028 1293 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52 1294 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63 1295 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000 1296 1297 1298 /* Description KEY_ID_OCTET 1299 1300 Field only valid when Frame_encryption_info_valid is set 1301 1302 1303 The key ID octet from the IV. 1304 1305 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1306 this field will be set to 0 1307 <legal all> 1308 */ 1309 1310 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 1311 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 1312 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 1313 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff 1314 1315 1316 /* Description NEW_PEER_ENTRY 1317 1318 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1319 this field will be set to 0 1320 1321 Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY 1322 doesn't follow so RX DECRYPTION module either uses old 1323 peer entry or not decrypt. 1324 <legal all> 1325 */ 1326 1327 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 1328 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 1329 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 1330 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 1331 1332 1333 /* Description DECRYPT_NEEDED 1334 1335 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1336 this field will be set to 0 1337 1338 Set if decryption is needed. 1339 1340 Note: 1341 When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', 1342 RXPCU will also ensure that this bit is NOT set 1343 CRYPTO for that reason only needs to evaluate this bit and 1344 non of the other ones. 1345 <legal all> 1346 */ 1347 1348 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 1349 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 1350 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 1351 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 1352 1353 1354 /* Description DECAP_TYPE 1355 1356 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1357 this field will be set to 0 1358 1359 Used by the OLE during decapsulation. 1360 1361 Indicates the decapsulation that HW will perform: 1362 1363 <enum 0 RAW> No encapsulation 1364 <enum 1 Native_WiFi> 1365 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1366 1367 <enum 3 802_3> Indicate Ethernet 1368 1369 <legal all> 1370 */ 1371 1372 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 1373 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 1374 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 1375 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 1376 1377 1378 /* Description RX_INSERT_VLAN_C_TAG_PADDING 1379 1380 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1381 this field will be set to 0 1382 1383 Insert 4 byte of all zeros as VLAN tag if the rx payload 1384 does not have VLAN. Used during decapsulation. 1385 <legal all> 1386 */ 1387 1388 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 1389 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 1390 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 1391 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 1392 1393 1394 /* Description RX_INSERT_VLAN_S_TAG_PADDING 1395 1396 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1397 this field will be set to 0 1398 1399 Insert 4 byte of all zeros as double VLAN tag if the rx 1400 payload does not have VLAN. Used during 1401 <legal all> 1402 */ 1403 1404 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 1405 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 1406 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 1407 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 1408 1409 1410 /* Description STRIP_VLAN_C_TAG_DECAP 1411 1412 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1413 this field will be set to 0 1414 1415 Strip the VLAN during decapsulation. Used by the OLE. 1416 <legal all> 1417 */ 1418 1419 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 1420 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 1421 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 1422 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 1423 1424 1425 /* Description STRIP_VLAN_S_TAG_DECAP 1426 1427 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1428 this field will be set to 0 1429 1430 Strip the double VLAN during decapsulation. Used by the 1431 OLE. 1432 <legal all> 1433 */ 1434 1435 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 1436 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 1437 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 1438 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 1439 1440 1441 /* Description PRE_DELIM_COUNT 1442 1443 The number of delimiters before this MPDU. 1444 1445 Note that this number is cleared at PPDU start. 1446 1447 If this MPDU is the first received MPDU in the PPDU and 1448 this MPDU gets filtered-in, this field will indicate the 1449 number of delimiters located after the last MPDU in the 1450 previous PPDU. 1451 1452 If this MPDU is located after the first received MPDU in 1453 an PPDU, this field will indicate the number of delimiters 1454 located between the previous MPDU and this MPDU. 1455 1456 In case of ndp or phy_err, this field will indicate the 1457 number of delimiters located after the last MPDU in the 1458 previous PPDU. 1459 <legal all> 1460 */ 1461 1462 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 1463 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 1464 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 1465 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 1466 1467 1468 /* Description AMPDU_FLAG 1469 1470 When set, received frame was part of an A-MPDU. 1471 1472 In case of ndp or phy_err, this field will never be set. 1473 1474 <legal all> 1475 */ 1476 1477 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 1478 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 1479 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 1480 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 1481 1482 1483 /* Description BAR_FRAME 1484 1485 In case of ndp or phy_err or AST_based_lookup_valid == 0, 1486 this field will be set to 0 1487 1488 When set, received frame is a BAR frame 1489 <legal all> 1490 */ 1491 1492 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 1493 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 1494 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 1495 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 1496 1497 1498 /* Description RAW_MPDU 1499 1500 Consumer: SW 1501 Producer: RXOLE 1502 1503 RXPCU sets this field to 0 and RXOLE overwrites it. 1504 1505 Set to 1 by RXOLE when it has not performed any 802.11 to 1506 Ethernet/Natvie WiFi header conversion on this MPDU. 1507 <legal all> 1508 */ 1509 1510 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 1511 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 1512 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 1513 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 1514 1515 1516 /* Description RESERVED_12 1517 1518 <legal 0> 1519 */ 1520 1521 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 1522 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 1523 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 1524 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 1525 1526 1527 /* Description MPDU_LENGTH 1528 1529 In case of ndp or phy_err this field will be set to 0 1530 1531 MPDU length before decapsulation. 1532 <legal all> 1533 */ 1534 1535 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 1536 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 1537 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 1538 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 1539 1540 1541 /* Description FIRST_MPDU 1542 1543 See definition in RX attention descriptor 1544 1545 In case of ndp or phy_err, this field will be set. Note 1546 however that there will not actually be any data contents 1547 in the MPDU. 1548 <legal all> 1549 */ 1550 1551 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 1552 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 1553 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 1554 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 1555 1556 1557 /* Description MCAST_BCAST 1558 1559 In case of ndp or phy_err or Phy_err_during_mpdu_header 1560 this field will be set to 0 1561 1562 See definition in RX attention descriptor 1563 <legal all> 1564 */ 1565 1566 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 1567 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 1568 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 1569 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 1570 1571 1572 /* Description AST_INDEX_NOT_FOUND 1573 1574 In case of ndp or phy_err or Phy_err_during_mpdu_header 1575 this field will be set to 0 1576 1577 See definition in RX attention descriptor 1578 <legal all> 1579 */ 1580 1581 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 1582 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 1583 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 1584 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 1585 1586 1587 /* Description AST_INDEX_TIMEOUT 1588 1589 In case of ndp or phy_err or Phy_err_during_mpdu_header 1590 this field will be set to 0 1591 1592 See definition in RX attention descriptor 1593 <legal all> 1594 */ 1595 1596 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 1597 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 1598 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 1599 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 1600 1601 1602 /* Description POWER_MGMT 1603 1604 In case of ndp or phy_err or Phy_err_during_mpdu_header 1605 this field will be set to 0 1606 1607 See definition in RX attention descriptor 1608 <legal all> 1609 */ 1610 1611 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 1612 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 1613 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 1614 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 1615 1616 1617 /* Description NON_QOS 1618 1619 In case of ndp or phy_err or Phy_err_during_mpdu_header 1620 this field will be set to 1 1621 1622 See definition in RX attention descriptor 1623 <legal all> 1624 */ 1625 1626 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 1627 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 1628 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 1629 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 1630 1631 1632 /* Description NULL_DATA 1633 1634 In case of ndp or phy_err or Phy_err_during_mpdu_header 1635 this field will be set to 0 1636 1637 See definition in RX attention descriptor 1638 <legal all> 1639 */ 1640 1641 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 1642 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 1643 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 1644 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 1645 1646 1647 /* Description MGMT_TYPE 1648 1649 In case of ndp or phy_err or Phy_err_during_mpdu_header 1650 this field will be set to 0 1651 1652 See definition in RX attention descriptor 1653 <legal all> 1654 */ 1655 1656 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 1657 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 1658 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 1659 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 1660 1661 1662 /* Description CTRL_TYPE 1663 1664 In case of ndp or phy_err or Phy_err_during_mpdu_header 1665 this field will be set to 0 1666 1667 See definition in RX attention descriptor 1668 <legal all> 1669 */ 1670 1671 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 1672 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 1673 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 1674 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 1675 1676 1677 /* Description MORE_DATA 1678 1679 In case of ndp or phy_err or Phy_err_during_mpdu_header 1680 this field will be set to 0 1681 1682 See definition in RX attention descriptor 1683 <legal all> 1684 */ 1685 1686 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 1687 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 1688 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 1689 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 1690 1691 1692 /* Description EOSP 1693 1694 In case of ndp or phy_err or Phy_err_during_mpdu_header 1695 this field will be set to 0 1696 1697 See definition in RX attention descriptor 1698 <legal all> 1699 */ 1700 1701 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 1702 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 1703 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 1704 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 1705 1706 1707 /* Description FRAGMENT_FLAG 1708 1709 In case of ndp or phy_err or Phy_err_during_mpdu_header 1710 this field will be set to 0 1711 1712 See definition in RX attention descriptor 1713 <legal all> 1714 */ 1715 1716 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 1717 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 1718 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 1719 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 1720 1721 1722 /* Description ORDER 1723 1724 In case of ndp or phy_err or Phy_err_during_mpdu_header 1725 this field will be set to 0 1726 1727 See definition in RX attention descriptor 1728 1729 <legal all> 1730 */ 1731 1732 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 1733 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 1734 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 1735 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 1736 1737 1738 /* Description U_APSD_TRIGGER 1739 1740 In case of ndp or phy_err or Phy_err_during_mpdu_header 1741 this field will be set to 0 1742 1743 See definition in RX attention descriptor 1744 <legal all> 1745 */ 1746 1747 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 1748 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 1749 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 1750 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 1751 1752 1753 /* Description ENCRYPT_REQUIRED 1754 1755 In case of ndp or phy_err or Phy_err_during_mpdu_header 1756 this field will be set to 0 1757 1758 See definition in RX attention descriptor 1759 <legal all> 1760 */ 1761 1762 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 1763 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 1764 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 1765 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 1766 1767 1768 /* Description DIRECTED 1769 1770 In case of ndp or phy_err or Phy_err_during_mpdu_header 1771 this field will be set to 0 1772 1773 See definition in RX attention descriptor 1774 <legal all> 1775 */ 1776 1777 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 1778 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 1779 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 1780 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 1781 1782 1783 /* Description AMSDU_PRESENT 1784 1785 Field only valid when Mpdu_qos_control_valid is set 1786 1787 The 'amsdu_present' bit within the QoS control field of 1788 the MPDU 1789 <legal all> 1790 */ 1791 1792 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 1793 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 1794 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 1795 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 1796 1797 1798 /* Description RESERVED_13 1799 1800 Field only valid when Mpdu_qos_control_valid is set 1801 1802 This indicates whether the 'Ack policy' field within the 1803 QoS control field of the MPDU indicates 'no-Ack.' 1804 <legal all> 1805 */ 1806 1807 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 1808 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 1809 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 1810 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 1811 1812 1813 /* Description MPDU_FRAME_CONTROL_FIELD 1814 1815 Field only valid when Mpdu_frame_control_valid is set 1816 1817 The frame control field of this received MPDU. 1818 1819 Field only valid when Ndp_frame and phy_err are NOT set 1820 1821 Bytes 0 + 1 of the received MPDU 1822 <legal all> 1823 */ 1824 1825 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 1826 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 1827 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 1828 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff 1829 1830 1831 /* Description MPDU_DURATION_FIELD 1832 1833 Field only valid when Mpdu_duration_valid is set 1834 1835 The duration field of this received MPDU. 1836 <legal all> 1837 */ 1838 1839 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 1840 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 1841 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 1842 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 1843 1844 1845 /* Description MAC_ADDR_AD1_31_0 1846 1847 Field only valid when mac_addr_ad1_valid is set 1848 1849 The Least Significant 4 bytes of the Received Frames MAC 1850 Address AD1 1851 <legal all> 1852 */ 1853 1854 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 1855 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 1856 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 1857 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 1858 1859 1860 /* Description MAC_ADDR_AD1_47_32 1861 1862 Field only valid when mac_addr_ad1_valid is set 1863 1864 The 2 most significant bytes of the Received Frames MAC 1865 Address AD1 1866 <legal all> 1867 */ 1868 1869 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 1870 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 1871 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 1872 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff 1873 1874 1875 /* Description MAC_ADDR_AD2_15_0 1876 1877 Field only valid when mac_addr_ad2_valid is set 1878 1879 The Least Significant 2 bytes of the Received Frames MAC 1880 Address AD2 1881 <legal all> 1882 */ 1883 1884 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 1885 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 1886 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 1887 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 1888 1889 1890 /* Description MAC_ADDR_AD2_47_16 1891 1892 Field only valid when mac_addr_ad2_valid is set 1893 1894 The 4 most significant bytes of the Received Frames MAC 1895 Address AD2 1896 <legal all> 1897 */ 1898 1899 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 1900 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 1901 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 1902 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 1903 1904 1905 /* Description MAC_ADDR_AD3_31_0 1906 1907 Field only valid when mac_addr_ad3_valid is set 1908 1909 The Least Significant 4 bytes of the Received Frames MAC 1910 Address AD3 1911 <legal all> 1912 */ 1913 1914 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 1915 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 1916 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 1917 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff 1918 1919 1920 /* Description MAC_ADDR_AD3_47_32 1921 1922 Field only valid when mac_addr_ad3_valid is set 1923 1924 The 2 most significant bytes of the Received Frames MAC 1925 Address AD3 1926 <legal all> 1927 */ 1928 1929 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 1930 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 1931 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 1932 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 1933 1934 1935 /* Description MPDU_SEQUENCE_CONTROL_FIELD 1936 1937 Field only valid when mpdu_sequence_control_valid is set 1938 1939 1940 The sequence control field of the MPDU 1941 <legal all> 1942 */ 1943 1944 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 1945 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 1946 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 1947 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 1948 1949 1950 /* Description MAC_ADDR_AD4_31_0 1951 1952 Field only valid when mac_addr_ad4_valid is set 1953 1954 The Least Significant 4 bytes of the Received Frames MAC 1955 Address AD4 1956 <legal all> 1957 */ 1958 1959 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 1960 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 1961 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 1962 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff 1963 1964 1965 /* Description MAC_ADDR_AD4_47_32 1966 1967 Field only valid when mac_addr_ad4_valid is set 1968 1969 The 2 most significant bytes of the Received Frames MAC 1970 Address AD4 1971 <legal all> 1972 */ 1973 1974 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 1975 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 1976 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 1977 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 1978 1979 1980 /* Description MPDU_QOS_CONTROL_FIELD 1981 1982 Field only valid when mpdu_qos_control_valid is set 1983 1984 The sequence control field of the MPDU 1985 <legal all> 1986 */ 1987 1988 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 1989 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 1990 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 1991 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 1992 1993 1994 /* Description MPDU_HT_CONTROL_FIELD 1995 1996 Field only valid when mpdu_qos_control_valid is set 1997 1998 The HT control field of the MPDU 1999 <legal all> 2000 */ 2001 2002 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 2003 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 2004 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 2005 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 2006 2007 2008 /* Description VDEV_ID 2009 2010 Consumer: RXOLE 2011 Producer: FW 2012 2013 Virtual device associated with this peer 2014 2015 RXOLE uses this to determine intra-BSS routing. 2016 2017 <legal all> 2018 */ 2019 2020 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 2021 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 2022 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 2023 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 2024 2025 2026 /* Description SERVICE_CODE 2027 2028 Opaque service code between PPE and Wi-Fi 2029 2030 This field gets passed on by REO to PPE in the EDMA descriptor 2031 ('REO_TO_PPE_RING'). 2032 2033 <legal all> 2034 */ 2035 2036 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 2037 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 2038 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 2039 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 2040 2041 2042 /* Description PRIORITY_VALID 2043 2044 This field gets passed on by REO to PPE in the EDMA descriptor 2045 ('REO_TO_PPE_RING'). 2046 2047 <legal all> 2048 */ 2049 2050 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 2051 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 2052 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 2053 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 2054 2055 2056 /* Description SRC_INFO 2057 2058 Source (virtual) device/interface info. associated with 2059 this peer 2060 2061 This field gets passed on by REO to PPE in the EDMA descriptor 2062 ('REO_TO_PPE_RING'). 2063 2064 <legal all> 2065 */ 2066 2067 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 2068 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 2069 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 2070 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 2071 2072 2073 /* Description RESERVED_23A 2074 2075 <legal 0> 2076 */ 2077 2078 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 2079 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 2080 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 2081 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 2082 2083 2084 /* Description MULTI_LINK_ADDR_AD1_AD2_VALID 2085 2086 If set, Rx OLE shall convert Address1 and Address2 of received 2087 data frames to multi-link addresses during decapsulation 2088 to Ethernet or Native WiFi 2089 <legal all> 2090 */ 2091 2092 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000000000000058 2093 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 63 2094 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 63 2095 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x8000000000000000 2096 2097 2098 /* Description MULTI_LINK_ADDR_AD1_31_0 2099 2100 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2101 2102 2103 Multi-link receiver address (address1), bits [31:0] 2104 */ 2105 2106 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000060 2107 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_LSB 0 2108 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MSB 31 2109 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff 2110 2111 2112 /* Description MULTI_LINK_ADDR_AD1_47_32 2113 2114 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2115 2116 2117 Multi-link receiver address (address1), bits [47:32] 2118 */ 2119 2120 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000060 2121 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_LSB 32 2122 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MSB 47 2123 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 2124 2125 2126 /* Description MULTI_LINK_ADDR_AD2_15_0 2127 2128 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2129 2130 2131 Multi-link transmitter address (address2), bits [15:0] 2132 */ 2133 2134 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000060 2135 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_LSB 48 2136 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MSB 63 2137 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 2138 2139 2140 /* Description MULTI_LINK_ADDR_AD2_47_16 2141 2142 Field only valid if Multi_link_addr_ad1_ad2_valid is set 2143 2144 2145 Multi-link transmitter address (address2), bits [47:16] 2146 */ 2147 2148 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000068 2149 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_LSB 0 2150 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MSB 31 2151 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff 2152 2153 2154 /* Description AUTHORIZED_TO_SEND_WDS 2155 2156 If not set, RXDMA shall perform error-routing for WDS packets 2157 as the sender is not authorized and might misuse WDS frame 2158 format to inject packets with arbitrary DA/SA. 2159 <legal all> 2160 */ 2161 2162 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 2163 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 2164 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 2165 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 2166 2167 2168 /* Description RESERVED_27A 2169 2170 Bit 1: disallow_mcbc_da_in_unicast_mpdu: 2171 2172 If set, RX OLE shall disallow multicast/broadcast DA in 2173 A-MSDU subframes in case of ToDS=0 MPDUs. This may be enabled 2174 for TDLS peers. 2175 <legal 0-1> 2176 */ 2177 2178 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 2179 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33 2180 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 2181 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000 2182 2183 2184 /* Description RESERVED_28A 2185 2186 <legal 0> 2187 */ 2188 2189 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070 2190 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 2191 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 2192 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff 2193 2194 2195 /* Description RESERVED_29A 2196 2197 <legal 0> 2198 */ 2199 2200 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 2201 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32 2202 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 2203 #define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000 2204 2205 2206 2207 #endif // RX_MPDU_START 2208