1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_DESC_INFO_H_ 18 #define _RX_MSDU_DESC_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 23 24 25 struct rx_msdu_desc_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t first_msdu_in_mpdu_flag : 1, // [0:0] 28 last_msdu_in_mpdu_flag : 1, // [1:1] 29 msdu_continuation : 1, // [2:2] 30 msdu_length : 14, // [16:3] 31 msdu_drop : 1, // [17:17] 32 sa_is_valid : 1, // [18:18] 33 da_is_valid : 1, // [19:19] 34 da_is_mcbc : 1, // [20:20] 35 l3_header_padding_msb : 1, // [21:21] 36 tcp_udp_chksum_fail : 1, // [22:22] 37 ip_chksum_fail : 1, // [23:23] 38 fr_ds : 1, // [24:24] 39 to_ds : 1, // [25:25] 40 intra_bss : 1, // [26:26] 41 dest_chip_id : 2, // [28:27] 42 decap_format : 2, // [30:29] 43 dest_chip_pmac_id : 1; // [31:31] 44 #else 45 uint32_t dest_chip_pmac_id : 1, // [31:31] 46 decap_format : 2, // [30:29] 47 dest_chip_id : 2, // [28:27] 48 intra_bss : 1, // [26:26] 49 to_ds : 1, // [25:25] 50 fr_ds : 1, // [24:24] 51 ip_chksum_fail : 1, // [23:23] 52 tcp_udp_chksum_fail : 1, // [22:22] 53 l3_header_padding_msb : 1, // [21:21] 54 da_is_mcbc : 1, // [20:20] 55 da_is_valid : 1, // [19:19] 56 sa_is_valid : 1, // [18:18] 57 msdu_drop : 1, // [17:17] 58 msdu_length : 14, // [16:3] 59 msdu_continuation : 1, // [2:2] 60 last_msdu_in_mpdu_flag : 1, // [1:1] 61 first_msdu_in_mpdu_flag : 1; // [0:0] 62 #endif 63 }; 64 65 66 /* Description FIRST_MSDU_IN_MPDU_FLAG 67 68 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 69 multiple buffers, this field will be valid in the Last 70 buffer used by the MSDU 71 72 <enum 0 Not_first_msdu> This is not the first MSDU in the 73 MPDU. 74 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 75 76 77 <legal all> 78 */ 79 80 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 81 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 82 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 83 #define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 84 85 86 /* Description LAST_MSDU_IN_MPDU_FLAG 87 88 Consumer: WBM/REO/SW/FW 89 Producer: RXDMA 90 91 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 92 multiple buffers, this field will be valid in the Last 93 buffer used by the MSDU 94 95 <enum 0 Not_last_msdu> There are more MSDUs linked to this 96 MSDU that belongs to this MPDU 97 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 98 This setting is only allowed in combination with 'Msdu_continuation' 99 set to 0. This implies that when an msdu is spread out over 100 multiple buffers and thus msdu_continuation is set, only 101 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 102 be set. 103 104 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 105 are set, the MPDU that this MSDU belongs to only contains 106 a single MSDU. 107 108 109 <legal all> 110 */ 111 112 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 113 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 114 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 115 #define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 116 117 118 /* Description MSDU_CONTINUATION 119 120 When set, this MSDU buffer was not able to hold the entire 121 MSDU. The next buffer will therefor contain additional 122 information related to this MSDU. 123 124 <legal all> 125 */ 126 127 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 128 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 129 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 130 #define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 131 132 133 /* Description MSDU_LENGTH 134 135 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 136 multiple buffers, this field will be valid in the First 137 buffer used by MSDU. 138 139 Full MSDU length in bytes after decapsulation. 140 141 This field is still valid for MPDU frames without A-MSDU. 142 It still represents MSDU length after decapsulation 143 144 Or in case of RAW MPDUs, it indicates the length of the 145 entire MPDU (without FCS field) 146 <legal all> 147 */ 148 149 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 150 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 151 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 152 #define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 153 154 155 /* Description MSDU_DROP 156 157 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 158 multiple buffers, this field will be valid in the Last 159 buffer used by the MSDU 160 161 When set, REO shall drop this MSDU and not forward it to 162 any other ring... 163 <legal all> 164 */ 165 166 #define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 167 #define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 168 #define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 169 #define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 170 171 172 /* Description SA_IS_VALID 173 174 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 175 multiple buffers, this field will be valid in the Last 176 buffer used by the MSDU 177 178 Indicates that OLE found a valid SA entry for this MSDU 179 <legal all> 180 */ 181 182 #define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 183 #define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 184 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 185 #define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 186 187 188 /* Description DA_IS_VALID 189 190 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 191 multiple buffers, this field will be valid in the Last 192 buffer used by the MSDU 193 194 Indicates that OLE found a valid DA entry for this MSDU 195 <legal all> 196 */ 197 198 #define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 199 #define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 200 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 201 #define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 202 203 204 /* Description DA_IS_MCBC 205 206 Field Only valid if "da_is_valid" is set 207 208 Indicates the DA address was a Multicast of Broadcast address 209 for this MSDU 210 <legal all> 211 */ 212 213 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 214 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 215 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 216 #define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 217 218 219 /* Description L3_HEADER_PADDING_MSB 220 221 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 222 as the LSB is always zero) 223 Number of bytes padded to make sure that the L3 header will 224 always start of a Dword boundary 225 <legal all> 226 */ 227 228 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 229 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 230 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 231 #define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 232 233 234 /* Description TCP_UDP_CHKSUM_FAIL 235 236 Passed on from 'RX_ATTENTION' TLV 237 Indicates that the computed checksum did not match the checksum 238 in the TCP/UDP header. 239 <legal all> 240 */ 241 242 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 243 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 244 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 245 #define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 246 247 248 /* Description IP_CHKSUM_FAIL 249 250 Passed on from 'RX_ATTENTION' TLV 251 Indicates that the computed checksum did not match the checksum 252 in the IP header. 253 <legal all> 254 */ 255 256 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 257 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 258 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 259 #define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 260 261 262 /* Description FR_DS 263 264 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 265 TLV 266 Set if the 'from DS' bit is set in the frame control. 267 <legal all> 268 */ 269 270 #define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 271 #define RX_MSDU_DESC_INFO_FR_DS_LSB 24 272 #define RX_MSDU_DESC_INFO_FR_DS_MSB 24 273 #define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 274 275 276 /* Description TO_DS 277 278 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 279 TLV 280 Set if the 'to DS' bit is set in the frame control. 281 <legal all> 282 */ 283 284 #define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 285 #define RX_MSDU_DESC_INFO_TO_DS_LSB 25 286 #define RX_MSDU_DESC_INFO_TO_DS_MSB 25 287 #define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 288 289 290 /* Description INTRA_BSS 291 292 This packet needs intra-BSS routing by SW as the 'vdev_id' 293 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 294 that this MSDU was got in. 295 296 <legal all> 297 */ 298 299 #define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 300 #define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 301 #define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 302 #define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 303 304 305 /* Description DEST_CHIP_ID 306 307 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 308 to support intra-BSS routing with multi-chip multi-link 309 operation. 310 311 This indicates into which chip's TCL the packet should be 312 queued. 313 314 <legal all> 315 */ 316 317 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 318 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 319 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 320 #define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 321 322 323 /* Description DECAP_FORMAT 324 325 Indicates the format after decapsulation: 326 327 <enum 0 RAW> No encapsulation 328 <enum 1 Native_WiFi> 329 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 330 331 <enum 3 802_3> Indicate Ethernet 332 333 <legal all> 334 */ 335 336 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 337 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 338 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 339 #define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 340 341 342 /* Description DEST_CHIP_PMAC_ID 343 344 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 345 to support intra-BSS routing with multi-chip multi-link 346 operation. 347 348 This indicates into which link/'vdev' the packet should 349 be queued in TCL. 350 351 <legal all> 352 */ 353 354 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_OFFSET 0x00000000 355 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_LSB 31 356 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MSB 31 357 #define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MASK 0x80000000 358 359 360 361 #endif // RX_MSDU_DESC_INFO 362