1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_DETAILS_H_ 18 #define _RX_MSDU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_msdu_desc_info.h" 23 #include "rx_msdu_ext_desc_info.h" 24 #include "buffer_addr_info.h" 25 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 26 27 28 struct rx_msdu_details { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct buffer_addr_info buffer_addr_info_details; 31 struct rx_msdu_desc_info rx_msdu_desc_info_details; 32 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 33 #else 34 struct buffer_addr_info buffer_addr_info_details; 35 struct rx_msdu_desc_info rx_msdu_desc_info_details; 36 struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; 37 #endif 38 }; 39 40 41 /* Description BUFFER_ADDR_INFO_DETAILS 42 43 Consumer: REO/SW 44 Producer: RXDMA 45 46 Details of the physical address of the buffer containing 47 an MSDU (or entire MPDU) 48 */ 49 50 51 /* Description BUFFER_ADDR_31_0 52 53 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 54 descriptor OR Link Descriptor 55 56 In case of 'NULL' pointer, this field is set to 0 57 <legal all> 58 */ 59 60 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 61 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 62 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 63 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 64 65 66 /* Description BUFFER_ADDR_39_32 67 68 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 69 descriptor OR Link Descriptor 70 71 In case of 'NULL' pointer, this field is set to 0 72 <legal all> 73 */ 74 75 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 76 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 77 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 78 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 79 80 81 /* Description RETURN_BUFFER_MANAGER 82 83 Consumer: WBM 84 Producer: SW/FW 85 86 In case of 'NULL' pointer, this field is set to 0 87 88 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 89 descriptor OR link descriptor that is being pointed to 90 shall be returned after the frame has been processed. It 91 is used by WBM for routing purposes. 92 93 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 94 to the WMB buffer idle list 95 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 96 to the WBM idle link descriptor idle list, where the chip 97 0 WBM is chosen in case of a multi-chip config 98 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 99 to the chip 1 WBM idle link descriptor idle list 100 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 101 to the chip 2 WBM idle link descriptor idle list 102 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 103 returned to chip 3 WBM idle link descriptor idle list 104 <enum 4 FW_BM> This buffer shall be returned to the FW 105 <enum 5 SW0_BM> This buffer shall be returned to the SW, 106 ring 0 107 <enum 6 SW1_BM> This buffer shall be returned to the SW, 108 ring 1 109 <enum 7 SW2_BM> This buffer shall be returned to the SW, 110 ring 2 111 <enum 8 SW3_BM> This buffer shall be returned to the SW, 112 ring 3 113 <enum 9 SW4_BM> This buffer shall be returned to the SW, 114 ring 4 115 <enum 10 SW5_BM> This buffer shall be returned to the SW, 116 ring 5 117 <enum 11 SW6_BM> This buffer shall be returned to the SW, 118 ring 6 119 120 <legal 0-12> 121 */ 122 123 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 124 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 125 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 126 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 127 128 129 /* Description SW_BUFFER_COOKIE 130 131 Cookie field exclusively used by SW. 132 133 In case of 'NULL' pointer, this field is set to 0 134 135 HW ignores the contents, accept that it passes the programmed 136 value on to other descriptors together with the physical 137 address 138 139 Field can be used by SW to for example associate the buffers 140 physical address with the virtual address 141 The bit definitions as used by SW are within SW HLD specification 142 143 144 NOTE1: 145 The three most significant bits can have a special meaning 146 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 147 and field transmit_bw_restriction is set 148 149 In case of NON punctured transmission: 150 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 151 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 152 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 153 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 154 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 155 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 156 Sw_buffer_cookie[19:18] = 2'b11: reserved 157 158 In case of punctured transmission: 159 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 160 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 161 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 162 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 163 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 164 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 165 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 166 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 167 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 168 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 169 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 170 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 171 Sw_buffer_cookie[19:18] = 2'b11: reserved 172 173 Note: a punctured transmission is indicated by the presence 174 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 175 176 <legal all> 177 */ 178 179 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 180 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 181 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 182 #define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 183 184 185 /* Description RX_MSDU_DESC_INFO_DETAILS 186 187 Consumer: REO/SW 188 Producer: RXDMA 189 190 General information related to the MSDU that should be passed 191 on from RXDMA all the way to to the REO destination ring. 192 193 */ 194 195 196 /* Description FIRST_MSDU_IN_MPDU_FLAG 197 198 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 199 multiple buffers, this field will be valid in the Last 200 buffer used by the MSDU 201 202 <enum 0 Not_first_msdu> This is not the first MSDU in the 203 MPDU. 204 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 205 206 207 <legal all> 208 */ 209 210 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 211 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 212 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 213 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 214 215 216 /* Description LAST_MSDU_IN_MPDU_FLAG 217 218 Consumer: WBM/REO/SW/FW 219 Producer: RXDMA 220 221 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 222 multiple buffers, this field will be valid in the Last 223 buffer used by the MSDU 224 225 <enum 0 Not_last_msdu> There are more MSDUs linked to this 226 MSDU that belongs to this MPDU 227 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 228 This setting is only allowed in combination with 'Msdu_continuation' 229 set to 0. This implies that when an msdu is spread out over 230 multiple buffers and thus msdu_continuation is set, only 231 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 232 be set. 233 234 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 235 are set, the MPDU that this MSDU belongs to only contains 236 a single MSDU. 237 238 239 <legal all> 240 */ 241 242 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 243 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 244 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 245 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 246 247 248 /* Description MSDU_CONTINUATION 249 250 When set, this MSDU buffer was not able to hold the entire 251 MSDU. The next buffer will therefor contain additional 252 information related to this MSDU. 253 254 <legal all> 255 */ 256 257 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 258 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 259 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 260 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 261 262 263 /* Description MSDU_LENGTH 264 265 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 266 multiple buffers, this field will be valid in the First 267 buffer used by MSDU. 268 269 Full MSDU length in bytes after decapsulation. 270 271 This field is still valid for MPDU frames without A-MSDU. 272 It still represents MSDU length after decapsulation 273 274 Or in case of RAW MPDUs, it indicates the length of the 275 entire MPDU (without FCS field) 276 <legal all> 277 */ 278 279 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 280 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 281 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 282 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 283 284 285 /* Description MSDU_DROP 286 287 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 288 multiple buffers, this field will be valid in the Last 289 buffer used by the MSDU 290 291 When set, REO shall drop this MSDU and not forward it to 292 any other ring... 293 <legal all> 294 */ 295 296 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 297 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 298 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 299 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 300 301 302 /* Description SA_IS_VALID 303 304 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 305 multiple buffers, this field will be valid in the Last 306 buffer used by the MSDU 307 308 Indicates that OLE found a valid SA entry for this MSDU 309 <legal all> 310 */ 311 312 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 313 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 314 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 315 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 316 317 318 /* Description DA_IS_VALID 319 320 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 321 multiple buffers, this field will be valid in the Last 322 buffer used by the MSDU 323 324 Indicates that OLE found a valid DA entry for this MSDU 325 <legal all> 326 */ 327 328 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 329 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 330 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 331 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 332 333 334 /* Description DA_IS_MCBC 335 336 Field Only valid if "da_is_valid" is set 337 338 Indicates the DA address was a Multicast of Broadcast address 339 for this MSDU 340 <legal all> 341 */ 342 343 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 344 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 345 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 346 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 347 348 349 /* Description L3_HEADER_PADDING_MSB 350 351 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 352 as the LSB is always zero) 353 Number of bytes padded to make sure that the L3 header will 354 always start of a Dword boundary 355 <legal all> 356 */ 357 358 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 359 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 360 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 361 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 362 363 364 /* Description TCP_UDP_CHKSUM_FAIL 365 366 Passed on from 'RX_ATTENTION' TLV 367 Indicates that the computed checksum did not match the checksum 368 in the TCP/UDP header. 369 <legal all> 370 */ 371 372 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 373 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 374 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 375 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 376 377 378 /* Description IP_CHKSUM_FAIL 379 380 Passed on from 'RX_ATTENTION' TLV 381 Indicates that the computed checksum did not match the checksum 382 in the IP header. 383 <legal all> 384 */ 385 386 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 387 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 388 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 389 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 390 391 392 /* Description FR_DS 393 394 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 395 TLV 396 Set if the 'from DS' bit is set in the frame control. 397 <legal all> 398 */ 399 400 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 401 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 402 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 403 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 404 405 406 /* Description TO_DS 407 408 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 409 TLV 410 Set if the 'to DS' bit is set in the frame control. 411 <legal all> 412 */ 413 414 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 415 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 416 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 417 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 418 419 420 /* Description INTRA_BSS 421 422 This packet needs intra-BSS routing by SW as the 'vdev_id' 423 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 424 that this MSDU was got in. 425 426 <legal all> 427 */ 428 429 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 430 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 431 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 432 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 433 434 435 /* Description DEST_CHIP_ID 436 437 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 438 to support intra-BSS routing with multi-chip multi-link 439 operation. 440 441 This indicates into which chip's TCL the packet should be 442 queued. 443 444 <legal all> 445 */ 446 447 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 448 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 449 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 450 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 451 452 453 /* Description DECAP_FORMAT 454 455 Indicates the format after decapsulation: 456 457 <enum 0 RAW> No encapsulation 458 <enum 1 Native_WiFi> 459 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 460 461 <enum 3 802_3> Indicate Ethernet 462 463 <legal all> 464 */ 465 466 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 467 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 468 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 469 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 470 471 472 /* Description DEST_CHIP_PMAC_ID 473 474 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 475 to support intra-BSS routing with multi-chip multi-link 476 operation. 477 478 This indicates into which link/'vdev' the packet should 479 be queued in TCL. 480 481 <legal all> 482 */ 483 484 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000008 485 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 486 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 487 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 488 489 490 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 491 492 Consumer: REO/SW 493 Producer: RXDMA 494 495 Extended information related to the MSDU that is passed 496 on from RXDMA to REO but not part of the REO destination 497 ring. Some fields are passed on to PPE. 498 */ 499 500 501 /* Description REO_DESTINATION_INDICATION 502 503 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 504 multiple buffers, this field will be valid in the Last 505 buffer used by the MSDU 506 507 The ID of the REO exit ring where the MSDU frame shall push 508 after (MPDU level) reordering has finished. 509 510 <enum 0 reo_destination_sw0> Reo will push the frame into 511 the REO2SW0 ring 512 <enum 1 reo_destination_sw1> Reo will push the frame into 513 the REO2SW1 ring 514 <enum 2 reo_destination_sw2> Reo will push the frame into 515 the REO2SW2 ring 516 <enum 3 reo_destination_sw3> Reo will push the frame into 517 the REO2SW3 ring 518 <enum 4 reo_destination_sw4> Reo will push the frame into 519 the REO2SW4 ring 520 <enum 5 reo_destination_release> Reo will push the frame 521 into the REO_release ring 522 <enum 6 reo_destination_fw> Reo will push the frame into 523 the REO2FW ring 524 <enum 7 reo_destination_sw5> Reo will push the frame into 525 the REO2SW5 ring (REO remaps this in chips without REO2SW5 526 ring) 527 <enum 8 reo_destination_sw6> Reo will push the frame into 528 the REO2SW6 ring (REO remaps this in chips without REO2SW6 529 ring) 530 <enum 9 reo_destination_sw7> Reo will push the frame into 531 the REO2SW7 ring (REO remaps this in chips without REO2SW7 532 ring) 533 <enum 10 reo_destination_sw8> Reo will push the frame into 534 the REO2SW8 ring (REO remaps this in chips without REO2SW8 535 ring) 536 <enum 11 reo_destination_11> REO remaps this 537 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 538 REO remaps this 539 <enum 14 reo_destination_14> REO remaps this 540 <enum 15 reo_destination_15> REO remaps this 541 <enum 16 reo_destination_16> REO remaps this 542 <enum 17 reo_destination_17> REO remaps this 543 <enum 18 reo_destination_18> REO remaps this 544 <enum 19 reo_destination_19> REO remaps this 545 <enum 20 reo_destination_20> REO remaps this 546 <enum 21 reo_destination_21> REO remaps this 547 <enum 22 reo_destination_22> REO remaps this 548 <enum 23 reo_destination_23> REO remaps this 549 <enum 24 reo_destination_24> REO remaps this 550 <enum 25 reo_destination_25> REO remaps this 551 <enum 26 reo_destination_26> REO remaps this 552 <enum 27 reo_destination_27> REO remaps this 553 <enum 28 reo_destination_28> REO remaps this 554 <enum 29 reo_destination_29> REO remaps this 555 <enum 30 reo_destination_30> REO remaps this 556 <enum 31 reo_destination_31> REO remaps this 557 558 <legal all> 559 */ 560 561 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c 562 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 563 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 564 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 565 566 567 /* Description SERVICE_CODE 568 569 Opaque service code between PPE and Wi-Fi 570 571 This field gets passed on by REO to PPE in the EDMA descriptor 572 ('REO_TO_PPE_RING'). 573 574 <legal all> 575 */ 576 577 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c 578 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 579 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 580 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 581 582 583 /* Description PRIORITY_VALID 584 585 This field gets passed on by REO to PPE in the EDMA descriptor 586 ('REO_TO_PPE_RING'). 587 588 <legal all> 589 */ 590 591 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c 592 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 593 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 594 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 595 596 597 /* Description DATA_OFFSET 598 599 The offset to Rx packet data within the buffer (including 600 Rx DMA offset programming and L3 header padding inserted 601 by Rx OLE). 602 603 This field gets passed on by REO to PPE in the EDMA descriptor 604 ('REO_TO_PPE_RING'). 605 606 <legal all> 607 */ 608 609 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c 610 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 611 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 612 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 613 614 615 /* Description SRC_LINK_ID 616 617 Consumer: SW 618 Producer: RXDMA 619 620 Set to the link ID of the PMAC that received the frame 621 <legal all> 622 */ 623 624 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c 625 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 626 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 627 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 628 629 630 /* Description RESERVED_0A 631 632 <legal 0> 633 */ 634 635 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c 636 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 637 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 638 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 639 640 641 642 #endif // RX_MSDU_DETAILS 643