1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_END_H_ 18 #define _RX_MSDU_END_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_MSDU_END 32 23 24 #define NUM_OF_QWORDS_RX_MSDU_END 16 25 26 27 struct rx_msdu_end { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 30 sw_frame_group_id : 7, // [8:2] 31 reserved_0 : 7, // [15:9] 32 phy_ppdu_id : 16; // [31:16] 33 uint32_t ip_hdr_chksum : 16, // [15:0] 34 reported_mpdu_length : 14, // [29:16] 35 reserved_1a : 2; // [31:30] 36 uint32_t reserved_2a : 8, // [7:0] 37 cce_super_rule : 6, // [13:8] 38 cce_classify_not_done_truncate : 1, // [14:14] 39 cce_classify_not_done_cce_dis : 1, // [15:15] 40 cumulative_l3_checksum : 16; // [31:16] 41 uint32_t rule_indication_31_0 : 32; // [31:0] 42 uint32_t ipv6_options_crc : 32; // [31:0] 43 uint32_t da_offset : 6, // [5:0] 44 sa_offset : 6, // [11:6] 45 da_offset_valid : 1, // [12:12] 46 sa_offset_valid : 1, // [13:13] 47 reserved_5a : 2, // [15:14] 48 l3_type : 16; // [31:16] 49 uint32_t rule_indication_63_32 : 32; // [31:0] 50 uint32_t tcp_seq_number : 32; // [31:0] 51 uint32_t tcp_ack_number : 32; // [31:0] 52 uint32_t tcp_flag : 9, // [8:0] 53 lro_eligible : 1, // [9:9] 54 reserved_9a : 6, // [15:10] 55 window_size : 16; // [31:16] 56 uint32_t sa_sw_peer_id : 16, // [15:0] 57 sa_idx_timeout : 1, // [16:16] 58 da_idx_timeout : 1, // [17:17] 59 to_ds : 1, // [18:18] 60 tid : 4, // [22:19] 61 sa_is_valid : 1, // [23:23] 62 da_is_valid : 1, // [24:24] 63 da_is_mcbc : 1, // [25:25] 64 l3_header_padding : 2, // [27:26] 65 first_msdu : 1, // [28:28] 66 last_msdu : 1, // [29:29] 67 fr_ds : 1, // [30:30] 68 ip_chksum_fail_copy : 1; // [31:31] 69 uint32_t sa_idx : 16, // [15:0] 70 da_idx_or_sw_peer_id : 16; // [31:16] 71 uint32_t msdu_drop : 1, // [0:0] 72 reo_destination_indication : 5, // [5:1] 73 flow_idx : 20, // [25:6] 74 use_ppe : 1, // [26:26] 75 mesh_sta : 2, // [28:27] 76 vlan_ctag_stripped : 1, // [29:29] 77 vlan_stag_stripped : 1, // [30:30] 78 fragment_flag : 1; // [31:31] 79 uint32_t fse_metadata : 32; // [31:0] 80 uint32_t cce_metadata : 16, // [15:0] 81 tcp_udp_chksum : 16; // [31:16] 82 uint32_t aggregation_count : 8, // [7:0] 83 flow_aggregation_continuation : 1, // [8:8] 84 fisa_timeout : 1, // [9:9] 85 tcp_udp_chksum_fail_copy : 1, // [10:10] 86 msdu_limit_error : 1, // [11:11] 87 flow_idx_timeout : 1, // [12:12] 88 flow_idx_invalid : 1, // [13:13] 89 cce_match : 1, // [14:14] 90 amsdu_parser_error : 1, // [15:15] 91 cumulative_ip_length : 16; // [31:16] 92 uint32_t key_id_octet : 8, // [7:0] 93 reserved_16a : 24; // [31:8] 94 uint32_t reserved_17a : 6, // [5:0] 95 service_code : 9, // [14:6] 96 priority_valid : 1, // [15:15] 97 intra_bss : 1, // [16:16] 98 dest_chip_id : 2, // [18:17] 99 multicast_echo : 1, // [19:19] 100 wds_learning_event : 1, // [20:20] 101 wds_roaming_event : 1, // [21:21] 102 wds_keep_alive_event : 1, // [22:22] 103 dest_chip_pmac_id : 1, // [23:23] 104 reserved_17b : 8; // [31:24] 105 uint32_t msdu_length : 14, // [13:0] 106 stbc : 1, // [14:14] 107 ipsec_esp : 1, // [15:15] 108 l3_offset : 7, // [22:16] 109 ipsec_ah : 1, // [23:23] 110 l4_offset : 8; // [31:24] 111 uint32_t msdu_number : 8, // [7:0] 112 decap_format : 2, // [9:8] 113 ipv4_proto : 1, // [10:10] 114 ipv6_proto : 1, // [11:11] 115 tcp_proto : 1, // [12:12] 116 udp_proto : 1, // [13:13] 117 ip_frag : 1, // [14:14] 118 tcp_only_ack : 1, // [15:15] 119 da_is_bcast_mcast : 1, // [16:16] 120 toeplitz_hash_sel : 2, // [18:17] 121 ip_fixed_header_valid : 1, // [19:19] 122 ip_extn_header_valid : 1, // [20:20] 123 tcp_udp_header_valid : 1, // [21:21] 124 mesh_control_present : 1, // [22:22] 125 ldpc : 1, // [23:23] 126 ip4_protocol_ip6_next_header : 8; // [31:24] 127 uint32_t vlan_ctag_ci : 16, // [15:0] 128 vlan_stag_ci : 16; // [31:16] 129 uint32_t peer_meta_data : 32; // [31:0] 130 uint32_t user_rssi : 8, // [7:0] 131 pkt_type : 4, // [11:8] 132 sgi : 2, // [13:12] 133 rate_mcs : 4, // [17:14] 134 receive_bandwidth : 3, // [20:18] 135 reception_type : 3, // [23:21] 136 mimo_ss_bitmap : 7, // [30:24] 137 msdu_done_copy : 1; // [31:31] 138 uint32_t flow_id_toeplitz : 32; // [31:0] 139 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 140 uint32_t sw_phy_meta_data : 32; // [31:0] 141 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 142 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 143 uint32_t reserved_28a : 16, // [15:0] 144 sa_15_0 : 16; // [31:16] 145 uint32_t sa_47_16 : 32; // [31:0] 146 uint32_t first_mpdu : 1, // [0:0] 147 reserved_30a : 1, // [1:1] 148 mcast_bcast : 1, // [2:2] 149 ast_index_not_found : 1, // [3:3] 150 ast_index_timeout : 1, // [4:4] 151 power_mgmt : 1, // [5:5] 152 non_qos : 1, // [6:6] 153 null_data : 1, // [7:7] 154 mgmt_type : 1, // [8:8] 155 ctrl_type : 1, // [9:9] 156 more_data : 1, // [10:10] 157 eosp : 1, // [11:11] 158 a_msdu_error : 1, // [12:12] 159 reserved_30b : 1, // [13:13] 160 order : 1, // [14:14] 161 wifi_parser_error : 1, // [15:15] 162 overflow_err : 1, // [16:16] 163 msdu_length_err : 1, // [17:17] 164 tcp_udp_chksum_fail : 1, // [18:18] 165 ip_chksum_fail : 1, // [19:19] 166 sa_idx_invalid : 1, // [20:20] 167 da_idx_invalid : 1, // [21:21] 168 amsdu_addr_mismatch : 1, // [22:22] 169 rx_in_tx_decrypt_byp : 1, // [23:23] 170 encrypt_required : 1, // [24:24] 171 directed : 1, // [25:25] 172 buffer_fragment : 1, // [26:26] 173 mpdu_length_err : 1, // [27:27] 174 tkip_mic_err : 1, // [28:28] 175 decrypt_err : 1, // [29:29] 176 unencrypted_frame_err : 1, // [30:30] 177 fcs_err : 1; // [31:31] 178 uint32_t reserved_31a : 10, // [9:0] 179 decrypt_status_code : 3, // [12:10] 180 rx_bitmap_not_updated : 1, // [13:13] 181 reserved_31b : 17, // [30:14] 182 msdu_done : 1; // [31:31] 183 #else 184 uint32_t phy_ppdu_id : 16, // [31:16] 185 reserved_0 : 7, // [15:9] 186 sw_frame_group_id : 7, // [8:2] 187 rxpcu_mpdu_filter_in_category : 2; // [1:0] 188 uint32_t reserved_1a : 2, // [31:30] 189 reported_mpdu_length : 14, // [29:16] 190 ip_hdr_chksum : 16; // [15:0] 191 uint32_t cumulative_l3_checksum : 16, // [31:16] 192 cce_classify_not_done_cce_dis : 1, // [15:15] 193 cce_classify_not_done_truncate : 1, // [14:14] 194 cce_super_rule : 6, // [13:8] 195 reserved_2a : 8; // [7:0] 196 uint32_t rule_indication_31_0 : 32; // [31:0] 197 uint32_t ipv6_options_crc : 32; // [31:0] 198 uint32_t l3_type : 16, // [31:16] 199 reserved_5a : 2, // [15:14] 200 sa_offset_valid : 1, // [13:13] 201 da_offset_valid : 1, // [12:12] 202 sa_offset : 6, // [11:6] 203 da_offset : 6; // [5:0] 204 uint32_t rule_indication_63_32 : 32; // [31:0] 205 uint32_t tcp_seq_number : 32; // [31:0] 206 uint32_t tcp_ack_number : 32; // [31:0] 207 uint32_t window_size : 16, // [31:16] 208 reserved_9a : 6, // [15:10] 209 lro_eligible : 1, // [9:9] 210 tcp_flag : 9; // [8:0] 211 uint32_t ip_chksum_fail_copy : 1, // [31:31] 212 fr_ds : 1, // [30:30] 213 last_msdu : 1, // [29:29] 214 first_msdu : 1, // [28:28] 215 l3_header_padding : 2, // [27:26] 216 da_is_mcbc : 1, // [25:25] 217 da_is_valid : 1, // [24:24] 218 sa_is_valid : 1, // [23:23] 219 tid : 4, // [22:19] 220 to_ds : 1, // [18:18] 221 da_idx_timeout : 1, // [17:17] 222 sa_idx_timeout : 1, // [16:16] 223 sa_sw_peer_id : 16; // [15:0] 224 uint32_t da_idx_or_sw_peer_id : 16, // [31:16] 225 sa_idx : 16; // [15:0] 226 uint32_t fragment_flag : 1, // [31:31] 227 vlan_stag_stripped : 1, // [30:30] 228 vlan_ctag_stripped : 1, // [29:29] 229 mesh_sta : 2, // [28:27] 230 use_ppe : 1, // [26:26] 231 flow_idx : 20, // [25:6] 232 reo_destination_indication : 5, // [5:1] 233 msdu_drop : 1; // [0:0] 234 uint32_t fse_metadata : 32; // [31:0] 235 uint32_t tcp_udp_chksum : 16, // [31:16] 236 cce_metadata : 16; // [15:0] 237 uint32_t cumulative_ip_length : 16, // [31:16] 238 amsdu_parser_error : 1, // [15:15] 239 cce_match : 1, // [14:14] 240 flow_idx_invalid : 1, // [13:13] 241 flow_idx_timeout : 1, // [12:12] 242 msdu_limit_error : 1, // [11:11] 243 tcp_udp_chksum_fail_copy : 1, // [10:10] 244 fisa_timeout : 1, // [9:9] 245 flow_aggregation_continuation : 1, // [8:8] 246 aggregation_count : 8; // [7:0] 247 uint32_t reserved_16a : 24, // [31:8] 248 key_id_octet : 8; // [7:0] 249 uint32_t reserved_17b : 8, // [31:24] 250 dest_chip_pmac_id : 1, // [23:23] 251 wds_keep_alive_event : 1, // [22:22] 252 wds_roaming_event : 1, // [21:21] 253 wds_learning_event : 1, // [20:20] 254 multicast_echo : 1, // [19:19] 255 dest_chip_id : 2, // [18:17] 256 intra_bss : 1, // [16:16] 257 priority_valid : 1, // [15:15] 258 service_code : 9, // [14:6] 259 reserved_17a : 6; // [5:0] 260 uint32_t l4_offset : 8, // [31:24] 261 ipsec_ah : 1, // [23:23] 262 l3_offset : 7, // [22:16] 263 ipsec_esp : 1, // [15:15] 264 stbc : 1, // [14:14] 265 msdu_length : 14; // [13:0] 266 uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] 267 ldpc : 1, // [23:23] 268 mesh_control_present : 1, // [22:22] 269 tcp_udp_header_valid : 1, // [21:21] 270 ip_extn_header_valid : 1, // [20:20] 271 ip_fixed_header_valid : 1, // [19:19] 272 toeplitz_hash_sel : 2, // [18:17] 273 da_is_bcast_mcast : 1, // [16:16] 274 tcp_only_ack : 1, // [15:15] 275 ip_frag : 1, // [14:14] 276 udp_proto : 1, // [13:13] 277 tcp_proto : 1, // [12:12] 278 ipv6_proto : 1, // [11:11] 279 ipv4_proto : 1, // [10:10] 280 decap_format : 2, // [9:8] 281 msdu_number : 8; // [7:0] 282 uint32_t vlan_stag_ci : 16, // [31:16] 283 vlan_ctag_ci : 16; // [15:0] 284 uint32_t peer_meta_data : 32; // [31:0] 285 uint32_t msdu_done_copy : 1, // [31:31] 286 mimo_ss_bitmap : 7, // [30:24] 287 reception_type : 3, // [23:21] 288 receive_bandwidth : 3, // [20:18] 289 rate_mcs : 4, // [17:14] 290 sgi : 2, // [13:12] 291 pkt_type : 4, // [11:8] 292 user_rssi : 8; // [7:0] 293 uint32_t flow_id_toeplitz : 32; // [31:0] 294 uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] 295 uint32_t sw_phy_meta_data : 32; // [31:0] 296 uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] 297 uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] 298 uint32_t sa_15_0 : 16, // [31:16] 299 reserved_28a : 16; // [15:0] 300 uint32_t sa_47_16 : 32; // [31:0] 301 uint32_t fcs_err : 1, // [31:31] 302 unencrypted_frame_err : 1, // [30:30] 303 decrypt_err : 1, // [29:29] 304 tkip_mic_err : 1, // [28:28] 305 mpdu_length_err : 1, // [27:27] 306 buffer_fragment : 1, // [26:26] 307 directed : 1, // [25:25] 308 encrypt_required : 1, // [24:24] 309 rx_in_tx_decrypt_byp : 1, // [23:23] 310 amsdu_addr_mismatch : 1, // [22:22] 311 da_idx_invalid : 1, // [21:21] 312 sa_idx_invalid : 1, // [20:20] 313 ip_chksum_fail : 1, // [19:19] 314 tcp_udp_chksum_fail : 1, // [18:18] 315 msdu_length_err : 1, // [17:17] 316 overflow_err : 1, // [16:16] 317 wifi_parser_error : 1, // [15:15] 318 order : 1, // [14:14] 319 reserved_30b : 1, // [13:13] 320 a_msdu_error : 1, // [12:12] 321 eosp : 1, // [11:11] 322 more_data : 1, // [10:10] 323 ctrl_type : 1, // [9:9] 324 mgmt_type : 1, // [8:8] 325 null_data : 1, // [7:7] 326 non_qos : 1, // [6:6] 327 power_mgmt : 1, // [5:5] 328 ast_index_timeout : 1, // [4:4] 329 ast_index_not_found : 1, // [3:3] 330 mcast_bcast : 1, // [2:2] 331 reserved_30a : 1, // [1:1] 332 first_mpdu : 1; // [0:0] 333 uint32_t msdu_done : 1, // [31:31] 334 reserved_31b : 17, // [30:14] 335 rx_bitmap_not_updated : 1, // [13:13] 336 decrypt_status_code : 3, // [12:10] 337 reserved_31a : 10; // [9:0] 338 #endif 339 }; 340 341 342 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 343 344 Field indicates what the reason was that this MPDU frame 345 was allowed to come into the receive path by RXPCU 346 <enum 0 rxpcu_filter_pass> This MPDU passed the normal frame 347 filter programming of rxpcu 348 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 349 regular frame filter and would have been dropped, were 350 it not for the frame fitting into the 'monitor_client' category. 351 352 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 353 regular frame filter and also did not pass the rxpcu_monitor_client 354 filter. It would have been dropped accept that it did pass 355 the 'monitor_other' category. 356 <enum 3 rxpcu_filter_pass_monitor_ovrd> This MPDU passed 357 the normal frame filter programming of RXPCU but additionally 358 fit into the 'monitor_override_client' category. 359 <legal 0-3> 360 */ 361 362 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 363 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 364 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 365 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 366 367 368 369 #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 370 #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 371 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 372 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 373 374 375 /* Description RESERVED_0 376 377 <legal 0> 378 */ 379 380 #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 381 #define RX_MSDU_END_RESERVED_0_LSB 9 382 #define RX_MSDU_END_RESERVED_0_MSB 15 383 #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 384 385 386 /* Description PHY_PPDU_ID 387 388 A ppdu counter value that PHY increments for every PPDU 389 received. The counter value wraps around 390 <legal all> 391 */ 392 393 #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 394 #define RX_MSDU_END_PHY_PPDU_ID_LSB 16 395 #define RX_MSDU_END_PHY_PPDU_ID_MSB 31 396 #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 397 398 399 /* Description IP_HDR_CHKSUM 400 401 This can include the IP header checksum or the pseudo header 402 checksum used by TCP/UDP checksum. 403 (with the first byte in the MSB and the second byte in the 404 LSB, i.e. requiring a byte-swap for little-endian FW/SW 405 w.r.t. the byte order in a packet) 406 */ 407 408 #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 409 #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 410 #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 411 #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 412 413 414 /* Description REPORTED_MPDU_LENGTH 415 416 MPDU length before decapsulation. Only valid when first_msdu 417 is set. This field is taken directly from the length field 418 of the A-MPDU delimiter or the preamble length field for 419 non-A-MPDU frames. 420 */ 421 422 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 423 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 424 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 425 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 426 427 428 /* Description RESERVED_1A 429 430 <legal 0> 431 */ 432 433 #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 434 #define RX_MSDU_END_RESERVED_1A_LSB 62 435 #define RX_MSDU_END_RESERVED_1A_MSB 63 436 #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 437 438 439 #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 440 #define RX_MSDU_END_RESERVED_2A_LSB 0 441 #define RX_MSDU_END_RESERVED_2A_MSB 7 442 #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff 443 444 445 /* Description CCE_SUPER_RULE 446 447 Indicates the super filter rule 448 */ 449 450 #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 451 #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 452 #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 453 #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 454 455 456 /* Description CCE_CLASSIFY_NOT_DONE_TRUNCATE 457 458 Classification failed due to truncated frame 459 */ 460 461 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 462 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 463 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 464 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 465 466 467 /* Description CCE_CLASSIFY_NOT_DONE_CCE_DIS 468 469 Classification failed due to CCE global disable 470 */ 471 472 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 473 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 474 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 475 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 476 477 478 /* Description CUMULATIVE_L3_CHECKSUM 479 480 FISA: IP header checksum including the total MSDU length 481 that is part of this flow aggregated so far, reported if 482 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set 483 484 Set to zero in chips not supporting FISA 485 <legal all> 486 */ 487 488 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 489 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 490 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 491 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 492 493 494 /* Description RULE_INDICATION_31_0 495 496 Bitmap indicating which of rules 31-0 have matched 497 498 In chips with more than 64 CCE rules, RXOLE 499 shall have a configuration to report any two rule_indication_* 500 in 'RX_MSDU_END.' 501 */ 502 503 #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 504 #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 505 #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 506 #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 507 508 509 #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 510 #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 511 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 512 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff 513 514 515 /* Description DA_OFFSET 516 517 Offset into MSDU buffer for DA 518 */ 519 520 #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 521 #define RX_MSDU_END_DA_OFFSET_LSB 32 522 #define RX_MSDU_END_DA_OFFSET_MSB 37 523 #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 524 525 526 /* Description SA_OFFSET 527 528 Offset into MSDU buffer for SA 529 */ 530 531 #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 532 #define RX_MSDU_END_SA_OFFSET_LSB 38 533 #define RX_MSDU_END_SA_OFFSET_MSB 43 534 #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 535 536 537 /* Description DA_OFFSET_VALID 538 539 da_offset field is valid. This will be set to 0 in case 540 of a dynamic A-MSDU when DA is compressed 541 */ 542 543 #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 544 #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 545 #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 546 #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 547 548 549 /* Description SA_OFFSET_VALID 550 551 sa_offset field is valid. This will be set to 0 in case 552 of a dynamic A-MSDU when SA is compressed 553 */ 554 555 #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 556 #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 557 #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 558 #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 559 560 561 /* Description RESERVED_5A 562 563 <legal 0> 564 */ 565 566 #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 567 #define RX_MSDU_END_RESERVED_5A_LSB 46 568 #define RX_MSDU_END_RESERVED_5A_MSB 47 569 #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 570 571 572 /* Description L3_TYPE 573 574 The 16-bit type value indicating the type of L3 later extracted 575 from LLC/SNAP, set to zero if SNAP is not available 576 */ 577 578 #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 579 #define RX_MSDU_END_L3_TYPE_LSB 48 580 #define RX_MSDU_END_L3_TYPE_MSB 63 581 #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 582 583 584 /* Description RULE_INDICATION_63_32 585 586 Bitmap indicating which of rules 63-32 have matched 587 588 In chips with more than 64 CCE rules, RXOLE 589 shall have a configuration to report any two rule_indication_* 590 in 'RX_MSDU_END.' 591 592 */ 593 594 #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 595 #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 596 #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 597 #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff 598 599 600 /* Description TCP_SEQ_NUMBER 601 602 TCP sequence number (as a number assembled from a TCP packet 603 in big-endian order, i.e. requiring a byte-swap for little-endian 604 FW/SW w.r.t. the byte order in a packet) 605 606 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' 607 is set, toeplitz_hash_2_or_4 from 'RX_MSDU_START' will be 608 reported here: 609 Controlled by multiple RxOLE registers for TCP/UDP over 610 IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 611 or IPv6 src/dest addresses is reported; or, Toeplitz hash 612 computed over 4-tuple IPv4 or IPv6 src/dest addresses and 613 src/dest ports is reported. The Flow_id_toeplitz hash can 614 also be reported here. Usually the hash reported here is 615 the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy 616 in 'RXPT_CLASSIFY_INFO'). Optionally the 3-tuple Toeplitz 617 hash over IPv4 or IPv6 src/dest addresses and L4 protocol 618 can be reported here. 619 */ 620 621 #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 622 #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 623 #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 624 #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 625 626 627 /* Description TCP_ACK_NUMBER 628 629 TCP acknowledge number (as a number assembled from a TCP 630 packet in big-endian order, i.e. requiring a byte-swap 631 for little-endian FW/SW w.r.t. the byte order in a packet) 632 633 634 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' 635 is set, flow_id_toeplitz from 'RX_MSDU_START' will be reported 636 here: 637 Toeplitz hash of 5-tuple {IP source address, IP destination 638 address, IP source port, IP destination port, L4 protocol} 639 in case of non-IPSec. In case of IPSec - Toeplitz hash 640 of 4-tuple {IP source address, IP destination address, SPI, 641 L4 protocol}. Optionally the 3-tuple Toeplitz hash over 642 IPv4 or IPv6 src/dest addresses and L4 protocol can be reported 643 here. 644 The relevant Toeplitz key registers are provided in RxOLE's 645 instance of common parser module. These registers are separate 646 from the Toeplitz keys used by ASE/FSE modules inside RxOLE. 647 The actual value will be passed on from common parser module 648 to RxOLE in one of the WHO_* TLVs. 649 */ 650 651 #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 652 #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 653 #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 654 #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff 655 656 657 /* Description TCP_FLAG 658 659 TCP flags 660 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit in 661 bit 8 and the FIN bit in bit 0, i.e. in big-endian order, 662 i.e. requiring a byte-swap for little-endian FW/SW w.r.t. 663 the byte order in a packet) 664 */ 665 666 #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 667 #define RX_MSDU_END_TCP_FLAG_LSB 32 668 #define RX_MSDU_END_TCP_FLAG_MSB 40 669 #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 670 671 672 /* Description LRO_ELIGIBLE 673 674 Computed out of TCP and IP fields to indicate that this 675 MSDU is eligible for LRO 676 */ 677 678 #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 679 #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 680 #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 681 #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 682 683 684 /* Description RESERVED_9A 685 686 NOTE: DO not assign a field... Internally used in RXOLE.. 687 688 <legal 0> 689 */ 690 691 #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 692 #define RX_MSDU_END_RESERVED_9A_LSB 42 693 #define RX_MSDU_END_RESERVED_9A_MSB 47 694 #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 695 696 697 /* Description WINDOW_SIZE 698 699 TCP receive window size (as a number assembled from a TCP 700 packet in big-endian order, i.e. requiring a byte-swap 701 for little-endian FW/SW w.r.t. the byte order in a packet) 702 703 704 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' 705 is set, msdu_length from 'RX_MSDU_START' will be reported 706 in the 14 LSBs here: 707 MSDU length in bytes after decapsulation. This field is 708 still valid for MPDU frames without A-MSDU. It still represents 709 MSDU length after decapsulation. 710 */ 711 712 #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 713 #define RX_MSDU_END_WINDOW_SIZE_LSB 48 714 #define RX_MSDU_END_WINDOW_SIZE_MSB 63 715 #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 716 717 718 /* Description SA_SW_PEER_ID 719 720 sw_peer_id from the address search entry corresponding to 721 the source address of the MSDU 722 723 <legal all> 724 */ 725 726 #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 727 #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 728 #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 729 #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff 730 731 732 /* Description SA_IDX_TIMEOUT 733 734 Indicates an unsuccessful MAC source address search due 735 to the expiring of the search timer. 736 */ 737 738 #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 739 #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 740 #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 741 #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 742 743 744 /* Description DA_IDX_TIMEOUT 745 746 Indicates an unsuccessful MAC destination address search 747 due to the expiring of the search timer. 748 */ 749 750 #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 751 #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 752 #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 753 #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 754 755 756 /* Description TO_DS 757 758 Set if the to DS bit is set in the frame control. 759 760 RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' 761 762 763 <legal all> 764 */ 765 766 #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 767 #define RX_MSDU_END_TO_DS_LSB 18 768 #define RX_MSDU_END_TO_DS_MSB 18 769 #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 770 771 772 773 #define RX_MSDU_END_TID_OFFSET 0x0000000000000028 774 #define RX_MSDU_END_TID_LSB 19 775 #define RX_MSDU_END_TID_MSB 22 776 #define RX_MSDU_END_TID_MASK 0x0000000000780000 777 778 779 /* Description SA_IS_VALID 780 781 Indicates that OLE found a valid SA entry 782 */ 783 784 #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 785 #define RX_MSDU_END_SA_IS_VALID_LSB 23 786 #define RX_MSDU_END_SA_IS_VALID_MSB 23 787 #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 788 789 790 /* Description DA_IS_VALID 791 792 Indicates that OLE found a valid DA entry 793 */ 794 795 #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 796 #define RX_MSDU_END_DA_IS_VALID_LSB 24 797 #define RX_MSDU_END_DA_IS_VALID_MSB 24 798 #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 799 800 801 /* Description DA_IS_MCBC 802 803 Field Only valid if "da_is_valid" is set 804 805 Indicates the DA address was a Multicast of Broadcast address. 806 807 */ 808 809 #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 810 #define RX_MSDU_END_DA_IS_MCBC_LSB 25 811 #define RX_MSDU_END_DA_IS_MCBC_MSB 25 812 #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 813 814 815 /* Description L3_HEADER_PADDING 816 817 Number of bytes padded to make sure that the L3 header 818 will always start of a Dword boundary 819 */ 820 821 #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 822 #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 823 #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 824 #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 825 826 827 /* Description FIRST_MSDU 828 829 Indicates the first MSDU of A-MSDU. If both first_msdu 830 and last_msdu are set in the MSDU then this is a non-aggregated 831 MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 832 have both first_mpdu and last_mpdu bits set to 0. 833 */ 834 835 #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 836 #define RX_MSDU_END_FIRST_MSDU_LSB 28 837 #define RX_MSDU_END_FIRST_MSDU_MSB 28 838 #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 839 840 841 /* Description LAST_MSDU 842 843 Indicates the last MSDU of the A-MSDU. MPDU end status 844 is only valid when last_msdu is set. 845 */ 846 847 #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 848 #define RX_MSDU_END_LAST_MSDU_LSB 29 849 #define RX_MSDU_END_LAST_MSDU_MSB 29 850 #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 851 852 853 /* Description FR_DS 854 855 Set if the from DS bit is set in the frame control. 856 857 RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' 858 859 <legal all> 860 */ 861 862 #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 863 #define RX_MSDU_END_FR_DS_LSB 30 864 #define RX_MSDU_END_FR_DS_MSB 30 865 #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 866 867 868 /* Description IP_CHKSUM_FAIL_COPY 869 870 If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, 871 ip_chksum_fail from 'RX_ATTENTION' will be reported in the 872 MSB here: 873 Indicates that the computed checksum (ip_hdr_chksum) did 874 not match the checksum in the IP header. 875 */ 876 877 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 878 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 879 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 880 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 881 882 883 /* Description SA_IDX 884 885 The offset in the address table which matches the MAC source 886 address. 887 */ 888 889 #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 890 #define RX_MSDU_END_SA_IDX_LSB 32 891 #define RX_MSDU_END_SA_IDX_MSB 47 892 #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 893 894 895 /* Description DA_IDX_OR_SW_PEER_ID 896 897 Based on a register configuration in RXOLE, this field will 898 contain: 899 The offset in the address table which matches the MAC destination 900 address 901 OR: 902 sw_peer_id from the address search entry corresponding to 903 the destination address of the MSDU 904 */ 905 906 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 907 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 908 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 909 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 910 911 912 /* Description MSDU_DROP 913 914 When set, REO shall drop this MSDU and not forward it to 915 any other ring... 916 <legal all> 917 */ 918 919 #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 920 #define RX_MSDU_END_MSDU_DROP_LSB 0 921 #define RX_MSDU_END_MSDU_DROP_MSB 0 922 #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 923 924 925 /* Description REO_DESTINATION_INDICATION 926 927 The ID of the REO exit ring where the MSDU frame shall push 928 after (MPDU level) reordering has finished. 929 930 <enum 0 reo_destination_sw0> Reo will push the frame into 931 the REO2SW0 ring 932 <enum 1 reo_destination_sw1> Reo will push the frame into 933 the REO2SW1 ring 934 <enum 2 reo_destination_sw2> Reo will push the frame into 935 the REO2SW2 ring 936 <enum 3 reo_destination_sw3> Reo will push the frame into 937 the REO2SW3 ring 938 <enum 4 reo_destination_sw4> Reo will push the frame into 939 the REO2SW4 ring 940 <enum 5 reo_destination_release> Reo will push the frame 941 into the REO_release ring 942 <enum 6 reo_destination_fw> Reo will push the frame into 943 the REO2FW ring 944 <enum 7 reo_destination_sw5> Reo will push the frame into 945 the REO2SW5 ring (REO remaps this in chips without REO2SW5 946 ring) 947 <enum 8 reo_destination_sw6> Reo will push the frame into 948 the REO2SW6 ring (REO remaps this in chips without REO2SW6 949 ring) 950 <enum 9 reo_destination_sw7> Reo will push the frame into 951 the REO2SW7 ring (REO remaps this in chips without REO2SW7 952 ring) 953 <enum 10 reo_destination_sw8> Reo will push the frame into 954 the REO2SW8 ring (REO remaps this in chips without REO2SW8 955 ring) 956 <enum 11 reo_destination_11> REO remaps this 957 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 958 REO remaps this 959 <enum 14 reo_destination_14> REO remaps this 960 <enum 15 reo_destination_15> REO remaps this 961 <enum 16 reo_destination_16> REO remaps this 962 <enum 17 reo_destination_17> REO remaps this 963 <enum 18 reo_destination_18> REO remaps this 964 <enum 19 reo_destination_19> REO remaps this 965 <enum 20 reo_destination_20> REO remaps this 966 <enum 21 reo_destination_21> REO remaps this 967 <enum 22 reo_destination_22> REO remaps this 968 <enum 23 reo_destination_23> REO remaps this 969 <enum 24 reo_destination_24> REO remaps this 970 <enum 25 reo_destination_25> REO remaps this 971 <enum 26 reo_destination_26> REO remaps this 972 <enum 27 reo_destination_27> REO remaps this 973 <enum 28 reo_destination_28> REO remaps this 974 <enum 29 reo_destination_29> REO remaps this 975 <enum 30 reo_destination_30> REO remaps this 976 <enum 31 reo_destination_31> REO remaps this 977 978 <legal all> 979 */ 980 981 #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 982 #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 983 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 984 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e 985 986 987 /* Description FLOW_IDX 988 989 Flow table index 990 <legal all> 991 */ 992 993 #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 994 #define RX_MSDU_END_FLOW_IDX_LSB 6 995 #define RX_MSDU_END_FLOW_IDX_MSB 25 996 #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 997 998 999 /* Description USE_PPE 1000 1001 Indicates to RXDMA to ignore the REO_destination_indication 1002 and use a programmed value corresponding to the REO2PPE 1003 ring 1004 1005 This override to REO2PPE for packets requiring multiple 1006 buffers shall be disabled based on an RXDMA configuration, 1007 as PPE may not support such packets. 1008 <legal all> 1009 */ 1010 1011 #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 1012 #define RX_MSDU_END_USE_PPE_LSB 26 1013 #define RX_MSDU_END_USE_PPE_MSB 26 1014 #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 1015 1016 1017 /* Description MESH_STA 1018 1019 When set, this is a Mesh (11s) STA. 1020 1021 The interpretation of the A-MSDU 'Length' field in the MPDU 1022 (if any) is decided by the e-numerations below. 1023 1024 <enum 0 MESH_DISABLE> 1025 <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and includes 1026 the length of Mesh Control. 1027 <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and excludes 1028 the length of Mesh Control. 1029 <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian and 1030 excludes the length of Mesh Control. This is 802.11s-compliant. 1031 1032 <legal all> 1033 */ 1034 1035 #define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 1036 #define RX_MSDU_END_MESH_STA_LSB 27 1037 #define RX_MSDU_END_MESH_STA_MSB 28 1038 #define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 1039 1040 1041 /* Description VLAN_CTAG_STRIPPED 1042 1043 Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the 1044 packet 1045 <legal all> 1046 */ 1047 1048 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 1049 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 1050 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 1051 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 1052 1053 1054 /* Description VLAN_STAG_STRIPPED 1055 1056 Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the 1057 packet 1058 <legal all> 1059 */ 1060 1061 #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 1062 #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 1063 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 1064 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 1065 1066 1067 /* Description FRAGMENT_FLAG 1068 1069 Indicates that this is an 802.11 fragment frame. This is 1070 set when either the more_frag bit is set in the frame control 1071 or the fragment number is not zero. Only set when first_msdu 1072 is set. 1073 */ 1074 1075 #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 1076 #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 1077 #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 1078 #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 1079 1080 1081 /* Description FSE_METADATA 1082 1083 FSE related meta data: 1084 <legal all> 1085 */ 1086 1087 #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 1088 #define RX_MSDU_END_FSE_METADATA_LSB 32 1089 #define RX_MSDU_END_FSE_METADATA_MSB 63 1090 #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 1091 1092 1093 /* Description CCE_METADATA 1094 1095 CCE related meta data: 1096 <legal all> 1097 */ 1098 1099 #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 1100 #define RX_MSDU_END_CCE_METADATA_LSB 0 1101 #define RX_MSDU_END_CCE_METADATA_MSB 15 1102 #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff 1103 1104 1105 1106 #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 1107 #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 1108 #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 1109 #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 1110 1111 1112 /* Description AGGREGATION_COUNT 1113 1114 FISA: Number of MSDU's aggregated so far 1115 1116 Set to zero in chips not supporting FISA 1117 <legal all> 1118 */ 1119 1120 #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 1121 #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 1122 #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 1123 #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 1124 1125 1126 /* Description FLOW_AGGREGATION_CONTINUATION 1127 1128 FISA: To indicate that this MSDU can be aggregated with 1129 the previous packet with the same flow id 1130 1131 Set to zero in chips not supporting FISA 1132 <legal all> 1133 */ 1134 1135 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 1136 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 1137 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 1138 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 1139 1140 1141 /* Description FISA_TIMEOUT 1142 1143 FISA: To indicate that the aggregation has restarted for 1144 this flow due to timeout 1145 1146 Set to zero in chips not supporting FISA 1147 <legal all> 1148 */ 1149 1150 #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 1151 #define RX_MSDU_END_FISA_TIMEOUT_LSB 41 1152 #define RX_MSDU_END_FISA_TIMEOUT_MSB 41 1153 #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 1154 1155 1156 /* Description TCP_UDP_CHKSUM_FAIL_COPY 1157 1158 if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, 1159 tcp_udp_chksum_fail from 'RX_ATTENTION' will be reported 1160 here: 1161 Indicates that the computed checksum (tcp_udp_chksum) did 1162 not match the checksum in the TCP/UDP header. 1163 */ 1164 1165 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 1166 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 1167 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 1168 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 1169 1170 1171 /* Description MSDU_LIMIT_ERROR 1172 1173 Indicates that the MSDU threshold was exceeded and thus 1174 all the rest of the MSDUs will not be scattered and will 1175 not be decapsulated but will be DMA'ed in RAW format as 1176 a single MSDU buffer 1177 */ 1178 1179 #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 1180 #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 1181 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 1182 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 1183 1184 1185 /* Description FLOW_IDX_TIMEOUT 1186 1187 Indicates an unsuccessful flow search due to the expiring 1188 of the search timer. 1189 <legal all> 1190 */ 1191 1192 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 1193 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 1194 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 1195 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 1196 1197 1198 /* Description FLOW_IDX_INVALID 1199 1200 flow id is not valid 1201 <legal all> 1202 */ 1203 1204 #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 1205 #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 1206 #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 1207 #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 1208 1209 1210 /* Description CCE_MATCH 1211 1212 Indicates that this status has a corresponding MSDU that 1213 requires FW processing. The OLE will have classification 1214 ring mask registers which will indicate the ring(s) for 1215 packets and descriptors which need FW attention. 1216 */ 1217 1218 #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 1219 #define RX_MSDU_END_CCE_MATCH_LSB 46 1220 #define RX_MSDU_END_CCE_MATCH_MSB 46 1221 #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 1222 1223 1224 /* Description AMSDU_PARSER_ERROR 1225 1226 A-MSDU could not be properly de-agregated. 1227 <legal all> 1228 */ 1229 1230 #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 1231 #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 1232 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 1233 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 1234 1235 1236 /* Description CUMULATIVE_IP_LENGTH 1237 1238 FISA: Total MSDU length that is part of this flow aggregated 1239 so far 1240 1241 Set to zero in chips not supporting FISA 1242 <legal all> 1243 */ 1244 1245 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 1246 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 1247 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 1248 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 1249 1250 1251 /* Description KEY_ID_OCTET 1252 1253 The key ID octet from the IV. Only valid when first_msdu 1254 is set. 1255 */ 1256 1257 #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 1258 #define RX_MSDU_END_KEY_ID_OCTET_LSB 0 1259 #define RX_MSDU_END_KEY_ID_OCTET_MSB 7 1260 #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff 1261 1262 1263 1264 #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 1265 #define RX_MSDU_END_RESERVED_16A_LSB 8 1266 #define RX_MSDU_END_RESERVED_16A_MSB 31 1267 #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 1268 1269 1270 /* Description RESERVED_17A 1271 1272 <legal 0> 1273 */ 1274 1275 #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 1276 #define RX_MSDU_END_RESERVED_17A_LSB 32 1277 #define RX_MSDU_END_RESERVED_17A_MSB 37 1278 #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 1279 1280 1281 /* Description SERVICE_CODE 1282 1283 Opaque service code between PPE and Wi-Fi 1284 1285 This field gets passed on by REO to PPE in the EDMA descriptor 1286 ('REO_TO_PPE_RING'). 1287 1288 <legal all> 1289 */ 1290 1291 #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 1292 #define RX_MSDU_END_SERVICE_CODE_LSB 38 1293 #define RX_MSDU_END_SERVICE_CODE_MSB 46 1294 #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 1295 1296 1297 /* Description PRIORITY_VALID 1298 1299 This field gets passed on by REO to PPE in the EDMA descriptor 1300 ('REO_TO_PPE_RING'). 1301 1302 <legal all> 1303 */ 1304 1305 #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 1306 #define RX_MSDU_END_PRIORITY_VALID_LSB 47 1307 #define RX_MSDU_END_PRIORITY_VALID_MSB 47 1308 #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 1309 1310 1311 /* Description INTRA_BSS 1312 1313 This packet needs intra-BSS routing by SW as the 'vdev_id' 1314 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 1315 that this MSDU was got in. 1316 1317 <legal all> 1318 */ 1319 1320 #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 1321 #define RX_MSDU_END_INTRA_BSS_LSB 48 1322 #define RX_MSDU_END_INTRA_BSS_MSB 48 1323 #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 1324 1325 1326 /* Description DEST_CHIP_ID 1327 1328 If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' 1329 to support intra-BSS routing with multi-chip multi-link 1330 operation. 1331 1332 This indicates into which chip's TCL the packet should be 1333 queued. 1334 1335 <legal all> 1336 */ 1337 1338 #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 1339 #define RX_MSDU_END_DEST_CHIP_ID_LSB 49 1340 #define RX_MSDU_END_DEST_CHIP_ID_MSB 50 1341 #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 1342 1343 1344 /* Description MULTICAST_ECHO 1345 1346 If set, this packet is a multicast echo, i.e. the DA is 1347 multicast and Rx OLE SA search with mcast_echo_check = 1 1348 passed. RXDMA should release such packets to WBM. 1349 1350 <legal all> 1351 */ 1352 1353 #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 1354 #define RX_MSDU_END_MULTICAST_ECHO_LSB 51 1355 #define RX_MSDU_END_MULTICAST_ECHO_MSB 51 1356 #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 1357 1358 1359 /* Description WDS_LEARNING_EVENT 1360 1361 If set, this packet has an SA search failure with WDS learning 1362 enabled for the peer. RXOLE should route this TLV to the 1363 RXDMA0 status ring to notify FW. 1364 1365 <legal all> 1366 */ 1367 1368 #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 1369 #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 1370 #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 1371 #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 1372 1373 1374 /* Description WDS_ROAMING_EVENT 1375 1376 If set, this packet's SA 'Sw_peer_id' mismatches the 'Sw_peer_id' 1377 of the peer through which the packet was got, indicating 1378 the SA node has roamed. RXOLE should route this TLV to 1379 the RXDMA0 status ring to notify FW. 1380 1381 <legal all> 1382 */ 1383 1384 #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 1385 #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 1386 #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 1387 #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 1388 1389 1390 /* Description WDS_KEEP_ALIVE_EVENT 1391 1392 If set, the AST timestamp for this packet's SA is older 1393 than the current timestamp by more than a threshold programmed 1394 in RXOLE. RXOLE should route this TLV to the RXDMA0 status 1395 ring to notify FW to keep the AST entry for the SA alive. 1396 1397 1398 <legal all> 1399 */ 1400 1401 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 1402 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 1403 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 1404 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 1405 1406 1407 /* Description DEST_CHIP_PMAC_ID 1408 1409 If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' 1410 to support intra-BSS routing with multi-chip multi-link 1411 operation. 1412 1413 This indicates into which link/'vdev' the packet should 1414 be queued in TCL. 1415 1416 <legal all> 1417 */ 1418 1419 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_OFFSET 0x0000000000000040 1420 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_LSB 55 1421 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MSB 55 1422 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MASK 0x0080000000000000 1423 1424 1425 /* Description RESERVED_17B 1426 1427 <legal 0> 1428 */ 1429 1430 #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 1431 #define RX_MSDU_END_RESERVED_17B_LSB 56 1432 #define RX_MSDU_END_RESERVED_17B_MSB 63 1433 #define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 1434 1435 1436 /* Description MSDU_LENGTH 1437 1438 MSDU length in bytes after decapsulation. 1439 1440 This field is still valid for MPDU frames without A-MSDU. 1441 It still represents MSDU length after decapsulation 1442 */ 1443 1444 #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 1445 #define RX_MSDU_END_MSDU_LENGTH_LSB 0 1446 #define RX_MSDU_END_MSDU_LENGTH_MSB 13 1447 #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff 1448 1449 1450 /* Description STBC 1451 1452 When set, use STBC transmission rates 1453 */ 1454 1455 #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 1456 #define RX_MSDU_END_STBC_LSB 14 1457 #define RX_MSDU_END_STBC_MSB 14 1458 #define RX_MSDU_END_STBC_MASK 0x0000000000004000 1459 1460 1461 /* Description IPSEC_ESP 1462 1463 Set if IPv4/v6 packet is using IPsec ESP 1464 */ 1465 1466 #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 1467 #define RX_MSDU_END_IPSEC_ESP_LSB 15 1468 #define RX_MSDU_END_IPSEC_ESP_MSB 15 1469 #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 1470 1471 1472 /* Description L3_OFFSET 1473 1474 Depending upon mode bit, this field either indicates the 1475 L3 offset in bytes from the start of the RX_HEADER or the 1476 IP offset in bytes from the start of the packet after decapsulation. 1477 The latter is only valid if ipv4_proto or ipv6_proto is 1478 set. 1479 */ 1480 1481 #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 1482 #define RX_MSDU_END_L3_OFFSET_LSB 16 1483 #define RX_MSDU_END_L3_OFFSET_MSB 22 1484 #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 1485 1486 1487 /* Description IPSEC_AH 1488 1489 Set if IPv4/v6 packet is using IPsec AH 1490 */ 1491 1492 #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 1493 #define RX_MSDU_END_IPSEC_AH_LSB 23 1494 #define RX_MSDU_END_IPSEC_AH_MSB 23 1495 #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 1496 1497 1498 /* Description L4_OFFSET 1499 1500 Depending upon mode bit, this field either indicates the 1501 L4 offset nin bytes from the start of RX_HEADER(only valid 1502 if either ipv4_proto or ipv6_proto is set to 1) or indicates 1503 the offset in bytes to the start of TCP or UDP header from 1504 the start of the IP header after decapsulation(Only valid 1505 if tcp_proto or udp_proto is set). The value 0 indicates 1506 that the offset is longer than 127 bytes. 1507 */ 1508 1509 #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 1510 #define RX_MSDU_END_L4_OFFSET_LSB 24 1511 #define RX_MSDU_END_L4_OFFSET_MSB 31 1512 #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 1513 1514 1515 /* Description MSDU_NUMBER 1516 1517 Indicates the MSDU number within a MPDU. This value is 1518 reset to zero at the start of each MPDU. If the number 1519 of MSDU exceeds 255 this number will wrap using modulo 256. 1520 1521 */ 1522 1523 #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 1524 #define RX_MSDU_END_MSDU_NUMBER_LSB 32 1525 #define RX_MSDU_END_MSDU_NUMBER_MSB 39 1526 #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 1527 1528 1529 /* Description DECAP_FORMAT 1530 1531 Indicates the format after decapsulation: 1532 1533 <enum 0 RAW> No encapsulation 1534 <enum 1 Native_WiFi> 1535 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1536 1537 <enum 3 802_3> Indicate Ethernet 1538 1539 <legal all> 1540 */ 1541 1542 #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 1543 #define RX_MSDU_END_DECAP_FORMAT_LSB 40 1544 #define RX_MSDU_END_DECAP_FORMAT_MSB 41 1545 #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 1546 1547 1548 /* Description IPV4_PROTO 1549 1550 Set if L2 layer indicates IPv4 protocol. 1551 */ 1552 1553 #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 1554 #define RX_MSDU_END_IPV4_PROTO_LSB 42 1555 #define RX_MSDU_END_IPV4_PROTO_MSB 42 1556 #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 1557 1558 1559 /* Description IPV6_PROTO 1560 1561 Set if L2 layer indicates IPv6 protocol. 1562 */ 1563 1564 #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 1565 #define RX_MSDU_END_IPV6_PROTO_LSB 43 1566 #define RX_MSDU_END_IPV6_PROTO_MSB 43 1567 #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 1568 1569 1570 /* Description TCP_PROTO 1571 1572 Set if the ipv4_proto or ipv6_proto are set and the IP protocol 1573 indicates TCP. 1574 */ 1575 1576 #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 1577 #define RX_MSDU_END_TCP_PROTO_LSB 44 1578 #define RX_MSDU_END_TCP_PROTO_MSB 44 1579 #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 1580 1581 1582 /* Description UDP_PROTO 1583 1584 Set if the ipv4_proto or ipv6_proto are set and the IP protocol 1585 indicates UDP. 1586 */ 1587 1588 #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 1589 #define RX_MSDU_END_UDP_PROTO_LSB 45 1590 #define RX_MSDU_END_UDP_PROTO_MSB 45 1591 #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 1592 1593 1594 /* Description IP_FRAG 1595 1596 Indicates that either the IP More frag bit is set or IP 1597 frag number is non-zero. If set indicates that this is 1598 a fragmented IP packet. 1599 */ 1600 1601 #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 1602 #define RX_MSDU_END_IP_FRAG_LSB 46 1603 #define RX_MSDU_END_IP_FRAG_MSB 46 1604 #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 1605 1606 1607 /* Description TCP_ONLY_ACK 1608 1609 Set if only the TCP Ack bit is set in the TCP flags and 1610 if the TCP payload is 0. 1611 */ 1612 1613 #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 1614 #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 1615 #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 1616 #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 1617 1618 1619 /* Description DA_IS_BCAST_MCAST 1620 1621 The destination address is broadcast or multicast. 1622 */ 1623 1624 #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 1625 #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 1626 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 1627 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 1628 1629 1630 /* Description TOEPLITZ_HASH_SEL 1631 1632 Actual choosen Hash. 1633 1634 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination 1635 address)1 -> Toeplitz hash of 4-tuple (IP source address, 1636 IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) 1637 destination port) 1638 2 -> Toeplitz of flow_id 1639 3 -> "Zero" is used 1640 <legal all> 1641 */ 1642 1643 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 1644 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 1645 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 1646 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 1647 1648 1649 /* Description IP_FIXED_HEADER_VALID 1650 1651 Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed 1652 fully within first 256 bytes of the packet 1653 */ 1654 1655 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 1656 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 1657 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 1658 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 1659 1660 1661 /* Description IP_EXTN_HEADER_VALID 1662 1663 IPv6/IPv6 header, including IPv4 options and recognizable 1664 extension headers parsed fully within first 256 bytes of 1665 the packet 1666 */ 1667 1668 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 1669 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 1670 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 1671 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 1672 1673 1674 /* Description TCP_UDP_HEADER_VALID 1675 1676 Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP 1677 header parsed fully within first 256 bytes of the packet 1678 1679 */ 1680 1681 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 1682 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 1683 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 1684 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 1685 1686 1687 /* Description MESH_CONTROL_PRESENT 1688 1689 When set, this MSDU includes the 'Mesh Control' field 1690 <legal all> 1691 */ 1692 1693 #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 1694 #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 1695 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 1696 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 1697 1698 1699 /* Description LDPC 1700 1701 When set, indicates that LDPC coding was used. 1702 <legal all> 1703 */ 1704 1705 #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 1706 #define RX_MSDU_END_LDPC_LSB 55 1707 #define RX_MSDU_END_LDPC_MSB 55 1708 #define RX_MSDU_END_LDPC_MASK 0x0080000000000000 1709 1710 1711 /* Description IP4_PROTOCOL_IP6_NEXT_HEADER 1712 1713 For IPv4 this is the 8 bit protocol field (when ipv4_proto 1714 is set). For IPv6 this is the 8 bit next_header field (when 1715 ipv6_proto is set). 1716 */ 1717 1718 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 1719 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 1720 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 1721 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 1722 1723 1724 1725 #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 1726 #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 1727 #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 1728 #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff 1729 1730 1731 1732 #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 1733 #define RX_MSDU_END_VLAN_STAG_CI_LSB 16 1734 #define RX_MSDU_END_VLAN_STAG_CI_MSB 31 1735 #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 1736 1737 1738 #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 1739 #define RX_MSDU_END_PEER_META_DATA_LSB 32 1740 #define RX_MSDU_END_PEER_META_DATA_MSB 63 1741 #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 1742 1743 1744 /* Description USER_RSSI 1745 1746 RSSI for this user 1747 <legal all> 1748 */ 1749 1750 #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 1751 #define RX_MSDU_END_USER_RSSI_LSB 0 1752 #define RX_MSDU_END_USER_RSSI_MSB 7 1753 #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff 1754 1755 1756 /* Description PKT_TYPE 1757 1758 Packet type: 1759 <enum 0 dot11a>802.11a PPDU type 1760 <enum 1 dot11b>802.11b PPDU type 1761 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 1762 <enum 3 dot11ac>802.11ac PPDU type 1763 <enum 4 dot11ax>802.11ax PPDU type 1764 <enum 5 dot11ba>802.11ba (WUR) PPDU type 1765 <enum 6 dot11be>802.11be PPDU type 1766 <enum 7 dot11az>802.11az (ranging) PPDU type 1767 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 1768 & aborted) 1769 */ 1770 1771 #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 1772 #define RX_MSDU_END_PKT_TYPE_LSB 8 1773 #define RX_MSDU_END_PKT_TYPE_MSB 11 1774 #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 1775 1776 1777 /* Description SGI 1778 1779 Field only valid when pkt type is HT, VHT or HE. 1780 1781 <enum 0 0_8_us_sgi > Legacy normal GI. Can also be used 1782 for HE 1783 <enum 1 0_4_us_sgi > Legacy short GI. Can also be used 1784 for HE 1785 <enum 2 1_6_us_sgi > HE related GI 1786 <enum 3 3_2_us_sgi > HE related GI 1787 <legal 0 - 3> 1788 */ 1789 1790 #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 1791 #define RX_MSDU_END_SGI_LSB 12 1792 #define RX_MSDU_END_SGI_MSB 13 1793 #define RX_MSDU_END_SGI_MASK 0x0000000000003000 1794 1795 1796 /* Description RATE_MCS 1797 1798 For details, refer to MCS_TYPE description 1799 Note: This is "rate" in case of 11a/11b 1800 1801 <legal all> 1802 */ 1803 1804 #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 1805 #define RX_MSDU_END_RATE_MCS_LSB 14 1806 #define RX_MSDU_END_RATE_MCS_MSB 17 1807 #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 1808 1809 1810 /* Description RECEIVE_BANDWIDTH 1811 1812 Full receive Bandwidth 1813 1814 <enum 0 20_mhz>20 Mhz BW 1815 <enum 1 40_mhz>40 Mhz BW 1816 <enum 2 80_mhz>80 Mhz BW 1817 <enum 3 160_mhz>160 Mhz BW 1818 <enum 4 320_mhz>320 Mhz BW 1819 <enum 5 240_mhz>240 Mhz BW 1820 */ 1821 1822 #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 1823 #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 1824 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 1825 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 1826 1827 1828 #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 1829 #define RX_MSDU_END_RECEPTION_TYPE_LSB 21 1830 #define RX_MSDU_END_RECEPTION_TYPE_MSB 23 1831 #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 1832 1833 1834 /* Description MIMO_SS_BITMAP 1835 1836 Field only valid when Reception_type for the MPDU from this 1837 STA is some form of MIMO reception 1838 1839 Bitmap, with each bit indicating if the related spatial 1840 stream is used for this STA 1841 LSB related to SS 0 1842 1843 0: spatial stream not used for this reception 1844 1: spatial stream used for this reception 1845 1846 Note: Only 7 bits are reported here to accommodate field 1847 'msdu_done_copy.' 1848 <legal all> 1849 */ 1850 1851 #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 1852 #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 1853 #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 1854 #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 1855 1856 1857 /* Description MSDU_DONE_COPY 1858 1859 If set indicates that the RX packet data, RX header data, 1860 RX PPDU start descriptor, RX MPDU start/end descriptor, 1861 RX MSDU start/end descriptors and RX Attention descriptor 1862 are all valid. 1863 1864 <legal 1> 1865 */ 1866 1867 #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 1868 #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 1869 #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 1870 #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 1871 1872 1873 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 1874 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 1875 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 1876 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 1877 1878 1879 /* Description PPDU_START_TIMESTAMP_63_32 1880 1881 Timestamp that indicates when the PPDU that contained this 1882 MPDU started on the medium, upper 32 bits 1883 <legal all> 1884 */ 1885 1886 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 1887 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 1888 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 1889 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff 1890 1891 1892 /* Description SW_PHY_META_DATA 1893 1894 SW programmed Meta data provided by the PHY. 1895 1896 Can be used for SW to indicate the channel the device is 1897 on. 1898 <legal all> 1899 */ 1900 1901 #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 1902 #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 1903 #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 1904 #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 1905 1906 1907 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 1908 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 1909 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 1910 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 1911 1912 1913 /* Description TOEPLITZ_HASH_2_OR_4 1914 1915 Controlled by multiple RxOLE registers for TCP/UDP over 1916 IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple 1917 IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz 1918 hash computed over 4-tuple IPv4 or IPv6 src/dest addresses 1919 and src/dest ports is reported. The Flow_id_toeplitz hash 1920 can also be reported here. Usually the hash reported here 1921 is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy 1922 in 'RXPT_CLASSIFY_INFO'). 1923 1924 Optionally the 3-tuple Toeplitz hash over IPv4 1925 or IPv6 src/dest addresses and L4 protocol can be reported 1926 */ 1927 1928 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 1929 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 1930 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 1931 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 1932 1933 1934 /* Description RESERVED_28A 1935 1936 <legal 0> 1937 */ 1938 1939 #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 1940 #define RX_MSDU_END_RESERVED_28A_LSB 0 1941 #define RX_MSDU_END_RESERVED_28A_MSB 15 1942 #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff 1943 1944 1945 /* Description SA_15_0 1946 1947 Source MAC address bits [15:0] (with the fifth byte in the 1948 MSB and the last byte in the LSB, i.e. requiring a byte-swap 1949 for little-endian FW) 1950 */ 1951 1952 #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 1953 #define RX_MSDU_END_SA_15_0_LSB 16 1954 #define RX_MSDU_END_SA_15_0_MSB 31 1955 #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 1956 1957 1958 /* Description SA_47_16 1959 1960 Source MAC address bits [47:16] (with the first byte in 1961 the MSB and the fourth byte in the LSB, i.e. requiring a 1962 byte-swap for little-endian FW) 1963 */ 1964 1965 #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 1966 #define RX_MSDU_END_SA_47_16_LSB 32 1967 #define RX_MSDU_END_SA_47_16_MSB 63 1968 #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 1969 1970 1971 #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 1972 #define RX_MSDU_END_FIRST_MPDU_LSB 0 1973 #define RX_MSDU_END_FIRST_MPDU_MSB 0 1974 #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 1975 1976 1977 /* Description RESERVED_30A 1978 1979 <legal 0> 1980 */ 1981 1982 #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 1983 #define RX_MSDU_END_RESERVED_30A_LSB 1 1984 #define RX_MSDU_END_RESERVED_30A_MSB 1 1985 #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 1986 1987 1988 /* Description MCAST_BCAST 1989 1990 Multicast / broadcast indicator. Only set when the MAC 1991 address 1 bit 0 is set indicating mcast/bcast and the BSSID 1992 matches one of the 4 BSSID registers. Only set when first_msdu 1993 is set. 1994 */ 1995 1996 #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 1997 #define RX_MSDU_END_MCAST_BCAST_LSB 2 1998 #define RX_MSDU_END_MCAST_BCAST_MSB 2 1999 #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 2000 2001 2002 /* Description AST_INDEX_NOT_FOUND 2003 2004 Only valid when first_msdu is set. 2005 2006 Indicates no AST matching entries within the the max search 2007 count. 2008 */ 2009 2010 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 2011 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 2012 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 2013 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 2014 2015 2016 /* Description AST_INDEX_TIMEOUT 2017 2018 Only valid when first_msdu is set. 2019 2020 Indicates an unsuccessful search in the address seach table 2021 due to timeout. 2022 */ 2023 2024 #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 2025 #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 2026 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 2027 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 2028 2029 2030 /* Description POWER_MGMT 2031 2032 Power management bit set in the 802.11 header. Only set 2033 when first_msdu is set. 2034 */ 2035 2036 #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 2037 #define RX_MSDU_END_POWER_MGMT_LSB 5 2038 #define RX_MSDU_END_POWER_MGMT_MSB 5 2039 #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 2040 2041 2042 /* Description NON_QOS 2043 2044 Set if packet is not a non-QoS data frame. Only set when 2045 first_msdu is set. 2046 */ 2047 2048 #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 2049 #define RX_MSDU_END_NON_QOS_LSB 6 2050 #define RX_MSDU_END_NON_QOS_MSB 6 2051 #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 2052 2053 2054 /* Description NULL_DATA 2055 2056 Set if frame type indicates either null data or QoS null 2057 data format. Only set when first_msdu is set. 2058 */ 2059 2060 #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 2061 #define RX_MSDU_END_NULL_DATA_LSB 7 2062 #define RX_MSDU_END_NULL_DATA_MSB 7 2063 #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 2064 2065 2066 /* Description MGMT_TYPE 2067 2068 Set if packet is a management packet. Only set when first_msdu 2069 is set. 2070 */ 2071 2072 #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 2073 #define RX_MSDU_END_MGMT_TYPE_LSB 8 2074 #define RX_MSDU_END_MGMT_TYPE_MSB 8 2075 #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 2076 2077 2078 /* Description CTRL_TYPE 2079 2080 Set if packet is a control packet. Only set when first_msdu 2081 is set. 2082 */ 2083 2084 #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 2085 #define RX_MSDU_END_CTRL_TYPE_LSB 9 2086 #define RX_MSDU_END_CTRL_TYPE_MSB 9 2087 #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 2088 2089 2090 /* Description MORE_DATA 2091 2092 Set if more bit in frame control is set. Only set when 2093 first_msdu is set. 2094 */ 2095 2096 #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 2097 #define RX_MSDU_END_MORE_DATA_LSB 10 2098 #define RX_MSDU_END_MORE_DATA_MSB 10 2099 #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 2100 2101 2102 /* Description EOSP 2103 2104 Set if the EOSP (end of service period) bit in the QoS control 2105 field is set. Only set when first_msdu is set. 2106 */ 2107 2108 #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 2109 #define RX_MSDU_END_EOSP_LSB 11 2110 #define RX_MSDU_END_EOSP_MSB 11 2111 #define RX_MSDU_END_EOSP_MASK 0x0000000000000800 2112 2113 2114 /* Description A_MSDU_ERROR 2115 2116 Set if number of MSDUs in A-MSDU is above a threshold or 2117 if the size of the MSDU is invalid. This receive buffer 2118 will contain all of the remainder of the MSDUs in this 2119 MPDU without decapsulation. 2120 */ 2121 2122 #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 2123 #define RX_MSDU_END_A_MSDU_ERROR_LSB 12 2124 #define RX_MSDU_END_A_MSDU_ERROR_MSB 12 2125 #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 2126 2127 2128 #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 2129 #define RX_MSDU_END_RESERVED_30B_LSB 13 2130 #define RX_MSDU_END_RESERVED_30B_MSB 13 2131 #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 2132 2133 2134 /* Description ORDER 2135 2136 Set if the order bit in the frame control is set. Only 2137 set when first_msdu is set. 2138 */ 2139 2140 #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 2141 #define RX_MSDU_END_ORDER_LSB 14 2142 #define RX_MSDU_END_ORDER_MSB 14 2143 #define RX_MSDU_END_ORDER_MASK 0x0000000000004000 2144 2145 2146 /* Description WIFI_PARSER_ERROR 2147 2148 Indicates that the WiFi frame has one of the following errors 2149 2150 o has less than minimum allowed bytes as per standard 2151 o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) 2152 <legal all> 2153 */ 2154 2155 #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 2156 #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 2157 #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 2158 #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 2159 2160 2161 /* Description OVERFLOW_ERR 2162 2163 RXPCU Receive FIFO ran out of space to receive the full 2164 MPDU. Therefor this MPDU is terminated early and is thus 2165 corrupted. 2166 2167 This MPDU will not be ACKed. 2168 RXPCU might still be able to correctly receive the following 2169 MPDUs in the PPDU if enough fifo space became available 2170 in time 2171 */ 2172 2173 #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 2174 #define RX_MSDU_END_OVERFLOW_ERR_LSB 16 2175 #define RX_MSDU_END_OVERFLOW_ERR_MSB 16 2176 #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 2177 2178 2179 /* Description MSDU_LENGTH_ERR 2180 2181 Indicates that the MSDU length from the 802.3 encapsulated 2182 length field extends beyond the MPDU boundary or if the 2183 length is less than 14 bytes. 2184 Merged with original "other_msdu_err": Indicates that the 2185 MSDU threshold was exceeded and thus all the rest of the 2186 MSDUs will not be scattered and will not be decasulated 2187 but will be DMA'ed in RAW format as a single MSDU buffer 2188 2189 */ 2190 2191 #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 2192 #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 2193 #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 2194 #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 2195 2196 2197 /* Description TCP_UDP_CHKSUM_FAIL 2198 2199 Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') 2200 did not match the checksum in the TCP/UDP header. 2201 */ 2202 2203 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 2204 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 2205 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 2206 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 2207 2208 2209 /* Description IP_CHKSUM_FAIL 2210 2211 Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') 2212 did not match the checksum in the IP header. 2213 */ 2214 2215 #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 2216 #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 2217 #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 2218 #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 2219 2220 2221 /* Description SA_IDX_INVALID 2222 2223 Indicates no matching entry was found in the address search 2224 table for the source MAC address. 2225 */ 2226 2227 #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 2228 #define RX_MSDU_END_SA_IDX_INVALID_LSB 20 2229 #define RX_MSDU_END_SA_IDX_INVALID_MSB 20 2230 #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 2231 2232 2233 /* Description DA_IDX_INVALID 2234 2235 Indicates no matching entry was found in the address search 2236 table for the destination MAC address. 2237 */ 2238 2239 #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 2240 #define RX_MSDU_END_DA_IDX_INVALID_LSB 21 2241 #define RX_MSDU_END_DA_IDX_INVALID_MSB 21 2242 #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 2243 2244 2245 /* Description AMSDU_ADDR_MISMATCH 2246 2247 Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching 2248 TA or an A-MDU with 'to DS = 0' had a DA mismatching RA 2249 2250 */ 2251 2252 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 2253 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 2254 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 2255 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 2256 2257 2258 /* Description RX_IN_TX_DECRYPT_BYP 2259 2260 Indicates that RX packet is not decrypted as Crypto is busy 2261 with TX packet processing. 2262 */ 2263 2264 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 2265 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 2266 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 2267 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 2268 2269 2270 /* Description ENCRYPT_REQUIRED 2271 2272 Indicates that this data type frame is not encrypted even 2273 if the policy for this MPDU requires encryption as indicated 2274 in the peer entry key type. 2275 */ 2276 2277 #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 2278 #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 2279 #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 2280 #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 2281 2282 2283 /* Description DIRECTED 2284 2285 MPDU is a directed packet which means that the RA matched 2286 our STA addresses. In proxySTA it means that the TA matched 2287 an entry in our address search table with the corresponding 2288 "no_ack" bit is the address search entry cleared. 2289 */ 2290 2291 #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 2292 #define RX_MSDU_END_DIRECTED_LSB 25 2293 #define RX_MSDU_END_DIRECTED_MSB 25 2294 #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 2295 2296 2297 /* Description BUFFER_FRAGMENT 2298 2299 Indicates that at least one of the rx buffers has been fragmented. 2300 If set the FW should look at the rx_frag_info descriptor 2301 described below. 2302 */ 2303 2304 #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 2305 #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 2306 #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 2307 #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 2308 2309 2310 /* Description MPDU_LENGTH_ERR 2311 2312 Indicates that the MPDU was pre-maturely terminated resulting 2313 in a truncated MPDU. Don't trust the MPDU length field. 2314 2315 */ 2316 2317 #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 2318 #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 2319 #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 2320 #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 2321 2322 2323 /* Description TKIP_MIC_ERR 2324 2325 Indicates that the MPDU Michael integrity check failed 2326 */ 2327 2328 #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 2329 #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 2330 #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 2331 #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 2332 2333 2334 /* Description DECRYPT_ERR 2335 2336 Indicates that the MPDU decrypt integrity check failed or 2337 CRYPTO received an encrypted frame, but did not get a valid 2338 corresponding key id in the peer entry. 2339 */ 2340 2341 #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 2342 #define RX_MSDU_END_DECRYPT_ERR_LSB 29 2343 #define RX_MSDU_END_DECRYPT_ERR_MSB 29 2344 #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 2345 2346 2347 /* Description UNENCRYPTED_FRAME_ERR 2348 2349 Copied here by RX OLE from the RX_MPDU_END TLV 2350 */ 2351 2352 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 2353 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 2354 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 2355 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 2356 2357 2358 /* Description FCS_ERR 2359 2360 Indicates that the MPDU FCS check failed 2361 */ 2362 2363 #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 2364 #define RX_MSDU_END_FCS_ERR_LSB 31 2365 #define RX_MSDU_END_FCS_ERR_MSB 31 2366 #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 2367 2368 2369 /* Description RESERVED_31A 2370 2371 <legal 0> 2372 */ 2373 2374 #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 2375 #define RX_MSDU_END_RESERVED_31A_LSB 32 2376 #define RX_MSDU_END_RESERVED_31A_MSB 41 2377 #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 2378 2379 2380 /* Description DECRYPT_STATUS_CODE 2381 2382 Field provides insight into the decryption performed 2383 2384 <enum 0 decrypt_ok> Frame had protection enabled and decrypted 2385 properly 2386 <enum 1 decrypt_unprotected_frame > Frame is unprotected 2387 and hence bypassed 2388 <enum 2 decrypt_data_err > Frame has protection enabled 2389 and could not be properly d ecrypted due to MIC/ICV mismatch 2390 etc. 2391 <enum 3 decrypt_key_invalid > Frame has protection enabled 2392 but the key that was required to decrypt this frame was 2393 not valid 2394 <enum 4 decrypt_peer_entry_invalid > Frame has protection 2395 enabled but the key that was required to decrypt this frame 2396 was not valid 2397 <enum 5 decrypt_other > Reserved for other indications 2398 2399 <legal 0 - 5> 2400 */ 2401 2402 #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 2403 #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 2404 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 2405 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 2406 2407 2408 /* Description RX_BITMAP_NOT_UPDATED 2409 2410 Frame is received, but RXPCU could not update the receive 2411 bitmap due to (temporary) fifo contraints. 2412 <legal all> 2413 */ 2414 2415 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 2416 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 2417 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 2418 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 2419 2420 2421 /* Description RESERVED_31B 2422 2423 <legal 0> 2424 */ 2425 2426 #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 2427 #define RX_MSDU_END_RESERVED_31B_LSB 46 2428 #define RX_MSDU_END_RESERVED_31B_MSB 62 2429 #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 2430 2431 2432 #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 2433 #define RX_MSDU_END_MSDU_DONE_LSB 63 2434 #define RX_MSDU_END_MSDU_DONE_MSB 63 2435 #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 2436 2437 2438 2439 #endif // RX_MSDU_END 2440