1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_EXT_DESC_INFO_H_ 18 #define _RX_MSDU_EXT_DESC_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 23 24 25 struct rx_msdu_ext_desc_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t reo_destination_indication : 5, // [4:0] 28 service_code : 9, // [13:5] 29 priority_valid : 1, // [14:14] 30 data_offset : 12, // [26:15] 31 src_link_id : 3, // [29:27] 32 reserved_0a : 2; // [31:30] 33 #else 34 uint32_t reserved_0a : 2, // [31:30] 35 src_link_id : 3, // [29:27] 36 data_offset : 12, // [26:15] 37 priority_valid : 1, // [14:14] 38 service_code : 9, // [13:5] 39 reo_destination_indication : 5; // [4:0] 40 #endif 41 }; 42 43 44 /* Description REO_DESTINATION_INDICATION 45 46 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 47 multiple buffers, this field will be valid in the Last 48 buffer used by the MSDU 49 50 The ID of the REO exit ring where the MSDU frame shall push 51 after (MPDU level) reordering has finished. 52 53 <enum 0 reo_destination_sw0> Reo will push the frame into 54 the REO2SW0 ring 55 <enum 1 reo_destination_sw1> Reo will push the frame into 56 the REO2SW1 ring 57 <enum 2 reo_destination_sw2> Reo will push the frame into 58 the REO2SW2 ring 59 <enum 3 reo_destination_sw3> Reo will push the frame into 60 the REO2SW3 ring 61 <enum 4 reo_destination_sw4> Reo will push the frame into 62 the REO2SW4 ring 63 <enum 5 reo_destination_release> Reo will push the frame 64 into the REO_release ring 65 <enum 6 reo_destination_fw> Reo will push the frame into 66 the REO2FW ring 67 <enum 7 reo_destination_sw5> Reo will push the frame into 68 the REO2SW5 ring (REO remaps this in chips without REO2SW5 69 ring) 70 <enum 8 reo_destination_sw6> Reo will push the frame into 71 the REO2SW6 ring (REO remaps this in chips without REO2SW6 72 ring) 73 <enum 9 reo_destination_sw7> Reo will push the frame into 74 the REO2SW7 ring (REO remaps this in chips without REO2SW7 75 ring) 76 <enum 10 reo_destination_sw8> Reo will push the frame into 77 the REO2SW8 ring (REO remaps this in chips without REO2SW8 78 ring) 79 <enum 11 reo_destination_11> REO remaps this 80 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 81 REO remaps this 82 <enum 14 reo_destination_14> REO remaps this 83 <enum 15 reo_destination_15> REO remaps this 84 <enum 16 reo_destination_16> REO remaps this 85 <enum 17 reo_destination_17> REO remaps this 86 <enum 18 reo_destination_18> REO remaps this 87 <enum 19 reo_destination_19> REO remaps this 88 <enum 20 reo_destination_20> REO remaps this 89 <enum 21 reo_destination_21> REO remaps this 90 <enum 22 reo_destination_22> REO remaps this 91 <enum 23 reo_destination_23> REO remaps this 92 <enum 24 reo_destination_24> REO remaps this 93 <enum 25 reo_destination_25> REO remaps this 94 <enum 26 reo_destination_26> REO remaps this 95 <enum 27 reo_destination_27> REO remaps this 96 <enum 28 reo_destination_28> REO remaps this 97 <enum 29 reo_destination_29> REO remaps this 98 <enum 30 reo_destination_30> REO remaps this 99 <enum 31 reo_destination_31> REO remaps this 100 101 <legal all> 102 */ 103 104 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 105 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 106 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 107 #define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f 108 109 110 /* Description SERVICE_CODE 111 112 Opaque service code between PPE and Wi-Fi 113 114 This field gets passed on by REO to PPE in the EDMA descriptor 115 ('REO_TO_PPE_RING'). 116 117 <legal all> 118 */ 119 120 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 121 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 122 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 123 #define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 124 125 126 /* Description PRIORITY_VALID 127 128 This field gets passed on by REO to PPE in the EDMA descriptor 129 ('REO_TO_PPE_RING'). 130 131 <legal all> 132 */ 133 134 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 135 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 136 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 137 #define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 138 139 140 /* Description DATA_OFFSET 141 142 The offset to Rx packet data within the buffer (including 143 Rx DMA offset programming and L3 header padding inserted 144 by Rx OLE). 145 146 This field gets passed on by REO to PPE in the EDMA descriptor 147 ('REO_TO_PPE_RING'). 148 149 <legal all> 150 */ 151 152 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 153 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 154 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 155 #define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 156 157 158 /* Description SRC_LINK_ID 159 160 Consumer: SW 161 Producer: RXDMA 162 163 Set to the link ID of the PMAC that received the frame 164 <legal all> 165 */ 166 167 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 168 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 169 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 170 #define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 171 172 173 /* Description RESERVED_0A 174 175 <legal 0> 176 */ 177 178 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 179 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 180 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 181 #define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 182 183 184 185 #endif // RX_MSDU_EXT_DESC_INFO 186