1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_LINK_H_ 18 #define _RX_MSDU_LINK_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #include "buffer_addr_info.h" 24 #include "rx_msdu_details.h" 25 #define NUM_OF_DWORDS_RX_MSDU_LINK 32 26 27 28 struct rx_msdu_link { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct uniform_descriptor_header descriptor_header; 31 struct buffer_addr_info next_msdu_link_desc_addr_info; 32 uint32_t receive_queue_number : 16, // [15:0] 33 first_rx_msdu_link_struct : 1, // [16:16] 34 reserved_3a : 15; // [31:17] 35 uint32_t pn_31_0 : 32; // [31:0] 36 uint32_t pn_63_32 : 32; // [31:0] 37 uint32_t pn_95_64 : 32; // [31:0] 38 uint32_t pn_127_96 : 32; // [31:0] 39 struct rx_msdu_details msdu_0; 40 struct rx_msdu_details msdu_1; 41 struct rx_msdu_details msdu_2; 42 struct rx_msdu_details msdu_3; 43 struct rx_msdu_details msdu_4; 44 struct rx_msdu_details msdu_5; 45 #else 46 struct uniform_descriptor_header descriptor_header; 47 struct buffer_addr_info next_msdu_link_desc_addr_info; 48 uint32_t reserved_3a : 15, // [31:17] 49 first_rx_msdu_link_struct : 1, // [16:16] 50 receive_queue_number : 16; // [15:0] 51 uint32_t pn_31_0 : 32; // [31:0] 52 uint32_t pn_63_32 : 32; // [31:0] 53 uint32_t pn_95_64 : 32; // [31:0] 54 uint32_t pn_127_96 : 32; // [31:0] 55 struct rx_msdu_details msdu_0; 56 struct rx_msdu_details msdu_1; 57 struct rx_msdu_details msdu_2; 58 struct rx_msdu_details msdu_3; 59 struct rx_msdu_details msdu_4; 60 struct rx_msdu_details msdu_5; 61 #endif 62 }; 63 64 65 /* Description DESCRIPTOR_HEADER 66 67 Details about which module owns this struct. 68 Note that sub field "Buffer_type" shall be set to "Receive_MSDU_Link_descriptor" 69 70 */ 71 72 73 /* Description OWNER 74 75 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 76 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 77 78 The owner of this data structure: 79 <enum 0 WBM_owned> Buffer Manager currently owns this data 80 structure. 81 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 82 data structure. 83 <enum 2 TQM_owned> Transmit Queue Manager currently owns 84 this data structure. 85 <enum 3 RXDMA_owned> Receive DMA currently owns this data 86 structure. 87 <enum 4 REO_owned> Reorder currently owns this data structure. 88 89 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 90 91 92 <legal 0-5> 93 */ 94 95 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 96 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 97 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 98 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 99 100 101 /* Description BUFFER_TYPE 102 103 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 104 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 105 106 Field describing what contents format is of this descriptor 107 108 109 <enum 0 Transmit_MSDU_Link_descriptor> 110 <enum 1 Transmit_MPDU_Link_descriptor> 111 <enum 2 Transmit_MPDU_Queue_head_descriptor> 112 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 113 <enum 4 Transmit_flow_descriptor> 114 <enum 5 Transmit_buffer> NOT TO BE USED: 115 116 <enum 6 Receive_MSDU_Link_descriptor> 117 <enum 7 Receive_MPDU_Link_descriptor> 118 <enum 8 Receive_REO_queue_descriptor> 119 <enum 9 Receive_REO_queue_1k_descriptor> 120 <enum 10 Receive_REO_queue_ext_descriptor> 121 122 <enum 11 Receive_buffer> 123 124 <enum 12 Idle_link_list_entry> 125 126 <legal 0-12> 127 */ 128 129 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 130 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 131 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 132 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 133 134 135 /* Description TX_MPDU_QUEUE_NUMBER 136 137 Consumer: TQM/Debug 138 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 139 140 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 141 142 143 Indicates the MPDU queue ID to which this MPDU descriptor 144 belongs 145 Used for tracking and debugging 146 147 <legal all> 148 */ 149 150 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 151 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 152 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 153 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 154 155 156 /* Description RESERVED_0A 157 158 <legal 0> 159 */ 160 161 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 162 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 163 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 164 #define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 165 166 167 /* Description NEXT_MSDU_LINK_DESC_ADDR_INFO 168 169 Details of the physical address of the next MSDU link descriptor 170 that contains info about additional MSDUs that are part 171 of this MPDU. 172 */ 173 174 175 /* Description BUFFER_ADDR_31_0 176 177 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 178 descriptor OR Link Descriptor 179 180 In case of 'NULL' pointer, this field is set to 0 181 <legal all> 182 */ 183 184 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 185 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 186 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 187 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 188 189 190 /* Description BUFFER_ADDR_39_32 191 192 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 193 descriptor OR Link Descriptor 194 195 In case of 'NULL' pointer, this field is set to 0 196 <legal all> 197 */ 198 199 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 200 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 201 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 202 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 203 204 205 /* Description RETURN_BUFFER_MANAGER 206 207 Consumer: WBM 208 Producer: SW/FW 209 210 In case of 'NULL' pointer, this field is set to 0 211 212 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 213 descriptor OR link descriptor that is being pointed to 214 shall be returned after the frame has been processed. It 215 is used by WBM for routing purposes. 216 217 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 218 to the WMB buffer idle list 219 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 220 to the WBM idle link descriptor idle list, where the chip 221 0 WBM is chosen in case of a multi-chip config 222 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 223 to the chip 1 WBM idle link descriptor idle list 224 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 225 to the chip 2 WBM idle link descriptor idle list 226 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 227 returned to chip 3 WBM idle link descriptor idle list 228 <enum 4 FW_BM> This buffer shall be returned to the FW 229 <enum 5 SW0_BM> This buffer shall be returned to the SW, 230 ring 0 231 <enum 6 SW1_BM> This buffer shall be returned to the SW, 232 ring 1 233 <enum 7 SW2_BM> This buffer shall be returned to the SW, 234 ring 2 235 <enum 8 SW3_BM> This buffer shall be returned to the SW, 236 ring 3 237 <enum 9 SW4_BM> This buffer shall be returned to the SW, 238 ring 4 239 <enum 10 SW5_BM> This buffer shall be returned to the SW, 240 ring 5 241 <enum 11 SW6_BM> This buffer shall be returned to the SW, 242 ring 6 243 244 <legal 0-12> 245 */ 246 247 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 248 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 249 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 250 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 251 252 253 /* Description SW_BUFFER_COOKIE 254 255 Cookie field exclusively used by SW. 256 257 In case of 'NULL' pointer, this field is set to 0 258 259 HW ignores the contents, accept that it passes the programmed 260 value on to other descriptors together with the physical 261 address 262 263 Field can be used by SW to for example associate the buffers 264 physical address with the virtual address 265 The bit definitions as used by SW are within SW HLD specification 266 267 268 NOTE1: 269 The three most significant bits can have a special meaning 270 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 271 and field transmit_bw_restriction is set 272 273 In case of NON punctured transmission: 274 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 275 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 276 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 277 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 278 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 279 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 280 Sw_buffer_cookie[19:18] = 2'b11: reserved 281 282 In case of punctured transmission: 283 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 284 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 285 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 286 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 287 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 288 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 289 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 290 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 291 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 292 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 293 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 294 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 295 Sw_buffer_cookie[19:18] = 2'b11: reserved 296 297 Note: a punctured transmission is indicated by the presence 298 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 299 300 <legal all> 301 */ 302 303 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 304 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 305 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 306 #define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 307 308 309 /* Description RECEIVE_QUEUE_NUMBER 310 311 Indicates the Receive queue to which this MPDU descriptor 312 belongs 313 Used for tracking, finding bugs and debugging. 314 <legal all> 315 */ 316 317 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 318 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 319 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 320 #define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 321 322 323 /* Description FIRST_RX_MSDU_LINK_STRUCT 324 325 When set, this RX_MSDU_link descriptor is the first one 326 in the MSDU link list. Field MSDU_0 points to the very first 327 MSDU buffer descriptor in the MPDU 328 <legal all> 329 */ 330 331 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c 332 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 333 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 334 #define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 335 336 337 /* Description RESERVED_3A 338 339 <legal 0> 340 */ 341 342 #define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c 343 #define RX_MSDU_LINK_RESERVED_3A_LSB 17 344 #define RX_MSDU_LINK_RESERVED_3A_MSB 31 345 #define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 346 347 348 /* Description PN_31_0 349 350 Field only valid when First_RX_MSDU_link_struct is set. 351 352 353 31-0 bits of the 256-bit packet number bitmap. 354 <legal all> 355 */ 356 357 #define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 358 #define RX_MSDU_LINK_PN_31_0_LSB 0 359 #define RX_MSDU_LINK_PN_31_0_MSB 31 360 #define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff 361 362 363 /* Description PN_63_32 364 365 Field only valid when First_RX_MSDU_link_struct is set. 366 367 368 63-32 bits of the 256-bit packet number bitmap. 369 <legal all> 370 */ 371 372 #define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 373 #define RX_MSDU_LINK_PN_63_32_LSB 0 374 #define RX_MSDU_LINK_PN_63_32_MSB 31 375 #define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff 376 377 378 /* Description PN_95_64 379 380 Field only valid when First_RX_MSDU_link_struct is set. 381 382 383 95-64 bits of the 256-bit packet number bitmap. 384 <legal all> 385 */ 386 387 #define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 388 #define RX_MSDU_LINK_PN_95_64_LSB 0 389 #define RX_MSDU_LINK_PN_95_64_MSB 31 390 #define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff 391 392 393 /* Description PN_127_96 394 395 Field only valid when First_RX_MSDU_link_struct is set. 396 397 398 127-96 bits of the 256-bit packet number bitmap. 399 <legal all> 400 */ 401 402 #define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c 403 #define RX_MSDU_LINK_PN_127_96_LSB 0 404 #define RX_MSDU_LINK_PN_127_96_MSB 31 405 #define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff 406 407 408 /* Description MSDU_0 409 410 When First_RX_MSDU_link_struct is set, this MSDU is the 411 first in the MPDU 412 413 When First_RX_MSDU_link_struct is NOT set, this MSDU follows 414 the last MSDU in the previous RX_MSDU_link data structure 415 416 */ 417 418 419 /* Description BUFFER_ADDR_INFO_DETAILS 420 421 Consumer: REO/SW 422 Producer: RXDMA 423 424 Details of the physical address of the buffer containing 425 an MSDU (or entire MPDU) 426 */ 427 428 429 /* Description BUFFER_ADDR_31_0 430 431 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 432 descriptor OR Link Descriptor 433 434 In case of 'NULL' pointer, this field is set to 0 435 <legal all> 436 */ 437 438 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 439 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 440 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 441 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 442 443 444 /* Description BUFFER_ADDR_39_32 445 446 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 447 descriptor OR Link Descriptor 448 449 In case of 'NULL' pointer, this field is set to 0 450 <legal all> 451 */ 452 453 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 454 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 455 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 456 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 457 458 459 /* Description RETURN_BUFFER_MANAGER 460 461 Consumer: WBM 462 Producer: SW/FW 463 464 In case of 'NULL' pointer, this field is set to 0 465 466 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 467 descriptor OR link descriptor that is being pointed to 468 shall be returned after the frame has been processed. It 469 is used by WBM for routing purposes. 470 471 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 472 to the WMB buffer idle list 473 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 474 to the WBM idle link descriptor idle list, where the chip 475 0 WBM is chosen in case of a multi-chip config 476 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 477 to the chip 1 WBM idle link descriptor idle list 478 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 479 to the chip 2 WBM idle link descriptor idle list 480 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 481 returned to chip 3 WBM idle link descriptor idle list 482 <enum 4 FW_BM> This buffer shall be returned to the FW 483 <enum 5 SW0_BM> This buffer shall be returned to the SW, 484 ring 0 485 <enum 6 SW1_BM> This buffer shall be returned to the SW, 486 ring 1 487 <enum 7 SW2_BM> This buffer shall be returned to the SW, 488 ring 2 489 <enum 8 SW3_BM> This buffer shall be returned to the SW, 490 ring 3 491 <enum 9 SW4_BM> This buffer shall be returned to the SW, 492 ring 4 493 <enum 10 SW5_BM> This buffer shall be returned to the SW, 494 ring 5 495 <enum 11 SW6_BM> This buffer shall be returned to the SW, 496 ring 6 497 498 <legal 0-12> 499 */ 500 501 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 502 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 503 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 504 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 505 506 507 /* Description SW_BUFFER_COOKIE 508 509 Cookie field exclusively used by SW. 510 511 In case of 'NULL' pointer, this field is set to 0 512 513 HW ignores the contents, accept that it passes the programmed 514 value on to other descriptors together with the physical 515 address 516 517 Field can be used by SW to for example associate the buffers 518 physical address with the virtual address 519 The bit definitions as used by SW are within SW HLD specification 520 521 522 NOTE1: 523 The three most significant bits can have a special meaning 524 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 525 and field transmit_bw_restriction is set 526 527 In case of NON punctured transmission: 528 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 529 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 530 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 531 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 532 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 533 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 534 Sw_buffer_cookie[19:18] = 2'b11: reserved 535 536 In case of punctured transmission: 537 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 538 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 539 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 540 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 541 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 542 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 543 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 544 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 545 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 546 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 547 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 548 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 549 Sw_buffer_cookie[19:18] = 2'b11: reserved 550 551 Note: a punctured transmission is indicated by the presence 552 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 553 554 <legal all> 555 */ 556 557 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 558 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 559 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 560 #define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 561 562 563 /* Description RX_MSDU_DESC_INFO_DETAILS 564 565 Consumer: REO/SW 566 Producer: RXDMA 567 568 General information related to the MSDU that should be passed 569 on from RXDMA all the way to to the REO destination ring. 570 571 */ 572 573 574 /* Description FIRST_MSDU_IN_MPDU_FLAG 575 576 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 577 multiple buffers, this field will be valid in the Last 578 buffer used by the MSDU 579 580 <enum 0 Not_first_msdu> This is not the first MSDU in the 581 MPDU. 582 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 583 584 585 <legal all> 586 */ 587 588 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 589 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 590 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 591 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 592 593 594 /* Description LAST_MSDU_IN_MPDU_FLAG 595 596 Consumer: WBM/REO/SW/FW 597 Producer: RXDMA 598 599 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 600 multiple buffers, this field will be valid in the Last 601 buffer used by the MSDU 602 603 <enum 0 Not_last_msdu> There are more MSDUs linked to this 604 MSDU that belongs to this MPDU 605 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 606 This setting is only allowed in combination with 'Msdu_continuation' 607 set to 0. This implies that when an msdu is spread out over 608 multiple buffers and thus msdu_continuation is set, only 609 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 610 be set. 611 612 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 613 are set, the MPDU that this MSDU belongs to only contains 614 a single MSDU. 615 616 617 <legal all> 618 */ 619 620 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 621 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 622 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 623 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 624 625 626 /* Description MSDU_CONTINUATION 627 628 When set, this MSDU buffer was not able to hold the entire 629 MSDU. The next buffer will therefor contain additional 630 information related to this MSDU. 631 632 <legal all> 633 */ 634 635 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 636 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 637 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 638 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 639 640 641 /* Description MSDU_LENGTH 642 643 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 644 multiple buffers, this field will be valid in the First 645 buffer used by MSDU. 646 647 Full MSDU length in bytes after decapsulation. 648 649 This field is still valid for MPDU frames without A-MSDU. 650 It still represents MSDU length after decapsulation 651 652 Or in case of RAW MPDUs, it indicates the length of the 653 entire MPDU (without FCS field) 654 <legal all> 655 */ 656 657 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 658 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 659 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 660 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 661 662 663 /* Description MSDU_DROP 664 665 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 666 multiple buffers, this field will be valid in the Last 667 buffer used by the MSDU 668 669 When set, REO shall drop this MSDU and not forward it to 670 any other ring... 671 <legal all> 672 */ 673 674 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 675 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 676 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 677 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 678 679 680 /* Description SA_IS_VALID 681 682 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 683 multiple buffers, this field will be valid in the Last 684 buffer used by the MSDU 685 686 Indicates that OLE found a valid SA entry for this MSDU 687 <legal all> 688 */ 689 690 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 691 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 692 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 693 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 694 695 696 /* Description DA_IS_VALID 697 698 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 699 multiple buffers, this field will be valid in the Last 700 buffer used by the MSDU 701 702 Indicates that OLE found a valid DA entry for this MSDU 703 <legal all> 704 */ 705 706 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 707 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 708 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 709 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 710 711 712 /* Description DA_IS_MCBC 713 714 Field Only valid if "da_is_valid" is set 715 716 Indicates the DA address was a Multicast of Broadcast address 717 for this MSDU 718 <legal all> 719 */ 720 721 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 722 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 723 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 724 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 725 726 727 /* Description L3_HEADER_PADDING_MSB 728 729 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 730 as the LSB is always zero) 731 Number of bytes padded to make sure that the L3 header will 732 always start of a Dword boundary 733 <legal all> 734 */ 735 736 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 737 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 738 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 739 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 740 741 742 /* Description TCP_UDP_CHKSUM_FAIL 743 744 Passed on from 'RX_ATTENTION' TLV 745 Indicates that the computed checksum did not match the checksum 746 in the TCP/UDP header. 747 <legal all> 748 */ 749 750 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 751 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 752 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 753 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 754 755 756 /* Description IP_CHKSUM_FAIL 757 758 Passed on from 'RX_ATTENTION' TLV 759 Indicates that the computed checksum did not match the checksum 760 in the IP header. 761 <legal all> 762 */ 763 764 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 765 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 766 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 767 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 768 769 770 /* Description FR_DS 771 772 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 773 TLV 774 Set if the 'from DS' bit is set in the frame control. 775 <legal all> 776 */ 777 778 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 779 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 780 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 781 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 782 783 784 /* Description TO_DS 785 786 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 787 TLV 788 Set if the 'to DS' bit is set in the frame control. 789 <legal all> 790 */ 791 792 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 793 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 794 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 795 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 796 797 798 /* Description INTRA_BSS 799 800 This packet needs intra-BSS routing by SW as the 'vdev_id' 801 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 802 that this MSDU was got in. 803 804 <legal all> 805 */ 806 807 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 808 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 809 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 810 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 811 812 813 /* Description DEST_CHIP_ID 814 815 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 816 to support intra-BSS routing with multi-chip multi-link 817 operation. 818 819 This indicates into which chip's TCL the packet should be 820 queued. 821 822 <legal all> 823 */ 824 825 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 826 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 827 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 828 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 829 830 831 /* Description DECAP_FORMAT 832 833 Indicates the format after decapsulation: 834 835 <enum 0 RAW> No encapsulation 836 <enum 1 Native_WiFi> 837 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 838 839 <enum 3 802_3> Indicate Ethernet 840 841 <legal all> 842 */ 843 844 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 845 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 846 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 847 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 848 849 850 /* Description DEST_CHIP_PMAC_ID 851 852 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 853 to support intra-BSS routing with multi-chip multi-link 854 operation. 855 856 This indicates into which link/'vdev' the packet should 857 be queued in TCL. 858 859 <legal all> 860 */ 861 862 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000028 863 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 864 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 865 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 866 867 868 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 869 870 Consumer: REO/SW 871 Producer: RXDMA 872 873 Extended information related to the MSDU that is passed 874 on from RXDMA to REO but not part of the REO destination 875 ring. Some fields are passed on to PPE. 876 */ 877 878 879 /* Description REO_DESTINATION_INDICATION 880 881 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 882 multiple buffers, this field will be valid in the Last 883 buffer used by the MSDU 884 885 The ID of the REO exit ring where the MSDU frame shall push 886 after (MPDU level) reordering has finished. 887 888 <enum 0 reo_destination_sw0> Reo will push the frame into 889 the REO2SW0 ring 890 <enum 1 reo_destination_sw1> Reo will push the frame into 891 the REO2SW1 ring 892 <enum 2 reo_destination_sw2> Reo will push the frame into 893 the REO2SW2 ring 894 <enum 3 reo_destination_sw3> Reo will push the frame into 895 the REO2SW3 ring 896 <enum 4 reo_destination_sw4> Reo will push the frame into 897 the REO2SW4 ring 898 <enum 5 reo_destination_release> Reo will push the frame 899 into the REO_release ring 900 <enum 6 reo_destination_fw> Reo will push the frame into 901 the REO2FW ring 902 <enum 7 reo_destination_sw5> Reo will push the frame into 903 the REO2SW5 ring (REO remaps this in chips without REO2SW5 904 ring) 905 <enum 8 reo_destination_sw6> Reo will push the frame into 906 the REO2SW6 ring (REO remaps this in chips without REO2SW6 907 ring) 908 <enum 9 reo_destination_sw7> Reo will push the frame into 909 the REO2SW7 ring (REO remaps this in chips without REO2SW7 910 ring) 911 <enum 10 reo_destination_sw8> Reo will push the frame into 912 the REO2SW8 ring (REO remaps this in chips without REO2SW8 913 ring) 914 <enum 11 reo_destination_11> REO remaps this 915 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 916 REO remaps this 917 <enum 14 reo_destination_14> REO remaps this 918 <enum 15 reo_destination_15> REO remaps this 919 <enum 16 reo_destination_16> REO remaps this 920 <enum 17 reo_destination_17> REO remaps this 921 <enum 18 reo_destination_18> REO remaps this 922 <enum 19 reo_destination_19> REO remaps this 923 <enum 20 reo_destination_20> REO remaps this 924 <enum 21 reo_destination_21> REO remaps this 925 <enum 22 reo_destination_22> REO remaps this 926 <enum 23 reo_destination_23> REO remaps this 927 <enum 24 reo_destination_24> REO remaps this 928 <enum 25 reo_destination_25> REO remaps this 929 <enum 26 reo_destination_26> REO remaps this 930 <enum 27 reo_destination_27> REO remaps this 931 <enum 28 reo_destination_28> REO remaps this 932 <enum 29 reo_destination_29> REO remaps this 933 <enum 30 reo_destination_30> REO remaps this 934 <enum 31 reo_destination_31> REO remaps this 935 936 <legal all> 937 */ 938 939 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c 940 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 941 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 942 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 943 944 945 /* Description SERVICE_CODE 946 947 Opaque service code between PPE and Wi-Fi 948 949 This field gets passed on by REO to PPE in the EDMA descriptor 950 ('REO_TO_PPE_RING'). 951 952 <legal all> 953 */ 954 955 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c 956 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 957 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 958 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 959 960 961 /* Description PRIORITY_VALID 962 963 This field gets passed on by REO to PPE in the EDMA descriptor 964 ('REO_TO_PPE_RING'). 965 966 <legal all> 967 */ 968 969 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c 970 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 971 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 972 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 973 974 975 /* Description DATA_OFFSET 976 977 The offset to Rx packet data within the buffer (including 978 Rx DMA offset programming and L3 header padding inserted 979 by Rx OLE). 980 981 This field gets passed on by REO to PPE in the EDMA descriptor 982 ('REO_TO_PPE_RING'). 983 984 <legal all> 985 */ 986 987 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c 988 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 989 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 990 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 991 992 993 /* Description SRC_LINK_ID 994 995 Consumer: SW 996 Producer: RXDMA 997 998 Set to the link ID of the PMAC that received the frame 999 <legal all> 1000 */ 1001 1002 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c 1003 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 1004 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 1005 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 1006 1007 1008 /* Description RESERVED_0A 1009 1010 <legal 0> 1011 */ 1012 1013 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c 1014 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 1015 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 1016 #define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 1017 1018 1019 /* Description MSDU_1 1020 1021 Details of next MSDU in this (MSDU flow) linked list 1022 */ 1023 1024 1025 /* Description BUFFER_ADDR_INFO_DETAILS 1026 1027 Consumer: REO/SW 1028 Producer: RXDMA 1029 1030 Details of the physical address of the buffer containing 1031 an MSDU (or entire MPDU) 1032 */ 1033 1034 1035 /* Description BUFFER_ADDR_31_0 1036 1037 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1038 descriptor OR Link Descriptor 1039 1040 In case of 'NULL' pointer, this field is set to 0 1041 <legal all> 1042 */ 1043 1044 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 1045 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1046 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 1047 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1048 1049 1050 /* Description BUFFER_ADDR_39_32 1051 1052 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1053 descriptor OR Link Descriptor 1054 1055 In case of 'NULL' pointer, this field is set to 0 1056 <legal all> 1057 */ 1058 1059 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 1060 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1061 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 1062 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1063 1064 1065 /* Description RETURN_BUFFER_MANAGER 1066 1067 Consumer: WBM 1068 Producer: SW/FW 1069 1070 In case of 'NULL' pointer, this field is set to 0 1071 1072 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1073 descriptor OR link descriptor that is being pointed to 1074 shall be returned after the frame has been processed. It 1075 is used by WBM for routing purposes. 1076 1077 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1078 to the WMB buffer idle list 1079 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1080 to the WBM idle link descriptor idle list, where the chip 1081 0 WBM is chosen in case of a multi-chip config 1082 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1083 to the chip 1 WBM idle link descriptor idle list 1084 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1085 to the chip 2 WBM idle link descriptor idle list 1086 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1087 returned to chip 3 WBM idle link descriptor idle list 1088 <enum 4 FW_BM> This buffer shall be returned to the FW 1089 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1090 ring 0 1091 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1092 ring 1 1093 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1094 ring 2 1095 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1096 ring 3 1097 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1098 ring 4 1099 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1100 ring 5 1101 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1102 ring 6 1103 1104 <legal 0-12> 1105 */ 1106 1107 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1108 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1109 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 1110 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1111 1112 1113 /* Description SW_BUFFER_COOKIE 1114 1115 Cookie field exclusively used by SW. 1116 1117 In case of 'NULL' pointer, this field is set to 0 1118 1119 HW ignores the contents, accept that it passes the programmed 1120 value on to other descriptors together with the physical 1121 address 1122 1123 Field can be used by SW to for example associate the buffers 1124 physical address with the virtual address 1125 The bit definitions as used by SW are within SW HLD specification 1126 1127 1128 NOTE1: 1129 The three most significant bits can have a special meaning 1130 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1131 and field transmit_bw_restriction is set 1132 1133 In case of NON punctured transmission: 1134 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1135 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1136 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1137 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1138 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1139 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1140 Sw_buffer_cookie[19:18] = 2'b11: reserved 1141 1142 In case of punctured transmission: 1143 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1144 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1145 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1146 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1147 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1148 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1149 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1150 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1151 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1152 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1153 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1154 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1155 Sw_buffer_cookie[19:18] = 2'b11: reserved 1156 1157 Note: a punctured transmission is indicated by the presence 1158 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1159 1160 <legal all> 1161 */ 1162 1163 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 1164 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 1165 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 1166 #define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 1167 1168 1169 /* Description RX_MSDU_DESC_INFO_DETAILS 1170 1171 Consumer: REO/SW 1172 Producer: RXDMA 1173 1174 General information related to the MSDU that should be passed 1175 on from RXDMA all the way to to the REO destination ring. 1176 1177 */ 1178 1179 1180 /* Description FIRST_MSDU_IN_MPDU_FLAG 1181 1182 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1183 multiple buffers, this field will be valid in the Last 1184 buffer used by the MSDU 1185 1186 <enum 0 Not_first_msdu> This is not the first MSDU in the 1187 MPDU. 1188 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 1189 1190 1191 <legal all> 1192 */ 1193 1194 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1195 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1196 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 1197 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1198 1199 1200 /* Description LAST_MSDU_IN_MPDU_FLAG 1201 1202 Consumer: WBM/REO/SW/FW 1203 Producer: RXDMA 1204 1205 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1206 multiple buffers, this field will be valid in the Last 1207 buffer used by the MSDU 1208 1209 <enum 0 Not_last_msdu> There are more MSDUs linked to this 1210 MSDU that belongs to this MPDU 1211 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 1212 This setting is only allowed in combination with 'Msdu_continuation' 1213 set to 0. This implies that when an msdu is spread out over 1214 multiple buffers and thus msdu_continuation is set, only 1215 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 1216 be set. 1217 1218 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 1219 are set, the MPDU that this MSDU belongs to only contains 1220 a single MSDU. 1221 1222 1223 <legal all> 1224 */ 1225 1226 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1227 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1228 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 1229 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1230 1231 1232 /* Description MSDU_CONTINUATION 1233 1234 When set, this MSDU buffer was not able to hold the entire 1235 MSDU. The next buffer will therefor contain additional 1236 information related to this MSDU. 1237 1238 <legal all> 1239 */ 1240 1241 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 1242 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1243 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 1244 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1245 1246 1247 /* Description MSDU_LENGTH 1248 1249 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 1250 multiple buffers, this field will be valid in the First 1251 buffer used by MSDU. 1252 1253 Full MSDU length in bytes after decapsulation. 1254 1255 This field is still valid for MPDU frames without A-MSDU. 1256 It still represents MSDU length after decapsulation 1257 1258 Or in case of RAW MPDUs, it indicates the length of the 1259 entire MPDU (without FCS field) 1260 <legal all> 1261 */ 1262 1263 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 1264 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1265 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 1266 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1267 1268 1269 /* Description MSDU_DROP 1270 1271 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1272 multiple buffers, this field will be valid in the Last 1273 buffer used by the MSDU 1274 1275 When set, REO shall drop this MSDU and not forward it to 1276 any other ring... 1277 <legal all> 1278 */ 1279 1280 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 1281 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 1282 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 1283 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 1284 1285 1286 /* Description SA_IS_VALID 1287 1288 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1289 multiple buffers, this field will be valid in the Last 1290 buffer used by the MSDU 1291 1292 Indicates that OLE found a valid SA entry for this MSDU 1293 <legal all> 1294 */ 1295 1296 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 1297 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 1298 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 1299 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 1300 1301 1302 /* Description DA_IS_VALID 1303 1304 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1305 multiple buffers, this field will be valid in the Last 1306 buffer used by the MSDU 1307 1308 Indicates that OLE found a valid DA entry for this MSDU 1309 <legal all> 1310 */ 1311 1312 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 1313 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 1314 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 1315 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 1316 1317 1318 /* Description DA_IS_MCBC 1319 1320 Field Only valid if "da_is_valid" is set 1321 1322 Indicates the DA address was a Multicast of Broadcast address 1323 for this MSDU 1324 <legal all> 1325 */ 1326 1327 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 1328 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 1329 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 1330 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 1331 1332 1333 /* Description L3_HEADER_PADDING_MSB 1334 1335 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 1336 as the LSB is always zero) 1337 Number of bytes padded to make sure that the L3 header will 1338 always start of a Dword boundary 1339 <legal all> 1340 */ 1341 1342 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 1343 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 1344 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 1345 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 1346 1347 1348 /* Description TCP_UDP_CHKSUM_FAIL 1349 1350 Passed on from 'RX_ATTENTION' TLV 1351 Indicates that the computed checksum did not match the checksum 1352 in the TCP/UDP header. 1353 <legal all> 1354 */ 1355 1356 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 1357 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 1358 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 1359 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 1360 1361 1362 /* Description IP_CHKSUM_FAIL 1363 1364 Passed on from 'RX_ATTENTION' TLV 1365 Indicates that the computed checksum did not match the checksum 1366 in the IP header. 1367 <legal all> 1368 */ 1369 1370 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 1371 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 1372 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 1373 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 1374 1375 1376 /* Description FR_DS 1377 1378 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1379 TLV 1380 Set if the 'from DS' bit is set in the frame control. 1381 <legal all> 1382 */ 1383 1384 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 1385 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 1386 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 1387 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 1388 1389 1390 /* Description TO_DS 1391 1392 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1393 TLV 1394 Set if the 'to DS' bit is set in the frame control. 1395 <legal all> 1396 */ 1397 1398 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 1399 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 1400 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 1401 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 1402 1403 1404 /* Description INTRA_BSS 1405 1406 This packet needs intra-BSS routing by SW as the 'vdev_id' 1407 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 1408 that this MSDU was got in. 1409 1410 <legal all> 1411 */ 1412 1413 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 1414 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 1415 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 1416 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 1417 1418 1419 /* Description DEST_CHIP_ID 1420 1421 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 1422 to support intra-BSS routing with multi-chip multi-link 1423 operation. 1424 1425 This indicates into which chip's TCL the packet should be 1426 queued. 1427 1428 <legal all> 1429 */ 1430 1431 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 1432 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 1433 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 1434 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 1435 1436 1437 /* Description DECAP_FORMAT 1438 1439 Indicates the format after decapsulation: 1440 1441 <enum 0 RAW> No encapsulation 1442 <enum 1 Native_WiFi> 1443 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 1444 1445 <enum 3 802_3> Indicate Ethernet 1446 1447 <legal all> 1448 */ 1449 1450 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 1451 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 1452 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 1453 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 1454 1455 1456 /* Description DEST_CHIP_PMAC_ID 1457 1458 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 1459 to support intra-BSS routing with multi-chip multi-link 1460 operation. 1461 1462 This indicates into which link/'vdev' the packet should 1463 be queued in TCL. 1464 1465 <legal all> 1466 */ 1467 1468 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000038 1469 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 1470 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 1471 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 1472 1473 1474 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 1475 1476 Consumer: REO/SW 1477 Producer: RXDMA 1478 1479 Extended information related to the MSDU that is passed 1480 on from RXDMA to REO but not part of the REO destination 1481 ring. Some fields are passed on to PPE. 1482 */ 1483 1484 1485 /* Description REO_DESTINATION_INDICATION 1486 1487 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1488 multiple buffers, this field will be valid in the Last 1489 buffer used by the MSDU 1490 1491 The ID of the REO exit ring where the MSDU frame shall push 1492 after (MPDU level) reordering has finished. 1493 1494 <enum 0 reo_destination_sw0> Reo will push the frame into 1495 the REO2SW0 ring 1496 <enum 1 reo_destination_sw1> Reo will push the frame into 1497 the REO2SW1 ring 1498 <enum 2 reo_destination_sw2> Reo will push the frame into 1499 the REO2SW2 ring 1500 <enum 3 reo_destination_sw3> Reo will push the frame into 1501 the REO2SW3 ring 1502 <enum 4 reo_destination_sw4> Reo will push the frame into 1503 the REO2SW4 ring 1504 <enum 5 reo_destination_release> Reo will push the frame 1505 into the REO_release ring 1506 <enum 6 reo_destination_fw> Reo will push the frame into 1507 the REO2FW ring 1508 <enum 7 reo_destination_sw5> Reo will push the frame into 1509 the REO2SW5 ring (REO remaps this in chips without REO2SW5 1510 ring) 1511 <enum 8 reo_destination_sw6> Reo will push the frame into 1512 the REO2SW6 ring (REO remaps this in chips without REO2SW6 1513 ring) 1514 <enum 9 reo_destination_sw7> Reo will push the frame into 1515 the REO2SW7 ring (REO remaps this in chips without REO2SW7 1516 ring) 1517 <enum 10 reo_destination_sw8> Reo will push the frame into 1518 the REO2SW8 ring (REO remaps this in chips without REO2SW8 1519 ring) 1520 <enum 11 reo_destination_11> REO remaps this 1521 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 1522 REO remaps this 1523 <enum 14 reo_destination_14> REO remaps this 1524 <enum 15 reo_destination_15> REO remaps this 1525 <enum 16 reo_destination_16> REO remaps this 1526 <enum 17 reo_destination_17> REO remaps this 1527 <enum 18 reo_destination_18> REO remaps this 1528 <enum 19 reo_destination_19> REO remaps this 1529 <enum 20 reo_destination_20> REO remaps this 1530 <enum 21 reo_destination_21> REO remaps this 1531 <enum 22 reo_destination_22> REO remaps this 1532 <enum 23 reo_destination_23> REO remaps this 1533 <enum 24 reo_destination_24> REO remaps this 1534 <enum 25 reo_destination_25> REO remaps this 1535 <enum 26 reo_destination_26> REO remaps this 1536 <enum 27 reo_destination_27> REO remaps this 1537 <enum 28 reo_destination_28> REO remaps this 1538 <enum 29 reo_destination_29> REO remaps this 1539 <enum 30 reo_destination_30> REO remaps this 1540 <enum 31 reo_destination_31> REO remaps this 1541 1542 <legal all> 1543 */ 1544 1545 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c 1546 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 1547 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 1548 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 1549 1550 1551 /* Description SERVICE_CODE 1552 1553 Opaque service code between PPE and Wi-Fi 1554 1555 This field gets passed on by REO to PPE in the EDMA descriptor 1556 ('REO_TO_PPE_RING'). 1557 1558 <legal all> 1559 */ 1560 1561 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c 1562 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 1563 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 1564 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 1565 1566 1567 /* Description PRIORITY_VALID 1568 1569 This field gets passed on by REO to PPE in the EDMA descriptor 1570 ('REO_TO_PPE_RING'). 1571 1572 <legal all> 1573 */ 1574 1575 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c 1576 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 1577 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 1578 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 1579 1580 1581 /* Description DATA_OFFSET 1582 1583 The offset to Rx packet data within the buffer (including 1584 Rx DMA offset programming and L3 header padding inserted 1585 by Rx OLE). 1586 1587 This field gets passed on by REO to PPE in the EDMA descriptor 1588 ('REO_TO_PPE_RING'). 1589 1590 <legal all> 1591 */ 1592 1593 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c 1594 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 1595 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 1596 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 1597 1598 1599 /* Description SRC_LINK_ID 1600 1601 Consumer: SW 1602 Producer: RXDMA 1603 1604 Set to the link ID of the PMAC that received the frame 1605 <legal all> 1606 */ 1607 1608 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c 1609 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 1610 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 1611 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 1612 1613 1614 /* Description RESERVED_0A 1615 1616 <legal 0> 1617 */ 1618 1619 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c 1620 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 1621 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 1622 #define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 1623 1624 1625 /* Description MSDU_2 1626 1627 Details of next MSDU in this (MSDU flow) linked list 1628 */ 1629 1630 1631 /* Description BUFFER_ADDR_INFO_DETAILS 1632 1633 Consumer: REO/SW 1634 Producer: RXDMA 1635 1636 Details of the physical address of the buffer containing 1637 an MSDU (or entire MPDU) 1638 */ 1639 1640 1641 /* Description BUFFER_ADDR_31_0 1642 1643 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1644 descriptor OR Link Descriptor 1645 1646 In case of 'NULL' pointer, this field is set to 0 1647 <legal all> 1648 */ 1649 1650 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 1651 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1652 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 1653 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1654 1655 1656 /* Description BUFFER_ADDR_39_32 1657 1658 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1659 descriptor OR Link Descriptor 1660 1661 In case of 'NULL' pointer, this field is set to 0 1662 <legal all> 1663 */ 1664 1665 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 1666 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1667 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 1668 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1669 1670 1671 /* Description RETURN_BUFFER_MANAGER 1672 1673 Consumer: WBM 1674 Producer: SW/FW 1675 1676 In case of 'NULL' pointer, this field is set to 0 1677 1678 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1679 descriptor OR link descriptor that is being pointed to 1680 shall be returned after the frame has been processed. It 1681 is used by WBM for routing purposes. 1682 1683 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1684 to the WMB buffer idle list 1685 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1686 to the WBM idle link descriptor idle list, where the chip 1687 0 WBM is chosen in case of a multi-chip config 1688 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1689 to the chip 1 WBM idle link descriptor idle list 1690 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1691 to the chip 2 WBM idle link descriptor idle list 1692 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1693 returned to chip 3 WBM idle link descriptor idle list 1694 <enum 4 FW_BM> This buffer shall be returned to the FW 1695 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1696 ring 0 1697 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1698 ring 1 1699 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1700 ring 2 1701 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1702 ring 3 1703 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1704 ring 4 1705 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1706 ring 5 1707 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1708 ring 6 1709 1710 <legal 0-12> 1711 */ 1712 1713 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1714 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1715 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 1716 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1717 1718 1719 /* Description SW_BUFFER_COOKIE 1720 1721 Cookie field exclusively used by SW. 1722 1723 In case of 'NULL' pointer, this field is set to 0 1724 1725 HW ignores the contents, accept that it passes the programmed 1726 value on to other descriptors together with the physical 1727 address 1728 1729 Field can be used by SW to for example associate the buffers 1730 physical address with the virtual address 1731 The bit definitions as used by SW are within SW HLD specification 1732 1733 1734 NOTE1: 1735 The three most significant bits can have a special meaning 1736 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1737 and field transmit_bw_restriction is set 1738 1739 In case of NON punctured transmission: 1740 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1741 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1742 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1743 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1744 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1745 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1746 Sw_buffer_cookie[19:18] = 2'b11: reserved 1747 1748 In case of punctured transmission: 1749 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1750 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1751 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1752 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1753 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1754 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1755 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1756 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1757 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1758 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1759 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1760 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1761 Sw_buffer_cookie[19:18] = 2'b11: reserved 1762 1763 Note: a punctured transmission is indicated by the presence 1764 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1765 1766 <legal all> 1767 */ 1768 1769 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 1770 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 1771 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 1772 #define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 1773 1774 1775 /* Description RX_MSDU_DESC_INFO_DETAILS 1776 1777 Consumer: REO/SW 1778 Producer: RXDMA 1779 1780 General information related to the MSDU that should be passed 1781 on from RXDMA all the way to to the REO destination ring. 1782 1783 */ 1784 1785 1786 /* Description FIRST_MSDU_IN_MPDU_FLAG 1787 1788 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1789 multiple buffers, this field will be valid in the Last 1790 buffer used by the MSDU 1791 1792 <enum 0 Not_first_msdu> This is not the first MSDU in the 1793 MPDU. 1794 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 1795 1796 1797 <legal all> 1798 */ 1799 1800 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1801 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1802 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 1803 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1804 1805 1806 /* Description LAST_MSDU_IN_MPDU_FLAG 1807 1808 Consumer: WBM/REO/SW/FW 1809 Producer: RXDMA 1810 1811 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1812 multiple buffers, this field will be valid in the Last 1813 buffer used by the MSDU 1814 1815 <enum 0 Not_last_msdu> There are more MSDUs linked to this 1816 MSDU that belongs to this MPDU 1817 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 1818 This setting is only allowed in combination with 'Msdu_continuation' 1819 set to 0. This implies that when an msdu is spread out over 1820 multiple buffers and thus msdu_continuation is set, only 1821 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 1822 be set. 1823 1824 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 1825 are set, the MPDU that this MSDU belongs to only contains 1826 a single MSDU. 1827 1828 1829 <legal all> 1830 */ 1831 1832 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1833 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1834 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 1835 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1836 1837 1838 /* Description MSDU_CONTINUATION 1839 1840 When set, this MSDU buffer was not able to hold the entire 1841 MSDU. The next buffer will therefor contain additional 1842 information related to this MSDU. 1843 1844 <legal all> 1845 */ 1846 1847 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 1848 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1849 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 1850 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1851 1852 1853 /* Description MSDU_LENGTH 1854 1855 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 1856 multiple buffers, this field will be valid in the First 1857 buffer used by MSDU. 1858 1859 Full MSDU length in bytes after decapsulation. 1860 1861 This field is still valid for MPDU frames without A-MSDU. 1862 It still represents MSDU length after decapsulation 1863 1864 Or in case of RAW MPDUs, it indicates the length of the 1865 entire MPDU (without FCS field) 1866 <legal all> 1867 */ 1868 1869 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 1870 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1871 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 1872 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1873 1874 1875 /* Description MSDU_DROP 1876 1877 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1878 multiple buffers, this field will be valid in the Last 1879 buffer used by the MSDU 1880 1881 When set, REO shall drop this MSDU and not forward it to 1882 any other ring... 1883 <legal all> 1884 */ 1885 1886 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 1887 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 1888 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 1889 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 1890 1891 1892 /* Description SA_IS_VALID 1893 1894 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1895 multiple buffers, this field will be valid in the Last 1896 buffer used by the MSDU 1897 1898 Indicates that OLE found a valid SA entry for this MSDU 1899 <legal all> 1900 */ 1901 1902 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 1903 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 1904 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 1905 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 1906 1907 1908 /* Description DA_IS_VALID 1909 1910 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 1911 multiple buffers, this field will be valid in the Last 1912 buffer used by the MSDU 1913 1914 Indicates that OLE found a valid DA entry for this MSDU 1915 <legal all> 1916 */ 1917 1918 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 1919 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 1920 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 1921 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 1922 1923 1924 /* Description DA_IS_MCBC 1925 1926 Field Only valid if "da_is_valid" is set 1927 1928 Indicates the DA address was a Multicast of Broadcast address 1929 for this MSDU 1930 <legal all> 1931 */ 1932 1933 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 1934 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 1935 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 1936 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 1937 1938 1939 /* Description L3_HEADER_PADDING_MSB 1940 1941 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 1942 as the LSB is always zero) 1943 Number of bytes padded to make sure that the L3 header will 1944 always start of a Dword boundary 1945 <legal all> 1946 */ 1947 1948 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 1949 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 1950 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 1951 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 1952 1953 1954 /* Description TCP_UDP_CHKSUM_FAIL 1955 1956 Passed on from 'RX_ATTENTION' TLV 1957 Indicates that the computed checksum did not match the checksum 1958 in the TCP/UDP header. 1959 <legal all> 1960 */ 1961 1962 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 1963 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 1964 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 1965 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 1966 1967 1968 /* Description IP_CHKSUM_FAIL 1969 1970 Passed on from 'RX_ATTENTION' TLV 1971 Indicates that the computed checksum did not match the checksum 1972 in the IP header. 1973 <legal all> 1974 */ 1975 1976 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 1977 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 1978 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 1979 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 1980 1981 1982 /* Description FR_DS 1983 1984 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1985 TLV 1986 Set if the 'from DS' bit is set in the frame control. 1987 <legal all> 1988 */ 1989 1990 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 1991 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 1992 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 1993 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 1994 1995 1996 /* Description TO_DS 1997 1998 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 1999 TLV 2000 Set if the 'to DS' bit is set in the frame control. 2001 <legal all> 2002 */ 2003 2004 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 2005 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 2006 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 2007 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 2008 2009 2010 /* Description INTRA_BSS 2011 2012 This packet needs intra-BSS routing by SW as the 'vdev_id' 2013 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 2014 that this MSDU was got in. 2015 2016 <legal all> 2017 */ 2018 2019 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 2020 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 2021 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 2022 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 2023 2024 2025 /* Description DEST_CHIP_ID 2026 2027 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2028 to support intra-BSS routing with multi-chip multi-link 2029 operation. 2030 2031 This indicates into which chip's TCL the packet should be 2032 queued. 2033 2034 <legal all> 2035 */ 2036 2037 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 2038 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 2039 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 2040 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 2041 2042 2043 /* Description DECAP_FORMAT 2044 2045 Indicates the format after decapsulation: 2046 2047 <enum 0 RAW> No encapsulation 2048 <enum 1 Native_WiFi> 2049 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 2050 2051 <enum 3 802_3> Indicate Ethernet 2052 2053 <legal all> 2054 */ 2055 2056 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 2057 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 2058 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 2059 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 2060 2061 2062 /* Description DEST_CHIP_PMAC_ID 2063 2064 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2065 to support intra-BSS routing with multi-chip multi-link 2066 operation. 2067 2068 This indicates into which link/'vdev' the packet should 2069 be queued in TCL. 2070 2071 <legal all> 2072 */ 2073 2074 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000048 2075 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 2076 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 2077 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 2078 2079 2080 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 2081 2082 Consumer: REO/SW 2083 Producer: RXDMA 2084 2085 Extended information related to the MSDU that is passed 2086 on from RXDMA to REO but not part of the REO destination 2087 ring. Some fields are passed on to PPE. 2088 */ 2089 2090 2091 /* Description REO_DESTINATION_INDICATION 2092 2093 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2094 multiple buffers, this field will be valid in the Last 2095 buffer used by the MSDU 2096 2097 The ID of the REO exit ring where the MSDU frame shall push 2098 after (MPDU level) reordering has finished. 2099 2100 <enum 0 reo_destination_sw0> Reo will push the frame into 2101 the REO2SW0 ring 2102 <enum 1 reo_destination_sw1> Reo will push the frame into 2103 the REO2SW1 ring 2104 <enum 2 reo_destination_sw2> Reo will push the frame into 2105 the REO2SW2 ring 2106 <enum 3 reo_destination_sw3> Reo will push the frame into 2107 the REO2SW3 ring 2108 <enum 4 reo_destination_sw4> Reo will push the frame into 2109 the REO2SW4 ring 2110 <enum 5 reo_destination_release> Reo will push the frame 2111 into the REO_release ring 2112 <enum 6 reo_destination_fw> Reo will push the frame into 2113 the REO2FW ring 2114 <enum 7 reo_destination_sw5> Reo will push the frame into 2115 the REO2SW5 ring (REO remaps this in chips without REO2SW5 2116 ring) 2117 <enum 8 reo_destination_sw6> Reo will push the frame into 2118 the REO2SW6 ring (REO remaps this in chips without REO2SW6 2119 ring) 2120 <enum 9 reo_destination_sw7> Reo will push the frame into 2121 the REO2SW7 ring (REO remaps this in chips without REO2SW7 2122 ring) 2123 <enum 10 reo_destination_sw8> Reo will push the frame into 2124 the REO2SW8 ring (REO remaps this in chips without REO2SW8 2125 ring) 2126 <enum 11 reo_destination_11> REO remaps this 2127 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 2128 REO remaps this 2129 <enum 14 reo_destination_14> REO remaps this 2130 <enum 15 reo_destination_15> REO remaps this 2131 <enum 16 reo_destination_16> REO remaps this 2132 <enum 17 reo_destination_17> REO remaps this 2133 <enum 18 reo_destination_18> REO remaps this 2134 <enum 19 reo_destination_19> REO remaps this 2135 <enum 20 reo_destination_20> REO remaps this 2136 <enum 21 reo_destination_21> REO remaps this 2137 <enum 22 reo_destination_22> REO remaps this 2138 <enum 23 reo_destination_23> REO remaps this 2139 <enum 24 reo_destination_24> REO remaps this 2140 <enum 25 reo_destination_25> REO remaps this 2141 <enum 26 reo_destination_26> REO remaps this 2142 <enum 27 reo_destination_27> REO remaps this 2143 <enum 28 reo_destination_28> REO remaps this 2144 <enum 29 reo_destination_29> REO remaps this 2145 <enum 30 reo_destination_30> REO remaps this 2146 <enum 31 reo_destination_31> REO remaps this 2147 2148 <legal all> 2149 */ 2150 2151 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c 2152 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 2153 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 2154 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 2155 2156 2157 /* Description SERVICE_CODE 2158 2159 Opaque service code between PPE and Wi-Fi 2160 2161 This field gets passed on by REO to PPE in the EDMA descriptor 2162 ('REO_TO_PPE_RING'). 2163 2164 <legal all> 2165 */ 2166 2167 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c 2168 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 2169 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 2170 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 2171 2172 2173 /* Description PRIORITY_VALID 2174 2175 This field gets passed on by REO to PPE in the EDMA descriptor 2176 ('REO_TO_PPE_RING'). 2177 2178 <legal all> 2179 */ 2180 2181 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c 2182 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 2183 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 2184 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 2185 2186 2187 /* Description DATA_OFFSET 2188 2189 The offset to Rx packet data within the buffer (including 2190 Rx DMA offset programming and L3 header padding inserted 2191 by Rx OLE). 2192 2193 This field gets passed on by REO to PPE in the EDMA descriptor 2194 ('REO_TO_PPE_RING'). 2195 2196 <legal all> 2197 */ 2198 2199 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c 2200 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 2201 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 2202 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 2203 2204 2205 /* Description SRC_LINK_ID 2206 2207 Consumer: SW 2208 Producer: RXDMA 2209 2210 Set to the link ID of the PMAC that received the frame 2211 <legal all> 2212 */ 2213 2214 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c 2215 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 2216 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 2217 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 2218 2219 2220 /* Description RESERVED_0A 2221 2222 <legal 0> 2223 */ 2224 2225 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c 2226 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 2227 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 2228 #define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 2229 2230 2231 /* Description MSDU_3 2232 2233 Details of next MSDU in this (MSDU flow) linked list 2234 */ 2235 2236 2237 /* Description BUFFER_ADDR_INFO_DETAILS 2238 2239 Consumer: REO/SW 2240 Producer: RXDMA 2241 2242 Details of the physical address of the buffer containing 2243 an MSDU (or entire MPDU) 2244 */ 2245 2246 2247 /* Description BUFFER_ADDR_31_0 2248 2249 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2250 descriptor OR Link Descriptor 2251 2252 In case of 'NULL' pointer, this field is set to 0 2253 <legal all> 2254 */ 2255 2256 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 2257 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2258 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 2259 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2260 2261 2262 /* Description BUFFER_ADDR_39_32 2263 2264 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2265 descriptor OR Link Descriptor 2266 2267 In case of 'NULL' pointer, this field is set to 0 2268 <legal all> 2269 */ 2270 2271 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 2272 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2273 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 2274 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2275 2276 2277 /* Description RETURN_BUFFER_MANAGER 2278 2279 Consumer: WBM 2280 Producer: SW/FW 2281 2282 In case of 'NULL' pointer, this field is set to 0 2283 2284 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2285 descriptor OR link descriptor that is being pointed to 2286 shall be returned after the frame has been processed. It 2287 is used by WBM for routing purposes. 2288 2289 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2290 to the WMB buffer idle list 2291 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2292 to the WBM idle link descriptor idle list, where the chip 2293 0 WBM is chosen in case of a multi-chip config 2294 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2295 to the chip 1 WBM idle link descriptor idle list 2296 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2297 to the chip 2 WBM idle link descriptor idle list 2298 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2299 returned to chip 3 WBM idle link descriptor idle list 2300 <enum 4 FW_BM> This buffer shall be returned to the FW 2301 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2302 ring 0 2303 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2304 ring 1 2305 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2306 ring 2 2307 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2308 ring 3 2309 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2310 ring 4 2311 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2312 ring 5 2313 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2314 ring 6 2315 2316 <legal 0-12> 2317 */ 2318 2319 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2320 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2321 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 2322 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2323 2324 2325 /* Description SW_BUFFER_COOKIE 2326 2327 Cookie field exclusively used by SW. 2328 2329 In case of 'NULL' pointer, this field is set to 0 2330 2331 HW ignores the contents, accept that it passes the programmed 2332 value on to other descriptors together with the physical 2333 address 2334 2335 Field can be used by SW to for example associate the buffers 2336 physical address with the virtual address 2337 The bit definitions as used by SW are within SW HLD specification 2338 2339 2340 NOTE1: 2341 The three most significant bits can have a special meaning 2342 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2343 and field transmit_bw_restriction is set 2344 2345 In case of NON punctured transmission: 2346 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2347 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2348 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2349 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2350 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2351 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2352 Sw_buffer_cookie[19:18] = 2'b11: reserved 2353 2354 In case of punctured transmission: 2355 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2356 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2357 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2358 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2359 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2360 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2361 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2362 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2363 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2364 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2365 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2366 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2367 Sw_buffer_cookie[19:18] = 2'b11: reserved 2368 2369 Note: a punctured transmission is indicated by the presence 2370 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2371 2372 <legal all> 2373 */ 2374 2375 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 2376 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 2377 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 2378 #define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 2379 2380 2381 /* Description RX_MSDU_DESC_INFO_DETAILS 2382 2383 Consumer: REO/SW 2384 Producer: RXDMA 2385 2386 General information related to the MSDU that should be passed 2387 on from RXDMA all the way to to the REO destination ring. 2388 2389 */ 2390 2391 2392 /* Description FIRST_MSDU_IN_MPDU_FLAG 2393 2394 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2395 multiple buffers, this field will be valid in the Last 2396 buffer used by the MSDU 2397 2398 <enum 0 Not_first_msdu> This is not the first MSDU in the 2399 MPDU. 2400 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 2401 2402 2403 <legal all> 2404 */ 2405 2406 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2407 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2408 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 2409 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2410 2411 2412 /* Description LAST_MSDU_IN_MPDU_FLAG 2413 2414 Consumer: WBM/REO/SW/FW 2415 Producer: RXDMA 2416 2417 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2418 multiple buffers, this field will be valid in the Last 2419 buffer used by the MSDU 2420 2421 <enum 0 Not_last_msdu> There are more MSDUs linked to this 2422 MSDU that belongs to this MPDU 2423 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 2424 This setting is only allowed in combination with 'Msdu_continuation' 2425 set to 0. This implies that when an msdu is spread out over 2426 multiple buffers and thus msdu_continuation is set, only 2427 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 2428 be set. 2429 2430 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 2431 are set, the MPDU that this MSDU belongs to only contains 2432 a single MSDU. 2433 2434 2435 <legal all> 2436 */ 2437 2438 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2439 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2440 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 2441 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2442 2443 2444 /* Description MSDU_CONTINUATION 2445 2446 When set, this MSDU buffer was not able to hold the entire 2447 MSDU. The next buffer will therefor contain additional 2448 information related to this MSDU. 2449 2450 <legal all> 2451 */ 2452 2453 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 2454 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2455 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 2456 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2457 2458 2459 /* Description MSDU_LENGTH 2460 2461 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 2462 multiple buffers, this field will be valid in the First 2463 buffer used by MSDU. 2464 2465 Full MSDU length in bytes after decapsulation. 2466 2467 This field is still valid for MPDU frames without A-MSDU. 2468 It still represents MSDU length after decapsulation 2469 2470 Or in case of RAW MPDUs, it indicates the length of the 2471 entire MPDU (without FCS field) 2472 <legal all> 2473 */ 2474 2475 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 2476 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2477 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 2478 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2479 2480 2481 /* Description MSDU_DROP 2482 2483 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2484 multiple buffers, this field will be valid in the Last 2485 buffer used by the MSDU 2486 2487 When set, REO shall drop this MSDU and not forward it to 2488 any other ring... 2489 <legal all> 2490 */ 2491 2492 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 2493 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 2494 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 2495 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 2496 2497 2498 /* Description SA_IS_VALID 2499 2500 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2501 multiple buffers, this field will be valid in the Last 2502 buffer used by the MSDU 2503 2504 Indicates that OLE found a valid SA entry for this MSDU 2505 <legal all> 2506 */ 2507 2508 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 2509 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 2510 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 2511 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 2512 2513 2514 /* Description DA_IS_VALID 2515 2516 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2517 multiple buffers, this field will be valid in the Last 2518 buffer used by the MSDU 2519 2520 Indicates that OLE found a valid DA entry for this MSDU 2521 <legal all> 2522 */ 2523 2524 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 2525 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 2526 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 2527 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 2528 2529 2530 /* Description DA_IS_MCBC 2531 2532 Field Only valid if "da_is_valid" is set 2533 2534 Indicates the DA address was a Multicast of Broadcast address 2535 for this MSDU 2536 <legal all> 2537 */ 2538 2539 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 2540 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 2541 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 2542 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 2543 2544 2545 /* Description L3_HEADER_PADDING_MSB 2546 2547 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 2548 as the LSB is always zero) 2549 Number of bytes padded to make sure that the L3 header will 2550 always start of a Dword boundary 2551 <legal all> 2552 */ 2553 2554 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 2555 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 2556 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 2557 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 2558 2559 2560 /* Description TCP_UDP_CHKSUM_FAIL 2561 2562 Passed on from 'RX_ATTENTION' TLV 2563 Indicates that the computed checksum did not match the checksum 2564 in the TCP/UDP header. 2565 <legal all> 2566 */ 2567 2568 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 2569 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 2570 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 2571 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 2572 2573 2574 /* Description IP_CHKSUM_FAIL 2575 2576 Passed on from 'RX_ATTENTION' TLV 2577 Indicates that the computed checksum did not match the checksum 2578 in the IP header. 2579 <legal all> 2580 */ 2581 2582 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 2583 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 2584 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 2585 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 2586 2587 2588 /* Description FR_DS 2589 2590 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 2591 TLV 2592 Set if the 'from DS' bit is set in the frame control. 2593 <legal all> 2594 */ 2595 2596 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 2597 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 2598 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 2599 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 2600 2601 2602 /* Description TO_DS 2603 2604 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 2605 TLV 2606 Set if the 'to DS' bit is set in the frame control. 2607 <legal all> 2608 */ 2609 2610 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 2611 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 2612 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 2613 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 2614 2615 2616 /* Description INTRA_BSS 2617 2618 This packet needs intra-BSS routing by SW as the 'vdev_id' 2619 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 2620 that this MSDU was got in. 2621 2622 <legal all> 2623 */ 2624 2625 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 2626 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 2627 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 2628 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 2629 2630 2631 /* Description DEST_CHIP_ID 2632 2633 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2634 to support intra-BSS routing with multi-chip multi-link 2635 operation. 2636 2637 This indicates into which chip's TCL the packet should be 2638 queued. 2639 2640 <legal all> 2641 */ 2642 2643 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 2644 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 2645 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 2646 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 2647 2648 2649 /* Description DECAP_FORMAT 2650 2651 Indicates the format after decapsulation: 2652 2653 <enum 0 RAW> No encapsulation 2654 <enum 1 Native_WiFi> 2655 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 2656 2657 <enum 3 802_3> Indicate Ethernet 2658 2659 <legal all> 2660 */ 2661 2662 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 2663 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 2664 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 2665 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 2666 2667 2668 /* Description DEST_CHIP_PMAC_ID 2669 2670 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 2671 to support intra-BSS routing with multi-chip multi-link 2672 operation. 2673 2674 This indicates into which link/'vdev' the packet should 2675 be queued in TCL. 2676 2677 <legal all> 2678 */ 2679 2680 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000058 2681 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 2682 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 2683 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 2684 2685 2686 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 2687 2688 Consumer: REO/SW 2689 Producer: RXDMA 2690 2691 Extended information related to the MSDU that is passed 2692 on from RXDMA to REO but not part of the REO destination 2693 ring. Some fields are passed on to PPE. 2694 */ 2695 2696 2697 /* Description REO_DESTINATION_INDICATION 2698 2699 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 2700 multiple buffers, this field will be valid in the Last 2701 buffer used by the MSDU 2702 2703 The ID of the REO exit ring where the MSDU frame shall push 2704 after (MPDU level) reordering has finished. 2705 2706 <enum 0 reo_destination_sw0> Reo will push the frame into 2707 the REO2SW0 ring 2708 <enum 1 reo_destination_sw1> Reo will push the frame into 2709 the REO2SW1 ring 2710 <enum 2 reo_destination_sw2> Reo will push the frame into 2711 the REO2SW2 ring 2712 <enum 3 reo_destination_sw3> Reo will push the frame into 2713 the REO2SW3 ring 2714 <enum 4 reo_destination_sw4> Reo will push the frame into 2715 the REO2SW4 ring 2716 <enum 5 reo_destination_release> Reo will push the frame 2717 into the REO_release ring 2718 <enum 6 reo_destination_fw> Reo will push the frame into 2719 the REO2FW ring 2720 <enum 7 reo_destination_sw5> Reo will push the frame into 2721 the REO2SW5 ring (REO remaps this in chips without REO2SW5 2722 ring) 2723 <enum 8 reo_destination_sw6> Reo will push the frame into 2724 the REO2SW6 ring (REO remaps this in chips without REO2SW6 2725 ring) 2726 <enum 9 reo_destination_sw7> Reo will push the frame into 2727 the REO2SW7 ring (REO remaps this in chips without REO2SW7 2728 ring) 2729 <enum 10 reo_destination_sw8> Reo will push the frame into 2730 the REO2SW8 ring (REO remaps this in chips without REO2SW8 2731 ring) 2732 <enum 11 reo_destination_11> REO remaps this 2733 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 2734 REO remaps this 2735 <enum 14 reo_destination_14> REO remaps this 2736 <enum 15 reo_destination_15> REO remaps this 2737 <enum 16 reo_destination_16> REO remaps this 2738 <enum 17 reo_destination_17> REO remaps this 2739 <enum 18 reo_destination_18> REO remaps this 2740 <enum 19 reo_destination_19> REO remaps this 2741 <enum 20 reo_destination_20> REO remaps this 2742 <enum 21 reo_destination_21> REO remaps this 2743 <enum 22 reo_destination_22> REO remaps this 2744 <enum 23 reo_destination_23> REO remaps this 2745 <enum 24 reo_destination_24> REO remaps this 2746 <enum 25 reo_destination_25> REO remaps this 2747 <enum 26 reo_destination_26> REO remaps this 2748 <enum 27 reo_destination_27> REO remaps this 2749 <enum 28 reo_destination_28> REO remaps this 2750 <enum 29 reo_destination_29> REO remaps this 2751 <enum 30 reo_destination_30> REO remaps this 2752 <enum 31 reo_destination_31> REO remaps this 2753 2754 <legal all> 2755 */ 2756 2757 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c 2758 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 2759 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 2760 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 2761 2762 2763 /* Description SERVICE_CODE 2764 2765 Opaque service code between PPE and Wi-Fi 2766 2767 This field gets passed on by REO to PPE in the EDMA descriptor 2768 ('REO_TO_PPE_RING'). 2769 2770 <legal all> 2771 */ 2772 2773 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c 2774 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 2775 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 2776 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 2777 2778 2779 /* Description PRIORITY_VALID 2780 2781 This field gets passed on by REO to PPE in the EDMA descriptor 2782 ('REO_TO_PPE_RING'). 2783 2784 <legal all> 2785 */ 2786 2787 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c 2788 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 2789 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 2790 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 2791 2792 2793 /* Description DATA_OFFSET 2794 2795 The offset to Rx packet data within the buffer (including 2796 Rx DMA offset programming and L3 header padding inserted 2797 by Rx OLE). 2798 2799 This field gets passed on by REO to PPE in the EDMA descriptor 2800 ('REO_TO_PPE_RING'). 2801 2802 <legal all> 2803 */ 2804 2805 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c 2806 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 2807 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 2808 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 2809 2810 2811 /* Description SRC_LINK_ID 2812 2813 Consumer: SW 2814 Producer: RXDMA 2815 2816 Set to the link ID of the PMAC that received the frame 2817 <legal all> 2818 */ 2819 2820 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c 2821 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 2822 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 2823 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 2824 2825 2826 /* Description RESERVED_0A 2827 2828 <legal 0> 2829 */ 2830 2831 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c 2832 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 2833 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 2834 #define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 2835 2836 2837 /* Description MSDU_4 2838 2839 Details of next MSDU in this (MSDU flow) linked list 2840 */ 2841 2842 2843 /* Description BUFFER_ADDR_INFO_DETAILS 2844 2845 Consumer: REO/SW 2846 Producer: RXDMA 2847 2848 Details of the physical address of the buffer containing 2849 an MSDU (or entire MPDU) 2850 */ 2851 2852 2853 /* Description BUFFER_ADDR_31_0 2854 2855 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2856 descriptor OR Link Descriptor 2857 2858 In case of 'NULL' pointer, this field is set to 0 2859 <legal all> 2860 */ 2861 2862 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 2863 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2864 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 2865 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2866 2867 2868 /* Description BUFFER_ADDR_39_32 2869 2870 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2871 descriptor OR Link Descriptor 2872 2873 In case of 'NULL' pointer, this field is set to 0 2874 <legal all> 2875 */ 2876 2877 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 2878 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2879 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 2880 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2881 2882 2883 /* Description RETURN_BUFFER_MANAGER 2884 2885 Consumer: WBM 2886 Producer: SW/FW 2887 2888 In case of 'NULL' pointer, this field is set to 0 2889 2890 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2891 descriptor OR link descriptor that is being pointed to 2892 shall be returned after the frame has been processed. It 2893 is used by WBM for routing purposes. 2894 2895 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2896 to the WMB buffer idle list 2897 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2898 to the WBM idle link descriptor idle list, where the chip 2899 0 WBM is chosen in case of a multi-chip config 2900 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2901 to the chip 1 WBM idle link descriptor idle list 2902 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2903 to the chip 2 WBM idle link descriptor idle list 2904 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2905 returned to chip 3 WBM idle link descriptor idle list 2906 <enum 4 FW_BM> This buffer shall be returned to the FW 2907 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2908 ring 0 2909 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2910 ring 1 2911 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2912 ring 2 2913 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2914 ring 3 2915 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2916 ring 4 2917 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2918 ring 5 2919 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2920 ring 6 2921 2922 <legal 0-12> 2923 */ 2924 2925 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2926 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2927 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 2928 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2929 2930 2931 /* Description SW_BUFFER_COOKIE 2932 2933 Cookie field exclusively used by SW. 2934 2935 In case of 'NULL' pointer, this field is set to 0 2936 2937 HW ignores the contents, accept that it passes the programmed 2938 value on to other descriptors together with the physical 2939 address 2940 2941 Field can be used by SW to for example associate the buffers 2942 physical address with the virtual address 2943 The bit definitions as used by SW are within SW HLD specification 2944 2945 2946 NOTE1: 2947 The three most significant bits can have a special meaning 2948 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2949 and field transmit_bw_restriction is set 2950 2951 In case of NON punctured transmission: 2952 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2953 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2954 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2955 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2956 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2957 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2958 Sw_buffer_cookie[19:18] = 2'b11: reserved 2959 2960 In case of punctured transmission: 2961 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2962 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2963 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2964 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2965 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2966 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2967 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2968 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2969 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2970 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2971 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2972 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2973 Sw_buffer_cookie[19:18] = 2'b11: reserved 2974 2975 Note: a punctured transmission is indicated by the presence 2976 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2977 2978 <legal all> 2979 */ 2980 2981 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 2982 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 2983 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 2984 #define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 2985 2986 2987 /* Description RX_MSDU_DESC_INFO_DETAILS 2988 2989 Consumer: REO/SW 2990 Producer: RXDMA 2991 2992 General information related to the MSDU that should be passed 2993 on from RXDMA all the way to to the REO destination ring. 2994 2995 */ 2996 2997 2998 /* Description FIRST_MSDU_IN_MPDU_FLAG 2999 3000 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3001 multiple buffers, this field will be valid in the Last 3002 buffer used by the MSDU 3003 3004 <enum 0 Not_first_msdu> This is not the first MSDU in the 3005 MPDU. 3006 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 3007 3008 3009 <legal all> 3010 */ 3011 3012 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 3013 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3014 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 3015 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3016 3017 3018 /* Description LAST_MSDU_IN_MPDU_FLAG 3019 3020 Consumer: WBM/REO/SW/FW 3021 Producer: RXDMA 3022 3023 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3024 multiple buffers, this field will be valid in the Last 3025 buffer used by the MSDU 3026 3027 <enum 0 Not_last_msdu> There are more MSDUs linked to this 3028 MSDU that belongs to this MPDU 3029 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 3030 This setting is only allowed in combination with 'Msdu_continuation' 3031 set to 0. This implies that when an msdu is spread out over 3032 multiple buffers and thus msdu_continuation is set, only 3033 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 3034 be set. 3035 3036 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 3037 are set, the MPDU that this MSDU belongs to only contains 3038 a single MSDU. 3039 3040 3041 <legal all> 3042 */ 3043 3044 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 3045 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3046 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 3047 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3048 3049 3050 /* Description MSDU_CONTINUATION 3051 3052 When set, this MSDU buffer was not able to hold the entire 3053 MSDU. The next buffer will therefor contain additional 3054 information related to this MSDU. 3055 3056 <legal all> 3057 */ 3058 3059 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 3060 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3061 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 3062 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3063 3064 3065 /* Description MSDU_LENGTH 3066 3067 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 3068 multiple buffers, this field will be valid in the First 3069 buffer used by MSDU. 3070 3071 Full MSDU length in bytes after decapsulation. 3072 3073 This field is still valid for MPDU frames without A-MSDU. 3074 It still represents MSDU length after decapsulation 3075 3076 Or in case of RAW MPDUs, it indicates the length of the 3077 entire MPDU (without FCS field) 3078 <legal all> 3079 */ 3080 3081 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 3082 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3083 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 3084 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3085 3086 3087 /* Description MSDU_DROP 3088 3089 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3090 multiple buffers, this field will be valid in the Last 3091 buffer used by the MSDU 3092 3093 When set, REO shall drop this MSDU and not forward it to 3094 any other ring... 3095 <legal all> 3096 */ 3097 3098 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 3099 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 3100 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 3101 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 3102 3103 3104 /* Description SA_IS_VALID 3105 3106 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3107 multiple buffers, this field will be valid in the Last 3108 buffer used by the MSDU 3109 3110 Indicates that OLE found a valid SA entry for this MSDU 3111 <legal all> 3112 */ 3113 3114 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 3115 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 3116 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 3117 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 3118 3119 3120 /* Description DA_IS_VALID 3121 3122 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3123 multiple buffers, this field will be valid in the Last 3124 buffer used by the MSDU 3125 3126 Indicates that OLE found a valid DA entry for this MSDU 3127 <legal all> 3128 */ 3129 3130 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 3131 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 3132 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 3133 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 3134 3135 3136 /* Description DA_IS_MCBC 3137 3138 Field Only valid if "da_is_valid" is set 3139 3140 Indicates the DA address was a Multicast of Broadcast address 3141 for this MSDU 3142 <legal all> 3143 */ 3144 3145 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 3146 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 3147 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 3148 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 3149 3150 3151 /* Description L3_HEADER_PADDING_MSB 3152 3153 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 3154 as the LSB is always zero) 3155 Number of bytes padded to make sure that the L3 header will 3156 always start of a Dword boundary 3157 <legal all> 3158 */ 3159 3160 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 3161 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 3162 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 3163 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 3164 3165 3166 /* Description TCP_UDP_CHKSUM_FAIL 3167 3168 Passed on from 'RX_ATTENTION' TLV 3169 Indicates that the computed checksum did not match the checksum 3170 in the TCP/UDP header. 3171 <legal all> 3172 */ 3173 3174 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 3175 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 3176 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 3177 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 3178 3179 3180 /* Description IP_CHKSUM_FAIL 3181 3182 Passed on from 'RX_ATTENTION' TLV 3183 Indicates that the computed checksum did not match the checksum 3184 in the IP header. 3185 <legal all> 3186 */ 3187 3188 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 3189 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 3190 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 3191 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 3192 3193 3194 /* Description FR_DS 3195 3196 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3197 TLV 3198 Set if the 'from DS' bit is set in the frame control. 3199 <legal all> 3200 */ 3201 3202 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 3203 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 3204 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 3205 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 3206 3207 3208 /* Description TO_DS 3209 3210 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3211 TLV 3212 Set if the 'to DS' bit is set in the frame control. 3213 <legal all> 3214 */ 3215 3216 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 3217 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 3218 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 3219 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 3220 3221 3222 /* Description INTRA_BSS 3223 3224 This packet needs intra-BSS routing by SW as the 'vdev_id' 3225 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 3226 that this MSDU was got in. 3227 3228 <legal all> 3229 */ 3230 3231 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 3232 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 3233 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 3234 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 3235 3236 3237 /* Description DEST_CHIP_ID 3238 3239 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3240 to support intra-BSS routing with multi-chip multi-link 3241 operation. 3242 3243 This indicates into which chip's TCL the packet should be 3244 queued. 3245 3246 <legal all> 3247 */ 3248 3249 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 3250 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 3251 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 3252 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 3253 3254 3255 /* Description DECAP_FORMAT 3256 3257 Indicates the format after decapsulation: 3258 3259 <enum 0 RAW> No encapsulation 3260 <enum 1 Native_WiFi> 3261 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 3262 3263 <enum 3 802_3> Indicate Ethernet 3264 3265 <legal all> 3266 */ 3267 3268 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 3269 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 3270 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 3271 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 3272 3273 3274 /* Description DEST_CHIP_PMAC_ID 3275 3276 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3277 to support intra-BSS routing with multi-chip multi-link 3278 operation. 3279 3280 This indicates into which link/'vdev' the packet should 3281 be queued in TCL. 3282 3283 <legal all> 3284 */ 3285 3286 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000068 3287 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 3288 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 3289 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 3290 3291 3292 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 3293 3294 Consumer: REO/SW 3295 Producer: RXDMA 3296 3297 Extended information related to the MSDU that is passed 3298 on from RXDMA to REO but not part of the REO destination 3299 ring. Some fields are passed on to PPE. 3300 */ 3301 3302 3303 /* Description REO_DESTINATION_INDICATION 3304 3305 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3306 multiple buffers, this field will be valid in the Last 3307 buffer used by the MSDU 3308 3309 The ID of the REO exit ring where the MSDU frame shall push 3310 after (MPDU level) reordering has finished. 3311 3312 <enum 0 reo_destination_sw0> Reo will push the frame into 3313 the REO2SW0 ring 3314 <enum 1 reo_destination_sw1> Reo will push the frame into 3315 the REO2SW1 ring 3316 <enum 2 reo_destination_sw2> Reo will push the frame into 3317 the REO2SW2 ring 3318 <enum 3 reo_destination_sw3> Reo will push the frame into 3319 the REO2SW3 ring 3320 <enum 4 reo_destination_sw4> Reo will push the frame into 3321 the REO2SW4 ring 3322 <enum 5 reo_destination_release> Reo will push the frame 3323 into the REO_release ring 3324 <enum 6 reo_destination_fw> Reo will push the frame into 3325 the REO2FW ring 3326 <enum 7 reo_destination_sw5> Reo will push the frame into 3327 the REO2SW5 ring (REO remaps this in chips without REO2SW5 3328 ring) 3329 <enum 8 reo_destination_sw6> Reo will push the frame into 3330 the REO2SW6 ring (REO remaps this in chips without REO2SW6 3331 ring) 3332 <enum 9 reo_destination_sw7> Reo will push the frame into 3333 the REO2SW7 ring (REO remaps this in chips without REO2SW7 3334 ring) 3335 <enum 10 reo_destination_sw8> Reo will push the frame into 3336 the REO2SW8 ring (REO remaps this in chips without REO2SW8 3337 ring) 3338 <enum 11 reo_destination_11> REO remaps this 3339 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 3340 REO remaps this 3341 <enum 14 reo_destination_14> REO remaps this 3342 <enum 15 reo_destination_15> REO remaps this 3343 <enum 16 reo_destination_16> REO remaps this 3344 <enum 17 reo_destination_17> REO remaps this 3345 <enum 18 reo_destination_18> REO remaps this 3346 <enum 19 reo_destination_19> REO remaps this 3347 <enum 20 reo_destination_20> REO remaps this 3348 <enum 21 reo_destination_21> REO remaps this 3349 <enum 22 reo_destination_22> REO remaps this 3350 <enum 23 reo_destination_23> REO remaps this 3351 <enum 24 reo_destination_24> REO remaps this 3352 <enum 25 reo_destination_25> REO remaps this 3353 <enum 26 reo_destination_26> REO remaps this 3354 <enum 27 reo_destination_27> REO remaps this 3355 <enum 28 reo_destination_28> REO remaps this 3356 <enum 29 reo_destination_29> REO remaps this 3357 <enum 30 reo_destination_30> REO remaps this 3358 <enum 31 reo_destination_31> REO remaps this 3359 3360 <legal all> 3361 */ 3362 3363 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c 3364 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 3365 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 3366 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 3367 3368 3369 /* Description SERVICE_CODE 3370 3371 Opaque service code between PPE and Wi-Fi 3372 3373 This field gets passed on by REO to PPE in the EDMA descriptor 3374 ('REO_TO_PPE_RING'). 3375 3376 <legal all> 3377 */ 3378 3379 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c 3380 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 3381 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 3382 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 3383 3384 3385 /* Description PRIORITY_VALID 3386 3387 This field gets passed on by REO to PPE in the EDMA descriptor 3388 ('REO_TO_PPE_RING'). 3389 3390 <legal all> 3391 */ 3392 3393 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c 3394 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 3395 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 3396 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 3397 3398 3399 /* Description DATA_OFFSET 3400 3401 The offset to Rx packet data within the buffer (including 3402 Rx DMA offset programming and L3 header padding inserted 3403 by Rx OLE). 3404 3405 This field gets passed on by REO to PPE in the EDMA descriptor 3406 ('REO_TO_PPE_RING'). 3407 3408 <legal all> 3409 */ 3410 3411 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c 3412 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 3413 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 3414 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 3415 3416 3417 /* Description SRC_LINK_ID 3418 3419 Consumer: SW 3420 Producer: RXDMA 3421 3422 Set to the link ID of the PMAC that received the frame 3423 <legal all> 3424 */ 3425 3426 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c 3427 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 3428 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 3429 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 3430 3431 3432 /* Description RESERVED_0A 3433 3434 <legal 0> 3435 */ 3436 3437 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c 3438 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 3439 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 3440 #define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 3441 3442 3443 /* Description MSDU_5 3444 3445 Details of next MSDU in this (MSDU flow) linked list 3446 */ 3447 3448 3449 /* Description BUFFER_ADDR_INFO_DETAILS 3450 3451 Consumer: REO/SW 3452 Producer: RXDMA 3453 3454 Details of the physical address of the buffer containing 3455 an MSDU (or entire MPDU) 3456 */ 3457 3458 3459 /* Description BUFFER_ADDR_31_0 3460 3461 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 3462 descriptor OR Link Descriptor 3463 3464 In case of 'NULL' pointer, this field is set to 0 3465 <legal all> 3466 */ 3467 3468 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 3469 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 3470 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 3471 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 3472 3473 3474 /* Description BUFFER_ADDR_39_32 3475 3476 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 3477 descriptor OR Link Descriptor 3478 3479 In case of 'NULL' pointer, this field is set to 0 3480 <legal all> 3481 */ 3482 3483 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 3484 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 3485 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 3486 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 3487 3488 3489 /* Description RETURN_BUFFER_MANAGER 3490 3491 Consumer: WBM 3492 Producer: SW/FW 3493 3494 In case of 'NULL' pointer, this field is set to 0 3495 3496 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 3497 descriptor OR link descriptor that is being pointed to 3498 shall be returned after the frame has been processed. It 3499 is used by WBM for routing purposes. 3500 3501 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 3502 to the WMB buffer idle list 3503 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 3504 to the WBM idle link descriptor idle list, where the chip 3505 0 WBM is chosen in case of a multi-chip config 3506 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 3507 to the chip 1 WBM idle link descriptor idle list 3508 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 3509 to the chip 2 WBM idle link descriptor idle list 3510 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 3511 returned to chip 3 WBM idle link descriptor idle list 3512 <enum 4 FW_BM> This buffer shall be returned to the FW 3513 <enum 5 SW0_BM> This buffer shall be returned to the SW, 3514 ring 0 3515 <enum 6 SW1_BM> This buffer shall be returned to the SW, 3516 ring 1 3517 <enum 7 SW2_BM> This buffer shall be returned to the SW, 3518 ring 2 3519 <enum 8 SW3_BM> This buffer shall be returned to the SW, 3520 ring 3 3521 <enum 9 SW4_BM> This buffer shall be returned to the SW, 3522 ring 4 3523 <enum 10 SW5_BM> This buffer shall be returned to the SW, 3524 ring 5 3525 <enum 11 SW6_BM> This buffer shall be returned to the SW, 3526 ring 6 3527 3528 <legal 0-12> 3529 */ 3530 3531 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 3532 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 3533 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 3534 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 3535 3536 3537 /* Description SW_BUFFER_COOKIE 3538 3539 Cookie field exclusively used by SW. 3540 3541 In case of 'NULL' pointer, this field is set to 0 3542 3543 HW ignores the contents, accept that it passes the programmed 3544 value on to other descriptors together with the physical 3545 address 3546 3547 Field can be used by SW to for example associate the buffers 3548 physical address with the virtual address 3549 The bit definitions as used by SW are within SW HLD specification 3550 3551 3552 NOTE1: 3553 The three most significant bits can have a special meaning 3554 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 3555 and field transmit_bw_restriction is set 3556 3557 In case of NON punctured transmission: 3558 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 3559 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 3560 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 3561 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 3562 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 3563 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 3564 Sw_buffer_cookie[19:18] = 2'b11: reserved 3565 3566 In case of punctured transmission: 3567 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 3568 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 3569 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 3570 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 3571 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 3572 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 3573 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 3574 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 3575 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 3576 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 3577 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 3578 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 3579 Sw_buffer_cookie[19:18] = 2'b11: reserved 3580 3581 Note: a punctured transmission is indicated by the presence 3582 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 3583 3584 <legal all> 3585 */ 3586 3587 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 3588 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 3589 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 3590 #define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 3591 3592 3593 /* Description RX_MSDU_DESC_INFO_DETAILS 3594 3595 Consumer: REO/SW 3596 Producer: RXDMA 3597 3598 General information related to the MSDU that should be passed 3599 on from RXDMA all the way to to the REO destination ring. 3600 3601 */ 3602 3603 3604 /* Description FIRST_MSDU_IN_MPDU_FLAG 3605 3606 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3607 multiple buffers, this field will be valid in the Last 3608 buffer used by the MSDU 3609 3610 <enum 0 Not_first_msdu> This is not the first MSDU in the 3611 MPDU. 3612 <enum 1 first_msdu> This MSDU is the first one in the MPDU. 3613 3614 3615 <legal all> 3616 */ 3617 3618 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3619 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3620 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 3621 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3622 3623 3624 /* Description LAST_MSDU_IN_MPDU_FLAG 3625 3626 Consumer: WBM/REO/SW/FW 3627 Producer: RXDMA 3628 3629 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3630 multiple buffers, this field will be valid in the Last 3631 buffer used by the MSDU 3632 3633 <enum 0 Not_last_msdu> There are more MSDUs linked to this 3634 MSDU that belongs to this MPDU 3635 <enum 1 Last_msdu> this MSDU is the last one in the MPDU. 3636 This setting is only allowed in combination with 'Msdu_continuation' 3637 set to 0. This implies that when an msdu is spread out over 3638 multiple buffers and thus msdu_continuation is set, only 3639 for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' 3640 be set. 3641 3642 When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag 3643 are set, the MPDU that this MSDU belongs to only contains 3644 a single MSDU. 3645 3646 3647 <legal all> 3648 */ 3649 3650 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3651 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3652 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 3653 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3654 3655 3656 /* Description MSDU_CONTINUATION 3657 3658 When set, this MSDU buffer was not able to hold the entire 3659 MSDU. The next buffer will therefor contain additional 3660 information related to this MSDU. 3661 3662 <legal all> 3663 */ 3664 3665 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 3666 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3667 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 3668 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3669 3670 3671 /* Description MSDU_LENGTH 3672 3673 Parsed from RX_MSDU_START TLV . In the case MSDU spans over 3674 multiple buffers, this field will be valid in the First 3675 buffer used by MSDU. 3676 3677 Full MSDU length in bytes after decapsulation. 3678 3679 This field is still valid for MPDU frames without A-MSDU. 3680 It still represents MSDU length after decapsulation 3681 3682 Or in case of RAW MPDUs, it indicates the length of the 3683 entire MPDU (without FCS field) 3684 <legal all> 3685 */ 3686 3687 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 3688 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3689 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 3690 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3691 3692 3693 /* Description MSDU_DROP 3694 3695 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3696 multiple buffers, this field will be valid in the Last 3697 buffer used by the MSDU 3698 3699 When set, REO shall drop this MSDU and not forward it to 3700 any other ring... 3701 <legal all> 3702 */ 3703 3704 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 3705 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 3706 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 3707 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 3708 3709 3710 /* Description SA_IS_VALID 3711 3712 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3713 multiple buffers, this field will be valid in the Last 3714 buffer used by the MSDU 3715 3716 Indicates that OLE found a valid SA entry for this MSDU 3717 <legal all> 3718 */ 3719 3720 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 3721 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 3722 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 3723 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 3724 3725 3726 /* Description DA_IS_VALID 3727 3728 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3729 multiple buffers, this field will be valid in the Last 3730 buffer used by the MSDU 3731 3732 Indicates that OLE found a valid DA entry for this MSDU 3733 <legal all> 3734 */ 3735 3736 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 3737 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 3738 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 3739 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 3740 3741 3742 /* Description DA_IS_MCBC 3743 3744 Field Only valid if "da_is_valid" is set 3745 3746 Indicates the DA address was a Multicast of Broadcast address 3747 for this MSDU 3748 <legal all> 3749 */ 3750 3751 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 3752 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 3753 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 3754 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 3755 3756 3757 /* Description L3_HEADER_PADDING_MSB 3758 3759 Passed on from 'RX_MSDU_END' TLV (only the MSB is reported 3760 as the LSB is always zero) 3761 Number of bytes padded to make sure that the L3 header will 3762 always start of a Dword boundary 3763 <legal all> 3764 */ 3765 3766 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 3767 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 3768 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 3769 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 3770 3771 3772 /* Description TCP_UDP_CHKSUM_FAIL 3773 3774 Passed on from 'RX_ATTENTION' TLV 3775 Indicates that the computed checksum did not match the checksum 3776 in the TCP/UDP header. 3777 <legal all> 3778 */ 3779 3780 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 3781 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 3782 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 3783 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 3784 3785 3786 /* Description IP_CHKSUM_FAIL 3787 3788 Passed on from 'RX_ATTENTION' TLV 3789 Indicates that the computed checksum did not match the checksum 3790 in the IP header. 3791 <legal all> 3792 */ 3793 3794 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 3795 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 3796 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 3797 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 3798 3799 3800 /* Description FR_DS 3801 3802 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3803 TLV 3804 Set if the 'from DS' bit is set in the frame control. 3805 <legal all> 3806 */ 3807 3808 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 3809 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 3810 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 3811 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 3812 3813 3814 /* Description TO_DS 3815 3816 Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' 3817 TLV 3818 Set if the 'to DS' bit is set in the frame control. 3819 <legal all> 3820 */ 3821 3822 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 3823 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 3824 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 3825 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 3826 3827 3828 /* Description INTRA_BSS 3829 3830 This packet needs intra-BSS routing by SW as the 'vdev_id' 3831 for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') 3832 that this MSDU was got in. 3833 3834 <legal all> 3835 */ 3836 3837 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 3838 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 3839 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 3840 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 3841 3842 3843 /* Description DEST_CHIP_ID 3844 3845 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3846 to support intra-BSS routing with multi-chip multi-link 3847 operation. 3848 3849 This indicates into which chip's TCL the packet should be 3850 queued. 3851 3852 <legal all> 3853 */ 3854 3855 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 3856 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 3857 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 3858 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 3859 3860 3861 /* Description DECAP_FORMAT 3862 3863 Indicates the format after decapsulation: 3864 3865 <enum 0 RAW> No encapsulation 3866 <enum 1 Native_WiFi> 3867 <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) 3868 3869 <enum 3 802_3> Indicate Ethernet 3870 3871 <legal all> 3872 */ 3873 3874 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 3875 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 3876 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 3877 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 3878 3879 3880 /* Description DEST_CHIP_PMAC_ID 3881 3882 If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 3883 to support intra-BSS routing with multi-chip multi-link 3884 operation. 3885 3886 This indicates into which link/'vdev' the packet should 3887 be queued in TCL. 3888 3889 <legal all> 3890 */ 3891 3892 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000078 3893 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 3894 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 3895 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 3896 3897 3898 /* Description RX_MSDU_EXT_DESC_INFO_DETAILS 3899 3900 Consumer: REO/SW 3901 Producer: RXDMA 3902 3903 Extended information related to the MSDU that is passed 3904 on from RXDMA to REO but not part of the REO destination 3905 ring. Some fields are passed on to PPE. 3906 */ 3907 3908 3909 /* Description REO_DESTINATION_INDICATION 3910 3911 Parsed from RX_MSDU_END TLV . In the case MSDU spans over 3912 multiple buffers, this field will be valid in the Last 3913 buffer used by the MSDU 3914 3915 The ID of the REO exit ring where the MSDU frame shall push 3916 after (MPDU level) reordering has finished. 3917 3918 <enum 0 reo_destination_sw0> Reo will push the frame into 3919 the REO2SW0 ring 3920 <enum 1 reo_destination_sw1> Reo will push the frame into 3921 the REO2SW1 ring 3922 <enum 2 reo_destination_sw2> Reo will push the frame into 3923 the REO2SW2 ring 3924 <enum 3 reo_destination_sw3> Reo will push the frame into 3925 the REO2SW3 ring 3926 <enum 4 reo_destination_sw4> Reo will push the frame into 3927 the REO2SW4 ring 3928 <enum 5 reo_destination_release> Reo will push the frame 3929 into the REO_release ring 3930 <enum 6 reo_destination_fw> Reo will push the frame into 3931 the REO2FW ring 3932 <enum 7 reo_destination_sw5> Reo will push the frame into 3933 the REO2SW5 ring (REO remaps this in chips without REO2SW5 3934 ring) 3935 <enum 8 reo_destination_sw6> Reo will push the frame into 3936 the REO2SW6 ring (REO remaps this in chips without REO2SW6 3937 ring) 3938 <enum 9 reo_destination_sw7> Reo will push the frame into 3939 the REO2SW7 ring (REO remaps this in chips without REO2SW7 3940 ring) 3941 <enum 10 reo_destination_sw8> Reo will push the frame into 3942 the REO2SW8 ring (REO remaps this in chips without REO2SW8 3943 ring) 3944 <enum 11 reo_destination_11> REO remaps this 3945 <enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13> 3946 REO remaps this 3947 <enum 14 reo_destination_14> REO remaps this 3948 <enum 15 reo_destination_15> REO remaps this 3949 <enum 16 reo_destination_16> REO remaps this 3950 <enum 17 reo_destination_17> REO remaps this 3951 <enum 18 reo_destination_18> REO remaps this 3952 <enum 19 reo_destination_19> REO remaps this 3953 <enum 20 reo_destination_20> REO remaps this 3954 <enum 21 reo_destination_21> REO remaps this 3955 <enum 22 reo_destination_22> REO remaps this 3956 <enum 23 reo_destination_23> REO remaps this 3957 <enum 24 reo_destination_24> REO remaps this 3958 <enum 25 reo_destination_25> REO remaps this 3959 <enum 26 reo_destination_26> REO remaps this 3960 <enum 27 reo_destination_27> REO remaps this 3961 <enum 28 reo_destination_28> REO remaps this 3962 <enum 29 reo_destination_29> REO remaps this 3963 <enum 30 reo_destination_30> REO remaps this 3964 <enum 31 reo_destination_31> REO remaps this 3965 3966 <legal all> 3967 */ 3968 3969 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c 3970 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 3971 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 3972 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 3973 3974 3975 /* Description SERVICE_CODE 3976 3977 Opaque service code between PPE and Wi-Fi 3978 3979 This field gets passed on by REO to PPE in the EDMA descriptor 3980 ('REO_TO_PPE_RING'). 3981 3982 <legal all> 3983 */ 3984 3985 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c 3986 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 3987 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 3988 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 3989 3990 3991 /* Description PRIORITY_VALID 3992 3993 This field gets passed on by REO to PPE in the EDMA descriptor 3994 ('REO_TO_PPE_RING'). 3995 3996 <legal all> 3997 */ 3998 3999 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c 4000 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 4001 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 4002 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 4003 4004 4005 /* Description DATA_OFFSET 4006 4007 The offset to Rx packet data within the buffer (including 4008 Rx DMA offset programming and L3 header padding inserted 4009 by Rx OLE). 4010 4011 This field gets passed on by REO to PPE in the EDMA descriptor 4012 ('REO_TO_PPE_RING'). 4013 4014 <legal all> 4015 */ 4016 4017 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c 4018 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 4019 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 4020 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 4021 4022 4023 /* Description SRC_LINK_ID 4024 4025 Consumer: SW 4026 Producer: RXDMA 4027 4028 Set to the link ID of the PMAC that received the frame 4029 <legal all> 4030 */ 4031 4032 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c 4033 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 4034 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 4035 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 4036 4037 4038 /* Description RESERVED_0A 4039 4040 <legal 0> 4041 */ 4042 4043 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c 4044 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 4045 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 4046 #define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 4047 4048 4049 4050 #endif // RX_MSDU_LINK 4051