1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_PPDU_END_USER_STATS_H_ 18 #define _RX_PPDU_END_USER_STATS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_rxpcu_classification_overview.h" 23 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 24 25 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 26 27 28 struct rx_ppdu_end_user_stats { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct rx_rxpcu_classification_overview rxpcu_classification_details; 31 uint32_t sta_full_aid : 13, // [12:0] 32 mcs : 4, // [16:13] 33 nss : 3, // [19:17] 34 expected_response_ack_or_ba : 1, // [20:20] 35 reserved_1a : 11; // [31:21] 36 uint32_t sw_peer_id : 16, // [15:0] 37 mpdu_cnt_fcs_err : 11, // [26:16] 38 sw2rxdma0_buf_source_used : 1, // [27:27] 39 fw2rxdma_pmac0_buf_source_used : 1, // [28:28] 40 sw2rxdma1_buf_source_used : 1, // [29:29] 41 sw2rxdma_exception_buf_source_used : 1, // [30:30] 42 fw2rxdma_pmac1_buf_source_used : 1; // [31:31] 43 uint32_t mpdu_cnt_fcs_ok : 11, // [10:0] 44 frame_control_info_valid : 1, // [11:11] 45 qos_control_info_valid : 1, // [12:12] 46 ht_control_info_valid : 1, // [13:13] 47 data_sequence_control_info_valid : 1, // [14:14] 48 ht_control_info_null_valid : 1, // [15:15] 49 rxdma2fw_pmac1_ring_used : 1, // [16:16] 50 rxdma2reo_ring_used : 1, // [17:17] 51 rxdma2fw_pmac0_ring_used : 1, // [18:18] 52 rxdma2sw_ring_used : 1, // [19:19] 53 rxdma_release_ring_used : 1, // [20:20] 54 ht_control_field_pkt_type : 4, // [24:21] 55 rxdma2reo_remote0_ring_used : 1, // [25:25] 56 rxdma2reo_remote1_ring_used : 1, // [26:26] 57 reserved_3b : 5; // [31:27] 58 uint32_t ast_index : 16, // [15:0] 59 frame_control_field : 16; // [31:16] 60 uint32_t first_data_seq_ctrl : 16, // [15:0] 61 qos_control_field : 16; // [31:16] 62 uint32_t ht_control_field : 32; // [31:0] 63 uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] 64 uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] 65 uint32_t udp_msdu_count : 16, // [15:0] 66 tcp_msdu_count : 16; // [31:16] 67 uint32_t other_msdu_count : 16, // [15:0] 68 tcp_ack_msdu_count : 16; // [31:16] 69 uint32_t sw_response_reference_ptr : 32; // [31:0] 70 uint32_t received_qos_data_tid_bitmap : 16, // [15:0] 71 received_qos_data_tid_eosp_bitmap : 16; // [31:16] 72 uint32_t qosctrl_15_8_tid0 : 8, // [7:0] 73 qosctrl_15_8_tid1 : 8, // [15:8] 74 qosctrl_15_8_tid2 : 8, // [23:16] 75 qosctrl_15_8_tid3 : 8; // [31:24] 76 uint32_t qosctrl_15_8_tid4 : 8, // [7:0] 77 qosctrl_15_8_tid5 : 8, // [15:8] 78 qosctrl_15_8_tid6 : 8, // [23:16] 79 qosctrl_15_8_tid7 : 8; // [31:24] 80 uint32_t qosctrl_15_8_tid8 : 8, // [7:0] 81 qosctrl_15_8_tid9 : 8, // [15:8] 82 qosctrl_15_8_tid10 : 8, // [23:16] 83 qosctrl_15_8_tid11 : 8; // [31:24] 84 uint32_t qosctrl_15_8_tid12 : 8, // [7:0] 85 qosctrl_15_8_tid13 : 8, // [15:8] 86 qosctrl_15_8_tid14 : 8, // [23:16] 87 qosctrl_15_8_tid15 : 8; // [31:24] 88 uint32_t mpdu_ok_byte_count : 25, // [24:0] 89 ampdu_delim_ok_count_6_0 : 7; // [31:25] 90 uint32_t ampdu_delim_err_count : 25, // [24:0] 91 ampdu_delim_ok_count_13_7 : 7; // [31:25] 92 uint32_t mpdu_err_byte_count : 25, // [24:0] 93 ampdu_delim_ok_count_20_14 : 7; // [31:25] 94 uint32_t non_consecutive_delimiter_err : 16, // [15:0] 95 retried_msdu_count : 16; // [31:16] 96 uint32_t ht_control_null_field : 32; // [31:0] 97 uint32_t sw_response_reference_ptr_ext : 32; // [31:0] 98 uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 99 frame_control_info_null_valid : 1, // [1:1] 100 frame_control_field_null : 16, // [17:2] 101 retried_mpdu_count : 11, // [28:18] 102 reserved_23a : 3; // [31:29] 103 uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] 104 sw_frame_group_id : 7, // [8:2] 105 reserved_24a : 4, // [12:9] 106 frame_control_info_mgmt_ctrl_valid : 1, // [13:13] 107 mac_addr_ad2_valid : 1, // [14:14] 108 mcast_bcast : 1, // [15:15] 109 frame_control_field_mgmt_ctrl : 16; // [31:16] 110 uint32_t user_ppdu_len : 24, // [23:0] 111 reserved_25a : 8; // [31:24] 112 uint32_t mac_addr_ad2_31_0 : 32; // [31:0] 113 uint32_t mac_addr_ad2_47_32 : 16, // [15:0] 114 amsdu_msdu_count : 16; // [31:16] 115 uint32_t non_amsdu_msdu_count : 16, // [15:0] 116 ucast_msdu_count : 16; // [31:16] 117 uint32_t bcast_msdu_count : 16, // [15:0] 118 mcast_bcast_msdu_count : 16; // [31:16] 119 #else 120 struct rx_rxpcu_classification_overview rxpcu_classification_details; 121 uint32_t reserved_1a : 11, // [31:21] 122 expected_response_ack_or_ba : 1, // [20:20] 123 nss : 3, // [19:17] 124 mcs : 4, // [16:13] 125 sta_full_aid : 13; // [12:0] 126 uint32_t fw2rxdma_pmac1_buf_source_used : 1, // [31:31] 127 sw2rxdma_exception_buf_source_used : 1, // [30:30] 128 sw2rxdma1_buf_source_used : 1, // [29:29] 129 fw2rxdma_pmac0_buf_source_used : 1, // [28:28] 130 sw2rxdma0_buf_source_used : 1, // [27:27] 131 mpdu_cnt_fcs_err : 11, // [26:16] 132 sw_peer_id : 16; // [15:0] 133 uint32_t reserved_3b : 5, // [31:27] 134 rxdma2reo_remote1_ring_used : 1, // [26:26] 135 rxdma2reo_remote0_ring_used : 1, // [25:25] 136 ht_control_field_pkt_type : 4, // [24:21] 137 rxdma_release_ring_used : 1, // [20:20] 138 rxdma2sw_ring_used : 1, // [19:19] 139 rxdma2fw_pmac0_ring_used : 1, // [18:18] 140 rxdma2reo_ring_used : 1, // [17:17] 141 rxdma2fw_pmac1_ring_used : 1, // [16:16] 142 ht_control_info_null_valid : 1, // [15:15] 143 data_sequence_control_info_valid : 1, // [14:14] 144 ht_control_info_valid : 1, // [13:13] 145 qos_control_info_valid : 1, // [12:12] 146 frame_control_info_valid : 1, // [11:11] 147 mpdu_cnt_fcs_ok : 11; // [10:0] 148 uint32_t frame_control_field : 16, // [31:16] 149 ast_index : 16; // [15:0] 150 uint32_t qos_control_field : 16, // [31:16] 151 first_data_seq_ctrl : 16; // [15:0] 152 uint32_t ht_control_field : 32; // [31:0] 153 uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] 154 uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] 155 uint32_t tcp_msdu_count : 16, // [31:16] 156 udp_msdu_count : 16; // [15:0] 157 uint32_t tcp_ack_msdu_count : 16, // [31:16] 158 other_msdu_count : 16; // [15:0] 159 uint32_t sw_response_reference_ptr : 32; // [31:0] 160 uint32_t received_qos_data_tid_eosp_bitmap : 16, // [31:16] 161 received_qos_data_tid_bitmap : 16; // [15:0] 162 uint32_t qosctrl_15_8_tid3 : 8, // [31:24] 163 qosctrl_15_8_tid2 : 8, // [23:16] 164 qosctrl_15_8_tid1 : 8, // [15:8] 165 qosctrl_15_8_tid0 : 8; // [7:0] 166 uint32_t qosctrl_15_8_tid7 : 8, // [31:24] 167 qosctrl_15_8_tid6 : 8, // [23:16] 168 qosctrl_15_8_tid5 : 8, // [15:8] 169 qosctrl_15_8_tid4 : 8; // [7:0] 170 uint32_t qosctrl_15_8_tid11 : 8, // [31:24] 171 qosctrl_15_8_tid10 : 8, // [23:16] 172 qosctrl_15_8_tid9 : 8, // [15:8] 173 qosctrl_15_8_tid8 : 8; // [7:0] 174 uint32_t qosctrl_15_8_tid15 : 8, // [31:24] 175 qosctrl_15_8_tid14 : 8, // [23:16] 176 qosctrl_15_8_tid13 : 8, // [15:8] 177 qosctrl_15_8_tid12 : 8; // [7:0] 178 uint32_t ampdu_delim_ok_count_6_0 : 7, // [31:25] 179 mpdu_ok_byte_count : 25; // [24:0] 180 uint32_t ampdu_delim_ok_count_13_7 : 7, // [31:25] 181 ampdu_delim_err_count : 25; // [24:0] 182 uint32_t ampdu_delim_ok_count_20_14 : 7, // [31:25] 183 mpdu_err_byte_count : 25; // [24:0] 184 uint32_t retried_msdu_count : 16, // [31:16] 185 non_consecutive_delimiter_err : 16; // [15:0] 186 uint32_t ht_control_null_field : 32; // [31:0] 187 uint32_t sw_response_reference_ptr_ext : 32; // [31:0] 188 uint32_t reserved_23a : 3, // [31:29] 189 retried_mpdu_count : 11, // [28:18] 190 frame_control_field_null : 16, // [17:2] 191 frame_control_info_null_valid : 1, // [1:1] 192 corrupted_due_to_fifo_delay : 1; // [0:0] 193 uint32_t frame_control_field_mgmt_ctrl : 16, // [31:16] 194 mcast_bcast : 1, // [15:15] 195 mac_addr_ad2_valid : 1, // [14:14] 196 frame_control_info_mgmt_ctrl_valid : 1, // [13:13] 197 reserved_24a : 4, // [12:9] 198 sw_frame_group_id : 7, // [8:2] 199 rxpcu_mpdu_filter_in_category : 2; // [1:0] 200 uint32_t reserved_25a : 8, // [31:24] 201 user_ppdu_len : 24; // [23:0] 202 uint32_t mac_addr_ad2_31_0 : 32; // [31:0] 203 uint32_t amsdu_msdu_count : 16, // [31:16] 204 mac_addr_ad2_47_32 : 16; // [15:0] 205 uint32_t ucast_msdu_count : 16, // [31:16] 206 non_amsdu_msdu_count : 16; // [15:0] 207 uint32_t mcast_bcast_msdu_count : 16, // [31:16] 208 bcast_msdu_count : 16; // [15:0] 209 #endif 210 }; 211 212 213 /* Description RXPCU_CLASSIFICATION_DETAILS 214 215 Details related to what RXPCU classification types of MPDUs 216 have been received 217 */ 218 219 220 /* Description FILTER_PASS_MPDUS 221 222 When set, at least one Filter Pass MPDU has been received. 223 FCS might or might not have been passing. 224 225 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 226 this field is the "OR of all the users. 227 <legal all> 228 */ 229 230 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 231 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 232 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 233 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 234 235 236 /* Description FILTER_PASS_MPDUS_FCS_OK 237 238 When set, at least one Filter Pass MPDU has been received 239 that has a correct FCS. 240 241 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 242 this field is the "OR of all the users. 243 244 <legal all> 245 */ 246 247 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 248 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 249 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 250 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 251 252 253 /* Description MONITOR_DIRECT_MPDUS 254 255 When set, at least one Monitor Direct MPDU has been received. 256 FCS might or might not have been passing 257 258 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 259 this field is the "OR of all the users. 260 <legal all> 261 */ 262 263 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 264 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 265 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 266 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 267 268 269 /* Description MONITOR_DIRECT_MPDUS_FCS_OK 270 271 When set, at least one Monitor Direct MPDU has been received 272 that has a correct FCS. 273 274 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 275 this field is the "OR of all the users. 276 277 <legal all> 278 */ 279 280 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 281 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 282 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 283 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 284 285 286 /* Description MONITOR_OTHER_MPDUS 287 288 When set, at least one Monitor Direct MPDU has been received. 289 FCS might or might not have been passing. 290 291 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 292 this field is the "OR of all the users. 293 <legal all> 294 */ 295 296 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 297 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 298 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 299 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 300 301 302 /* Description MONITOR_OTHER_MPDUS_FCS_OK 303 304 When set, at least one Monitor Direct MPDU has been received 305 that has a correct FCS. 306 307 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 308 this field is the "OR of all the users. 309 <legal all> 310 */ 311 312 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 313 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 314 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 315 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 316 317 318 /* Description PHYRX_ABORT_RECEIVED 319 320 When set, PPDU reception was aborted by the PHY 321 <legal all> 322 */ 323 324 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 325 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 326 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 327 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 328 329 330 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS 331 332 When set, at least one 'Filter Pass Monitor Override' MPDU 333 has been received. FCS might or might not have been passing. 334 335 336 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 337 this field is the "OR of all the users. 338 <legal all> 339 */ 340 341 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 342 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 343 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 344 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 345 346 347 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK 348 349 When set, at least one 'Filter Pass Monitor Override' MPDU 350 has been received that has a correct FCS. 351 352 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 353 this field is the "OR of all the users. 354 355 <legal all> 356 */ 357 358 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 359 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 360 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 361 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 362 363 364 /* Description RESERVED_0 365 366 <legal 0> 367 */ 368 369 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 370 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 371 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 372 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 373 374 375 /* Description PHY_PPDU_ID 376 377 A ppdu counter value that PHY increments for every PPDU 378 received. The counter value wraps around 379 <legal all> 380 */ 381 382 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 383 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 384 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 385 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 386 387 388 /* Description STA_FULL_AID 389 390 Consumer: FW 391 Producer: RXPCU 392 393 The full AID of this station. 394 395 <legal all> 396 */ 397 398 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 399 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 400 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 401 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 402 403 404 /* Description MCS 405 406 MCS of the received frame 407 408 For details, refer to MCS_TYPE description 409 Note: This is "rate" in case of 11a/11b 410 411 <legal all> 412 */ 413 414 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 415 #define RX_PPDU_END_USER_STATS_MCS_LSB 45 416 #define RX_PPDU_END_USER_STATS_MCS_MSB 48 417 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 418 419 420 /* Description NSS 421 422 Number of spatial streams. 423 424 NOTE: RXPCU derives this from the 'Mimo_ss_bitmap' 425 426 <enum 0 1_spatial_stream>Single spatial stream 427 <enum 1 2_spatial_streams>2 spatial streams 428 <enum 2 3_spatial_streams>3 spatial streams 429 <enum 3 4_spatial_streams>4 spatial streams 430 <enum 4 5_spatial_streams>5 spatial streams 431 <enum 5 6_spatial_streams>6 spatial streams 432 <enum 6 7_spatial_streams>7 spatial streams 433 <enum 7 8_spatial_streams>8 spatial streams 434 */ 435 436 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 437 #define RX_PPDU_END_USER_STATS_NSS_LSB 49 438 #define RX_PPDU_END_USER_STATS_NSS_MSB 51 439 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 440 441 442 /* Description EXPECTED_RESPONSE_ACK_OR_BA 443 444 When set, it indicates an Ack or BA matching 'EXPECTED_RESPONSE' 445 from TXPCU 446 */ 447 448 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 449 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 450 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 451 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 452 453 454 /* Description RESERVED_1A 455 456 <legal 0> 457 */ 458 459 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 460 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 461 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 462 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 463 464 465 /* Description SW_PEER_ID 466 467 This field indicates a unique peer identifier, set from 468 the field 'sw_peer_id' in the AST entry corresponding to 469 this MPDU. It is provided by RXPCU. 470 A value of 0xFFFF indicates no AST entry was found or no 471 AST search was performed. 472 <legal all> 473 */ 474 475 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 476 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 477 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 478 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff 479 480 481 /* Description MPDU_CNT_FCS_ERR 482 483 The number of MPDUs received from this STA in this PPDU 484 with FCS errors 485 <legal all> 486 */ 487 488 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 489 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 490 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 491 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 492 493 494 /* Description SW2RXDMA0_BUF_SOURCE_USED 495 496 Field filled in by RXDMA 497 498 When set, RXDMA has used the sw2rxdma0 buffer ring as source 499 for at least one of the frames in this PPDU. 500 */ 501 502 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 503 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 504 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 505 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 506 507 508 /* Description FW2RXDMA_PMAC0_BUF_SOURCE_USED 509 510 Field filled in by RXDMA 511 512 When set, RXDMA has used the fw2rxdma buffer ring for PMAC0 513 as source for at least one of the frames in this PPDU. 514 */ 515 516 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 517 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 518 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 519 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 520 521 522 /* Description SW2RXDMA1_BUF_SOURCE_USED 523 524 Field filled in by RXDMA 525 526 When set, RXDMA has used the sw2rxdma1 buffer ring as source 527 for at least one of the frames in this PPDU. 528 */ 529 530 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 531 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 532 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 533 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 534 535 536 /* Description SW2RXDMA_EXCEPTION_BUF_SOURCE_USED 537 538 Field filled in by RXDMA 539 540 When set, RXDMA has used the sw2rxdma_exception buffer ring 541 as source for at least one of the frames in this PPDU. 542 */ 543 544 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 545 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 546 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 547 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 548 549 550 /* Description FW2RXDMA_PMAC1_BUF_SOURCE_USED 551 552 Field filled in by RXDMA 553 554 When set, RXDMA has used the fw2rxdma buffer ring for PMAC1 555 as source for at least one of the frames in this PPDU. 556 */ 557 558 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 559 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 560 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 561 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 562 563 564 /* Description MPDU_CNT_FCS_OK 565 566 The number of MPDUs received from this STA in this PPDU 567 with correct FCS 568 <legal all> 569 */ 570 571 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 572 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 573 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 574 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 575 576 577 /* Description FRAME_CONTROL_INFO_VALID 578 579 When set, the frame_control_info field contains valid information 580 581 <legal all> 582 */ 583 584 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 585 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 586 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 587 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 588 589 590 /* Description QOS_CONTROL_INFO_VALID 591 592 When set, the QoS_control_info field contains valid information 593 594 <legal all> 595 */ 596 597 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 598 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 599 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 600 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 601 602 603 /* Description HT_CONTROL_INFO_VALID 604 605 When set, the HT_control_field contains valid information 606 607 <legal all> 608 */ 609 610 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 611 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 612 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 613 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 614 615 616 /* Description DATA_SEQUENCE_CONTROL_INFO_VALID 617 618 When set, the First_data_seq_ctrl field contains valid information 619 620 <legal all> 621 */ 622 623 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 624 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 625 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 626 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 627 628 629 /* Description HT_CONTROL_INFO_NULL_VALID 630 631 When set, the HT_control_NULL_field contains valid information 632 633 <legal all> 634 */ 635 636 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 637 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 638 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 639 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 640 641 642 /* Description RXDMA2FW_PMAC1_RING_USED 643 644 Field filled in by RXDMA 645 646 Set when at least one frame during this PPDU got pushed 647 to this ring by RXDMA 648 */ 649 650 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 651 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 652 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 653 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 654 655 656 /* Description RXDMA2REO_RING_USED 657 658 Field filled in by RXDMA 659 660 Set when at least one frame during this PPDU got pushed 661 to this ring by RXDMA 662 */ 663 664 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 665 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 666 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 667 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 668 669 670 /* Description RXDMA2FW_PMAC0_RING_USED 671 672 Field filled in by RXDMA 673 674 Set when at least one frame during this PPDU got pushed 675 to this ring by RXDMA 676 */ 677 678 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 679 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 680 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 681 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 682 683 684 /* Description RXDMA2SW_RING_USED 685 686 Field filled in by RXDMA 687 688 Set when at least one frame during this PPDU got pushed 689 to this ring by RXDMA 690 */ 691 692 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 693 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 694 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 695 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 696 697 698 /* Description RXDMA_RELEASE_RING_USED 699 700 Field filled in by RXDMA 701 702 Set when at least one frame during this PPDU got pushed 703 to this ring by RXDMA 704 */ 705 706 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 707 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 708 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 709 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 710 711 712 /* Description HT_CONTROL_FIELD_PKT_TYPE 713 714 Field only valid when HT_control_info_valid or HT_control_info_NULL_valid 715 is set. 716 717 Indicates what the PHY receive type was for receiving this 718 frame. Can help determine if the HT_CONTROL field shall 719 be interpreted as HT/VHT or HE. 720 721 NOTE: later on in the 11ax IEEE spec a bit within the HT 722 control field was introduced that explicitly indicated 723 how to interpret the HT control field.... As HT, VHT, or 724 HE. 725 726 <enum 0 dot11a>802.11a PPDU type 727 <enum 1 dot11b>802.11b PPDU type 728 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 729 <enum 3 dot11ac>802.11ac PPDU type 730 <enum 4 dot11ax>802.11ax PPDU type 731 <enum 5 dot11ba>802.11ba (WUR) PPDU type 732 <enum 6 dot11be>802.11be PPDU type 733 <enum 7 dot11az>802.11az (ranging) PPDU type 734 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 735 & aborted) 736 */ 737 738 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 739 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 740 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 741 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 742 743 744 /* Description RXDMA2REO_REMOTE0_RING_USED 745 746 Field filled in by RXDMA 747 748 Set when at least one frame during this PPDU got pushed 749 to this ring by RXDMA 750 */ 751 752 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 753 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 754 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 755 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 756 757 758 /* Description RXDMA2REO_REMOTE1_RING_USED 759 760 Field filled in by RXDMA 761 762 Set when at least one frame during this PPDU got pushed 763 to this ring by RXDMA 764 */ 765 766 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 767 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 768 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 769 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 770 771 772 /* Description RESERVED_3B 773 774 <legal 0> 775 */ 776 777 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 778 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 779 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 780 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 781 782 783 /* Description AST_INDEX 784 785 This field indicates the index of the AST entry corresponding 786 to this MPDU. It is provided by the GSE module instantiated 787 in RXPCU. 788 A value of 0xFFFF indicates an invalid AST index, meaning 789 that No AST entry was found or NO AST search was performed 790 791 <legal all> 792 */ 793 794 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 795 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 796 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 797 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff 798 799 800 /* Description FRAME_CONTROL_FIELD 801 802 Field only valid when Frame_control_info_valid is set. 803 804 Last successfully received Frame_control field of data frame 805 (excluding Data NULL/ QoS Null) for this user 806 Mainly used to track the PM state of the transmitted device 807 808 809 NOTE: only data frame info is needed, as control and management 810 frames are already routed to the FW. 811 <legal all> 812 */ 813 814 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 815 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 816 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 817 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 818 819 820 /* Description FIRST_DATA_SEQ_CTRL 821 822 Field only valid when Data_sequence_control_info_valid is 823 set. 824 825 Sequence control field of the first data frame (excluding 826 Data NULL or QoS Data null) received for this user with 827 correct FCS 828 829 NOTE: only data frame info is needed, as control and management 830 frames are already routed to the FW. 831 <legal all> 832 */ 833 834 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 835 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 836 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 837 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 838 839 840 /* Description QOS_CONTROL_FIELD 841 842 Field only valid when QoS_control_info_valid is set. 843 844 Last successfully received QoS_control field of data frame 845 (excluding Data NULL/ QoS Null) for this user 846 847 Note that in case of multi TID, this field can only reflect 848 the last properly received MPDU, and thus can not indicate 849 all potentially different TIDs that had been received earlier. 850 851 852 There are however per TID fields, that will contain among 853 other things all buffer status info: See 854 QoSCtrl_15_8_tid??? 855 <legal all> 856 */ 857 858 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 859 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 860 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 861 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 862 863 864 /* Description HT_CONTROL_FIELD 865 866 Field only valid when HT_control_info_valid is set. 867 868 Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL 869 field of data frames, excluding QoS Null frames for this 870 user. 871 872 NOTE: HT control fields from QoS Null frames are captured 873 in field HT_control_NULL_field 874 <legal all> 875 */ 876 877 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 878 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 879 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 880 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 881 882 883 /* Description FCS_OK_BITMAP_31_0 884 885 Bitmap indicates in order of received MPDUs, which MPDUs 886 had an passing FCS or had an error. 887 1: FCS OK 888 0: FCS error 889 <legal all> 890 */ 891 892 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 893 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 894 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 895 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 896 897 898 /* Description FCS_OK_BITMAP_63_32 899 900 Bitmap indicates in order of received MPDUs, which MPDUs 901 had an passing FCS or had an error. 902 1: FCS OK 903 0: FCS error 904 905 NOTE: for users 0, 1, 2 and 3, additional bitmap info (up 906 to 256 bitmap window) is provided in RX_PPDU_END_USER_STATS_EXT 907 TLV 908 <legal all> 909 */ 910 911 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 912 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 913 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 914 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff 915 916 917 /* Description UDP_MSDU_COUNT 918 919 Field filled in by RX OLE 920 Set to 0 by RXPCU 921 922 The number of MSDUs that are part of MPDUs without FCS error, 923 that contain UDP frames. 924 <legal all> 925 */ 926 927 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 928 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 929 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 930 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 931 932 933 /* Description TCP_MSDU_COUNT 934 935 Field filled in by RX OLE 936 Set to 0 by RXPCU 937 938 The number of MSDUs that are part of MPDUs without FCS error, 939 that contain TCP frames. 940 941 (Note: This does NOT include TCP-ACK) 942 <legal all> 943 */ 944 945 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 946 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 947 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 948 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 949 950 951 /* Description OTHER_MSDU_COUNT 952 953 Field filled in by RX OLE 954 Set to 0 by RXPCU 955 956 The number of MSDUs that are part of MPDUs without FCS error, 957 that contain neither UDP or TCP frames. 958 959 Includes Management and control frames. 960 961 <legal all> 962 */ 963 964 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 965 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 966 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 967 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff 968 969 970 /* Description TCP_ACK_MSDU_COUNT 971 972 Field filled in by RX OLE 973 Set to 0 by RXPCU 974 975 The number of MSDUs that are part of MPDUs without FCS error, 976 that contain TCP ack frames. 977 <legal all> 978 */ 979 980 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 981 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 982 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 983 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 984 985 986 /* Description SW_RESPONSE_REFERENCE_PTR 987 988 Pointer that SW uses to refer back to an expected response 989 reception. Used for Rate adaptation purposes. 990 When a reception occurs that is not tied to an expected 991 response, this field is set to 0x0. 992 993 Note: further on in this TLV there is also the field: Sw_response_reference_ptr_ext. 994 995 <legal all> 996 */ 997 998 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 999 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 1000 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 1001 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 1002 1003 1004 /* Description RECEIVED_QOS_DATA_TID_BITMAP 1005 1006 Whenever a frame is received that contains a QoS control 1007 field (that includes QoS Data and/or QoS Null), the bit 1008 in this field that corresponds to the received TID shall 1009 be set. 1010 ...Bitmap[0] = TID0 1011 ...Bitmap[1] = TID1 1012 Etc. 1013 <legal all> 1014 */ 1015 1016 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 1017 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 1018 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 1019 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff 1020 1021 1022 /* Description RECEIVED_QOS_DATA_TID_EOSP_BITMAP 1023 1024 Field initialized to 0 1025 For every QoS Data frame that is correctly received, the 1026 EOSP bit of that frame is copied over into the corresponding 1027 TID related field. 1028 Note that this implies that the bits here represent the 1029 EOSP bit status for each TID of the last MPDU received for 1030 that TID. 1031 1032 received TID shall be set. 1033 ...eosp_bitmap[0] = eosp of TID0 1034 ...eosp_bitmap[1] = eosp of TID1 1035 Etc. 1036 <legal all> 1037 */ 1038 1039 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 1040 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 1041 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 1042 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 1043 1044 1045 /* Description QOSCTRL_15_8_TID0 1046 1047 Field only valid when Received_qos_data_tid_bitmap[0] is 1048 set 1049 1050 QoS control field bits 15-8 of the last properly received 1051 MPDU with a QoS control field embedded, with TID == 0 1052 */ 1053 1054 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 1055 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 1056 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 1057 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 1058 1059 1060 /* Description QOSCTRL_15_8_TID1 1061 1062 Field only valid when Received_qos_data_tid_bitmap[1] is 1063 set 1064 1065 QoS control field bits 15-8 of the last properly received 1066 MPDU with a QoS control field embedded, with TID == 1 1067 */ 1068 1069 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 1070 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 1071 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 1072 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 1073 1074 1075 /* Description QOSCTRL_15_8_TID2 1076 1077 Field only valid when Received_qos_data_tid_bitmap[2] is 1078 set 1079 1080 QoS control field bits 15-8 of the last properly received 1081 MPDU with a QoS control field embedded, with TID == 2 1082 */ 1083 1084 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 1085 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 1086 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 1087 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 1088 1089 1090 /* Description QOSCTRL_15_8_TID3 1091 1092 Field only valid when Received_qos_data_tid_bitmap[3] is 1093 set 1094 1095 QoS control field bits 15-8 of the last properly received 1096 MPDU with a QoS control field embedded, with TID == 3 1097 */ 1098 1099 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 1100 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 1101 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 1102 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 1103 1104 1105 /* Description QOSCTRL_15_8_TID4 1106 1107 Field only valid when Received_qos_data_tid_bitmap[4] is 1108 set 1109 1110 QoS control field bits 15-8 of the last properly received 1111 MPDU with a QoS control field embedded, with TID == 4 1112 */ 1113 1114 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 1115 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 1116 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 1117 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff 1118 1119 1120 /* Description QOSCTRL_15_8_TID5 1121 1122 Field only valid when Received_qos_data_tid_bitmap[5] is 1123 set 1124 1125 QoS control field bits 15-8 of the last properly received 1126 MPDU with a QoS control field embedded, with TID == 5 1127 */ 1128 1129 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 1130 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 1131 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 1132 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 1133 1134 1135 /* Description QOSCTRL_15_8_TID6 1136 1137 Field only valid when Received_qos_data_tid_bitmap[6] is 1138 set 1139 1140 QoS control field bits 15-8 of the last properly received 1141 MPDU with a QoS control field embedded, with TID == 6 1142 */ 1143 1144 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 1145 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 1146 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 1147 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 1148 1149 1150 /* Description QOSCTRL_15_8_TID7 1151 1152 Field only valid when Received_qos_data_tid_bitmap[7] is 1153 set 1154 1155 QoS control field bits 15-8 of the last properly received 1156 MPDU with a QoS control field embedded, with TID == 7 1157 */ 1158 1159 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 1160 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 1161 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 1162 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 1163 1164 1165 /* Description QOSCTRL_15_8_TID8 1166 1167 Field only valid when Received_qos_data_tid_bitmap[8] is 1168 set 1169 1170 QoS control field bits 15-8 of the last properly received 1171 MPDU with a QoS control field embedded, with TID == 8 1172 */ 1173 1174 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 1175 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 1176 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 1177 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 1178 1179 1180 /* Description QOSCTRL_15_8_TID9 1181 1182 Field only valid when Received_qos_data_tid_bitmap[9] is 1183 set 1184 1185 QoS control field bits 15-8 of the last properly received 1186 MPDU with a QoS control field embedded, with TID == 9 1187 */ 1188 1189 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 1190 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 1191 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 1192 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 1193 1194 1195 /* Description QOSCTRL_15_8_TID10 1196 1197 Field only valid when Received_qos_data_tid_bitmap[10] is 1198 set 1199 1200 QoS control field bits 15-8 of the last properly received 1201 MPDU with a QoS control field embedded, with TID == 10 1202 1203 */ 1204 1205 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 1206 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 1207 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 1208 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 1209 1210 1211 /* Description QOSCTRL_15_8_TID11 1212 1213 Field only valid when Received_qos_data_tid_bitmap[11] is 1214 set 1215 1216 QoS control field bits 15-8 of the last properly received 1217 MPDU with a QoS control field embedded, with TID == 11 1218 1219 */ 1220 1221 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 1222 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 1223 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 1224 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 1225 1226 1227 /* Description QOSCTRL_15_8_TID12 1228 1229 Field only valid when Received_qos_data_tid_bitmap[12] is 1230 set 1231 1232 QoS control field bits 15-8 of the last properly received 1233 MPDU with a QoS control field embedded, with TID == 12 1234 1235 */ 1236 1237 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 1238 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 1239 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 1240 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff 1241 1242 1243 /* Description QOSCTRL_15_8_TID13 1244 1245 Field only valid when Received_qos_data_tid_bitmap[13] is 1246 set 1247 1248 QoS control field bits 15-8 of the last properly received 1249 MPDU with a QoS control field embedded, with TID == 13 1250 1251 */ 1252 1253 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 1254 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 1255 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 1256 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 1257 1258 1259 /* Description QOSCTRL_15_8_TID14 1260 1261 Field only valid when Received_qos_data_tid_bitmap[14] is 1262 set 1263 1264 QoS control field bits 15-8 of the last properly received 1265 MPDU with a QoS control field embedded, with TID == 14 1266 1267 */ 1268 1269 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 1270 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 1271 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 1272 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 1273 1274 1275 /* Description QOSCTRL_15_8_TID15 1276 1277 Field only valid when Received_qos_data_tid_bitmap[15] is 1278 set 1279 1280 QoS control field bits 15-8 of the last properly received 1281 MPDU with a QoS control field embedded, with TID == 15 1282 1283 */ 1284 1285 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 1286 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 1287 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 1288 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 1289 1290 1291 /* Description MPDU_OK_BYTE_COUNT 1292 1293 The number of bytes received within an MPDU for this user 1294 with correct FCS. This includes the FCS field 1295 1296 NOTE: 1297 The sum of the four fields..... 1298 Mpdu_ok_byte_count + 1299 mpdu_err_byte_count + 1300 (Ampdu_delim_ok_count x 4) + (Ampdu_delim_err_count x 4) 1301 1302 .....is the total number of bytes that were received for 1303 this user from the PHY. 1304 1305 <legal all> 1306 */ 1307 1308 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 1309 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 1310 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 1311 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 1312 1313 1314 /* Description AMPDU_DELIM_OK_COUNT_6_0 1315 1316 Number of AMPDU delimiter received with correct structure 1317 1318 LSB 7 bits from this counter 1319 1320 Note that this is a delimiter count and not byte count. 1321 To get to the number of bytes occupied by these delimiters, 1322 multiply this number by 4 1323 1324 <legal all> 1325 */ 1326 1327 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 1328 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 1329 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 1330 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 1331 1332 1333 /* Description AMPDU_DELIM_ERR_COUNT 1334 1335 The number of MPDU delimiter errors counted for this user. 1336 1337 1338 Note that this is a delimiter count and not byte count. 1339 To get to the number of bytes occupied by these delimiters, 1340 multiply this number by 4 1341 <legal all> 1342 */ 1343 1344 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 1345 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 1346 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 1347 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff 1348 1349 1350 /* Description AMPDU_DELIM_OK_COUNT_13_7 1351 1352 Number of AMPDU delimiters received with correct structure 1353 1354 Bits 13-7 from this counter 1355 1356 Note that this is a delimiter count and not byte count. 1357 To get to the number of bytes occupied by these delimiters, 1358 multiply this number by 4 1359 <legal all> 1360 */ 1361 1362 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 1363 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 1364 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 1365 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 1366 1367 1368 /* Description MPDU_ERR_BYTE_COUNT 1369 1370 The number of bytes belonging to MPDUs with an FCS error. 1371 This includes the FCS field. 1372 1373 <legal all> 1374 */ 1375 1376 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 1377 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 1378 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 1379 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 1380 1381 1382 /* Description AMPDU_DELIM_OK_COUNT_20_14 1383 1384 Number of AMPDU delimiters received with correct structure 1385 1386 Bits 20-14 from this counter 1387 1388 Note that this is a delimiter count and not byte count. 1389 To get to the number of bytes occupied by these delimiters, 1390 multiply this number by 4 1391 1392 <legal all> 1393 */ 1394 1395 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 1396 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 1397 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 1398 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 1399 1400 1401 /* Description NON_CONSECUTIVE_DELIMITER_ERR 1402 1403 The number of times an MPDU delimiter error is detected 1404 that is not immediately preceded by another MPDU delimiter 1405 also with FCS error. 1406 1407 The counter saturates at 0xFFFF 1408 1409 <legal all> 1410 */ 1411 1412 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 1413 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 1414 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 1415 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff 1416 1417 1418 /* Description RETRIED_MSDU_COUNT 1419 1420 Field filled in by RX OLE 1421 Set to 0 by RXPCU 1422 1423 The number of MSDUs that are part of MPDUs without FCS error, 1424 that have the retry bit set. 1425 <legal all> 1426 */ 1427 1428 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 1429 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 1430 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 1431 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 1432 1433 1434 /* Description HT_CONTROL_NULL_FIELD 1435 1436 Field only valid when HT_control_info_NULL_valid is set. 1437 1438 1439 Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL 1440 field from QoS Null frame for this user. 1441 <legal all> 1442 */ 1443 1444 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 1445 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 1446 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 1447 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 1448 1449 1450 /* Description SW_RESPONSE_REFERENCE_PTR_EXT 1451 1452 Extended Pointer info that SW uses to refer back to an expected 1453 response transmission. Used for Rate adaptation purposes. 1454 1455 When a reception occurs that is not tied to an expected 1456 response, this field is set to 0x0. 1457 1458 Note: earlier on in this TLV there is also the field: Sw_response_reference_ptr. 1459 1460 <legal all> 1461 */ 1462 1463 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 1464 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 1465 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 1466 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff 1467 1468 1469 /* Description CORRUPTED_DUE_TO_FIFO_DELAY 1470 1471 Set if Rx PCU avoided a hang due to SFM delays by writing 1472 a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' 1473 1474 */ 1475 1476 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 1477 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 1478 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 1479 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 1480 1481 1482 /* Description FRAME_CONTROL_INFO_NULL_VALID 1483 1484 When set, Frame_control_field_null contains valid information 1485 1486 <legal all> 1487 */ 1488 1489 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 1490 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 1491 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 1492 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 1493 1494 1495 /* Description FRAME_CONTROL_FIELD_NULL 1496 1497 Field only valid when Frame_control_info_null_valid is set. 1498 1499 1500 Last successfully received Frame_control field of Data Null/QoS 1501 Null for this user, mainly used to track the PM state of 1502 the transmitted device 1503 <legal all> 1504 */ 1505 1506 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 1507 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 1508 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 1509 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 1510 1511 1512 /* Description RETRIED_MPDU_COUNT 1513 1514 Field filled in by RXPCU 1515 1516 The number of MPDUs without FCS error, that have the retry 1517 bit set. 1518 <legal all> 1519 */ 1520 1521 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 1522 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 1523 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 1524 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 1525 1526 1527 /* Description RESERVED_23A 1528 1529 <legal 0> 1530 */ 1531 1532 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 1533 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 1534 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 1535 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 1536 1537 1538 /* Description RXPCU_MPDU_FILTER_IN_CATEGORY 1539 1540 Field indicates what the reason was that the last successfully 1541 received MPDU was allowed to come into the receive path 1542 by RXPCU. 1543 <enum 0 rxpcu_filter_pass> The last MPDU passed the normal 1544 frame filter programming of rxpcu 1545 <enum 1 rxpcu_monitor_client> The last MPDU did NOT pass 1546 the regular frame filter and would have been dropped, were 1547 it not for the frame fitting into the 'monitor_client' 1548 category. 1549 <enum 2 rxpcu_monitor_other> The last MPDU did NOT pass 1550 the regular frame filter and also did not pass the rxpcu_monitor_client 1551 filter. It would have been dropped accept that it did pass 1552 the 'monitor_other' category. 1553 <enum 3 rxpcu_filter_pass_monitor_ovrd> The last MPDU passed 1554 the normal frame filter programming of RXPCU but additionally 1555 fit into the 'monitor_override_client' category. 1556 1557 <legal 0-3> 1558 */ 1559 1560 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 1561 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 1562 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 1563 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 1564 1565 1566 /* Description SW_FRAME_GROUP_ID 1567 1568 SW processes frames based on certain classifications. This 1569 field indicates to what sw classification the last successfully 1570 received MPDU is mapped. 1571 The classification is given in priority order 1572 1573 <enum 0 sw_frame_group_NDP_frame> 1574 1575 <enum 1 sw_frame_group_Multicast_data> 1576 <enum 2 sw_frame_group_Unicast_data> 1577 <enum 3 sw_frame_group_Null_data > This includes mpdus of 1578 type Data Null. 1579 <enum 38 sw_frame_group_QoS_Null_data> This includes QoS 1580 Null frames except in UL MU or TB PPDUs. 1581 <enum 39 sw_frame_group_QoS_Null_data_TB> This includes 1582 QoS Null frames in UL MU or TB PPDUs. 1583 1584 <enum 4 sw_frame_group_mgmt_0000 > 1585 <enum 5 sw_frame_group_mgmt_0001 > 1586 <enum 6 sw_frame_group_mgmt_0010 > 1587 <enum 7 sw_frame_group_mgmt_0011 > 1588 <enum 8 sw_frame_group_mgmt_0100 > 1589 <enum 9 sw_frame_group_mgmt_0101 > 1590 <enum 10 sw_frame_group_mgmt_0110 > 1591 <enum 11 sw_frame_group_mgmt_0111 > 1592 <enum 12 sw_frame_group_mgmt_1000 > 1593 <enum 13 sw_frame_group_mgmt_1001 > 1594 <enum 14 sw_frame_group_mgmt_1010 > 1595 <enum 15 sw_frame_group_mgmt_1011 > 1596 <enum 16 sw_frame_group_mgmt_1100 > 1597 <enum 17 sw_frame_group_mgmt_1101 > 1598 <enum 18 sw_frame_group_mgmt_1110 > 1599 <enum 19 sw_frame_group_mgmt_1111 > 1600 1601 <enum 20 sw_frame_group_ctrl_0000 > 1602 <enum 21 sw_frame_group_ctrl_0001 > 1603 <enum 22 sw_frame_group_ctrl_0010 > 1604 <enum 23 sw_frame_group_ctrl_0011 > 1605 <enum 24 sw_frame_group_ctrl_0100 > 1606 <enum 25 sw_frame_group_ctrl_0101 > 1607 <enum 26 sw_frame_group_ctrl_0110 > 1608 <enum 27 sw_frame_group_ctrl_0111 > 1609 <enum 28 sw_frame_group_ctrl_1000 > 1610 <enum 29 sw_frame_group_ctrl_1001 > 1611 <enum 30 sw_frame_group_ctrl_1010 > 1612 <enum 31 sw_frame_group_ctrl_1011 > 1613 <enum 32 sw_frame_group_ctrl_1100 > 1614 <enum 33 sw_frame_group_ctrl_1101 > 1615 <enum 34 sw_frame_group_ctrl_1110 > 1616 <enum 35 sw_frame_group_ctrl_1111 > 1617 1618 <enum 36 sw_frame_group_unsupported> This covers type 3 1619 and protocol version != 0 1620 1621 <enum 37 sw_frame_group_phy_error> PHY reported an error 1622 1623 1624 <legal 0-39> 1625 */ 1626 1627 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 1628 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 1629 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 1630 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 1631 1632 1633 /* Description RESERVED_24A 1634 1635 <legal 0> 1636 */ 1637 1638 #define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 1639 #define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 1640 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 1641 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 1642 1643 1644 /* Description FRAME_CONTROL_INFO_MGMT_CTRL_VALID 1645 1646 When set, Frame_control_field_mgmt_ctrl contains valid information. 1647 1648 <legal all> 1649 */ 1650 1651 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 1652 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 1653 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 1654 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 1655 1656 1657 /* Description MAC_ADDR_AD2_VALID 1658 1659 When set, the fields mac_addr_ad2_... contain valid information. 1660 1661 <legal all> 1662 */ 1663 1664 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 1665 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 1666 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 1667 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 1668 1669 1670 /* Description MCAST_BCAST 1671 1672 Multicast / broadcast indicator 1673 1674 Only set when the MAC address 1 bit 0 is set indicating 1675 mcast/bcast and the BSSID matches one of the BSSID registers, 1676 for the last successfully received MPDU 1677 <legal all> 1678 */ 1679 1680 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 1681 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 1682 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 1683 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 1684 1685 1686 /* Description FRAME_CONTROL_FIELD_MGMT_CTRL 1687 1688 Field only valid when Frame_control_info_mgmt_ctrl_valid 1689 is set 1690 1691 Last successfully received 'Frame control' field of control 1692 or management frames for this user, mainly used in Rx monitor 1693 mode 1694 <legal all> 1695 */ 1696 1697 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 1698 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 1699 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 1700 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 1701 1702 1703 /* Description USER_PPDU_LEN 1704 1705 The sum of the mpdu_length fields of all the 'RX_MPDU_START' 1706 TLVs generated for this user for this PPDU 1707 */ 1708 1709 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 1710 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 1711 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 1712 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 1713 1714 1715 /* Description RESERVED_25A 1716 1717 <legal 0> 1718 */ 1719 1720 #define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 1721 #define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 1722 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 1723 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 1724 1725 1726 /* Description MAC_ADDR_AD2_31_0 1727 1728 Field only valid when mac_addr_ad2_valid is set 1729 1730 The least significant 4 bytes of the last successfully received 1731 frame's MAC Address AD2 1732 <legal all> 1733 */ 1734 1735 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 1736 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 1737 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 1738 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff 1739 1740 1741 /* Description MAC_ADDR_AD2_47_32 1742 1743 Field only valid when mac_addr_ad2_valid is set 1744 1745 The 2 most significant bytes of the last successfully received 1746 frame's MAC Address AD2 1747 <legal all> 1748 */ 1749 1750 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 1751 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 1752 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 1753 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 1754 1755 1756 /* Description AMSDU_MSDU_COUNT 1757 1758 Field filled in by RX OLE 1759 Set to 0 by RXPCU 1760 1761 The number of MSDUs that are part of A-MSDUs that are part 1762 of MPDUs without FCS error 1763 <legal all> 1764 */ 1765 1766 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 1767 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 1768 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 1769 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 1770 1771 1772 /* Description NON_AMSDU_MSDU_COUNT 1773 1774 Field filled in by RX OLE 1775 Set to 0 by RXPCU 1776 1777 The number of MSDUs that are not part of A-MSDUs that are 1778 part of MPDUs without FCS error 1779 <legal all> 1780 */ 1781 1782 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 1783 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 1784 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 1785 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff 1786 1787 1788 /* Description UCAST_MSDU_COUNT 1789 1790 Field filled in by RX OLE 1791 Set to 0 by RXPCU 1792 1793 The number of MSDUs that are part of MPDUs without FCS error, 1794 that are directed to a unicast destination address 1795 <legal all> 1796 */ 1797 1798 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1799 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 1800 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 1801 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 1802 1803 1804 /* Description BCAST_MSDU_COUNT 1805 1806 Field filled in by RX OLE 1807 Set to 0 by RXPCU 1808 1809 The number of MSDUs that are part of MPDUs without FCS error, 1810 whose destination addresses are broadcast (0xFFFF_FFFF_FFFF) 1811 1812 <legal all> 1813 */ 1814 1815 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1816 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 1817 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 1818 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 1819 1820 1821 /* Description MCAST_BCAST_MSDU_COUNT 1822 1823 Field filled in by RX OLE 1824 Set to 0 by RXPCU 1825 1826 The number of MSDUs that are part of MPDUs without FCS error, 1827 whose destination addresses are either multicast or broadcast 1828 1829 <legal all> 1830 */ 1831 1832 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 1833 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 1834 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 1835 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 1836 1837 1838 1839 #endif // RX_PPDU_END_USER_STATS 1840