1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_PPDU_END_USER_STATS_EXT_H_ 18 #define _RX_PPDU_END_USER_STATS_EXT_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_rxpcu_classification_overview.h" 23 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 24 25 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 26 27 28 struct rx_ppdu_end_user_stats_ext { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct rx_rxpcu_classification_overview rxpcu_classification_details; 31 uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] 32 uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] 33 uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] 34 uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] 35 uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] 36 uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] 37 uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 38 reserved_7a : 31; // [31:1] 39 #else 40 struct rx_rxpcu_classification_overview rxpcu_classification_details; 41 uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] 42 uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] 43 uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] 44 uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] 45 uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] 46 uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] 47 uint32_t reserved_7a : 31, // [31:1] 48 corrupted_due_to_fifo_delay : 1; // [0:0] 49 #endif 50 }; 51 52 53 /* Description RXPCU_CLASSIFICATION_DETAILS 54 55 Details related to what RXPCU classification types of MPDUs 56 have been received 57 */ 58 59 60 /* Description FILTER_PASS_MPDUS 61 62 When set, at least one Filter Pass MPDU has been received. 63 FCS might or might not have been passing. 64 65 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 66 this field is the "OR of all the users. 67 <legal all> 68 */ 69 70 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 71 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 72 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 73 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 74 75 76 /* Description FILTER_PASS_MPDUS_FCS_OK 77 78 When set, at least one Filter Pass MPDU has been received 79 that has a correct FCS. 80 81 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 82 this field is the "OR of all the users. 83 84 <legal all> 85 */ 86 87 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 88 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 89 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 90 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 91 92 93 /* Description MONITOR_DIRECT_MPDUS 94 95 When set, at least one Monitor Direct MPDU has been received. 96 FCS might or might not have been passing 97 98 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 99 this field is the "OR of all the users. 100 <legal all> 101 */ 102 103 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 104 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 105 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 106 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 107 108 109 /* Description MONITOR_DIRECT_MPDUS_FCS_OK 110 111 When set, at least one Monitor Direct MPDU has been received 112 that has a correct FCS. 113 114 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 115 this field is the "OR of all the users. 116 117 <legal all> 118 */ 119 120 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 121 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 122 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 123 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 124 125 126 /* Description MONITOR_OTHER_MPDUS 127 128 When set, at least one Monitor Direct MPDU has been received. 129 FCS might or might not have been passing. 130 131 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 132 this field is the "OR of all the users. 133 <legal all> 134 */ 135 136 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 137 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 138 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 139 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 140 141 142 /* Description MONITOR_OTHER_MPDUS_FCS_OK 143 144 When set, at least one Monitor Direct MPDU has been received 145 that has a correct FCS. 146 147 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 148 this field is the "OR of all the users. 149 <legal all> 150 */ 151 152 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 153 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 154 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 155 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 156 157 158 /* Description PHYRX_ABORT_RECEIVED 159 160 When set, PPDU reception was aborted by the PHY 161 <legal all> 162 */ 163 164 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 165 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 166 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 167 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 168 169 170 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS 171 172 When set, at least one 'Filter Pass Monitor Override' MPDU 173 has been received. FCS might or might not have been passing. 174 175 176 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 177 this field is the "OR of all the users. 178 <legal all> 179 */ 180 181 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 182 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 183 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 184 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 185 186 187 /* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK 188 189 When set, at least one 'Filter Pass Monitor Override' MPDU 190 has been received that has a correct FCS. 191 192 For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, 193 this field is the "OR of all the users. 194 195 <legal all> 196 */ 197 198 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 199 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 200 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 201 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 202 203 204 /* Description RESERVED_0 205 206 <legal 0> 207 */ 208 209 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 210 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 211 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 212 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 213 214 215 /* Description PHY_PPDU_ID 216 217 A ppdu counter value that PHY increments for every PPDU 218 received. The counter value wraps around 219 <legal all> 220 */ 221 222 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 223 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 224 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 225 #define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 226 227 228 /* Description FCS_OK_BITMAP_95_64 229 230 Bitmap indicates in order of received MPDUs, which MPDUs 231 had an passing FCS or had an error. 232 1: FCS OK 233 0: FCS error 234 <legal all> 235 */ 236 237 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 238 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 239 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 240 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 241 242 243 /* Description FCS_OK_BITMAP_127_96 244 245 Bitmap indicates in order of received MPDUs, which MPDUs 246 had an passing FCS or had an error. 247 1: FCS OK 248 0: FCS error 249 <legal all> 250 */ 251 252 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 253 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 254 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 255 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff 256 257 258 /* Description FCS_OK_BITMAP_159_128 259 260 Bitmap indicates in order of received MPDUs, which MPDUs 261 had an passing FCS or had an error. 262 1: FCS OK 263 0: FCS error 264 <legal all> 265 */ 266 267 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 268 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 269 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 270 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 271 272 273 /* Description FCS_OK_BITMAP_191_160 274 275 Bitmap indicates in order of received MPDUs, which MPDUs 276 had an passing FCS or had an error. 277 1: FCS OK 278 0: FCS error 279 <legal all> 280 */ 281 282 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 283 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 284 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 285 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff 286 287 288 /* Description FCS_OK_BITMAP_223_192 289 290 Bitmap indicates in order of received MPDUs, which MPDUs 291 had an passing FCS or had an error. 292 1: FCS OK 293 0: FCS error 294 <legal all> 295 */ 296 297 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 298 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 299 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 300 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 301 302 303 /* Description FCS_OK_BITMAP_255_224 304 305 Bitmap indicates in order of received MPDUs, which MPDUs 306 had an passing FCS or had an error. 307 1: FCS OK 308 0: FCS error 309 <legal all> 310 */ 311 312 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 313 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 314 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 315 #define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff 316 317 318 /* Description CORRUPTED_DUE_TO_FIFO_DELAY 319 320 Set if Rx PCU avoided a hang due to SFM delays by writing 321 a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' 322 323 */ 324 325 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 326 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 327 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 328 #define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 329 330 331 /* Description RESERVED_7A 332 333 <legal 0> 334 */ 335 336 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 337 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 338 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 339 #define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 340 341 342 343 #endif // RX_PPDU_END_USER_STATS_EXT 344