1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_H_ 18 #define _RX_REO_QUEUE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 24 25 26 struct rx_reo_queue { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct uniform_descriptor_header descriptor_header; 29 uint32_t receive_queue_number : 16, // [15:0] 30 reserved_1b : 16; // [31:16] 31 uint32_t vld : 1, // [0:0] 32 associated_link_descriptor_counter : 2, // [2:1] 33 disable_duplicate_detection : 1, // [3:3] 34 soft_reorder_enable : 1, // [4:4] 35 ac : 2, // [6:5] 36 bar : 1, // [7:7] 37 rty : 1, // [8:8] 38 chk_2k_mode : 1, // [9:9] 39 oor_mode : 1, // [10:10] 40 ba_window_size : 10, // [20:11] 41 pn_check_needed : 1, // [21:21] 42 pn_shall_be_even : 1, // [22:22] 43 pn_shall_be_uneven : 1, // [23:23] 44 pn_handling_enable : 1, // [24:24] 45 pn_size : 2, // [26:25] 46 ignore_ampdu_flag : 1, // [27:27] 47 reserved_2b : 4; // [31:28] 48 uint32_t svld : 1, // [0:0] 49 ssn : 12, // [12:1] 50 current_index : 10, // [22:13] 51 seq_2k_error_detected_flag : 1, // [23:23] 52 pn_error_detected_flag : 1, // [24:24] 53 reserved_3a : 6, // [30:25] 54 pn_valid : 1; // [31:31] 55 uint32_t pn_31_0 : 32; // [31:0] 56 uint32_t pn_63_32 : 32; // [31:0] 57 uint32_t pn_95_64 : 32; // [31:0] 58 uint32_t pn_127_96 : 32; // [31:0] 59 uint32_t last_rx_enqueue_timestamp : 32; // [31:0] 60 uint32_t last_rx_dequeue_timestamp : 32; // [31:0] 61 uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] 62 uint32_t ptr_to_next_aging_queue_39_32 : 8, // [7:0] 63 reserved_11a : 24; // [31:8] 64 uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] 65 uint32_t ptr_to_previous_aging_queue_39_32 : 8, // [7:0] 66 statistics_counter_index : 6, // [13:8] 67 reserved_13a : 18; // [31:14] 68 uint32_t rx_bitmap_31_0 : 32; // [31:0] 69 uint32_t rx_bitmap_63_32 : 32; // [31:0] 70 uint32_t rx_bitmap_95_64 : 32; // [31:0] 71 uint32_t rx_bitmap_127_96 : 32; // [31:0] 72 uint32_t rx_bitmap_159_128 : 32; // [31:0] 73 uint32_t rx_bitmap_191_160 : 32; // [31:0] 74 uint32_t rx_bitmap_223_192 : 32; // [31:0] 75 uint32_t rx_bitmap_255_224 : 32; // [31:0] 76 uint32_t rx_bitmap_287_256 : 32; // [31:0] 77 uint32_t current_mpdu_count : 7, // [6:0] 78 current_msdu_count : 25; // [31:7] 79 uint32_t last_sn_reg_index : 4, // [3:0] 80 timeout_count : 6, // [9:4] 81 forward_due_to_bar_count : 6, // [15:10] 82 duplicate_count : 16; // [31:16] 83 uint32_t frames_in_order_count : 24, // [23:0] 84 bar_received_count : 8; // [31:24] 85 uint32_t mpdu_frames_processed_count : 32; // [31:0] 86 uint32_t msdu_frames_processed_count : 32; // [31:0] 87 uint32_t total_processed_byte_count : 32; // [31:0] 88 uint32_t late_receive_mpdu_count : 12, // [11:0] 89 window_jump_2k : 4, // [15:12] 90 hole_count : 16; // [31:16] 91 uint32_t aging_drop_mpdu_count : 16, // [15:0] 92 aging_drop_interval : 8, // [23:16] 93 reserved_30 : 8; // [31:24] 94 uint32_t reserved_31 : 32; // [31:0] 95 #else 96 struct uniform_descriptor_header descriptor_header; 97 uint32_t reserved_1b : 16, // [31:16] 98 receive_queue_number : 16; // [15:0] 99 uint32_t reserved_2b : 4, // [31:28] 100 ignore_ampdu_flag : 1, // [27:27] 101 pn_size : 2, // [26:25] 102 pn_handling_enable : 1, // [24:24] 103 pn_shall_be_uneven : 1, // [23:23] 104 pn_shall_be_even : 1, // [22:22] 105 pn_check_needed : 1, // [21:21] 106 ba_window_size : 10, // [20:11] 107 oor_mode : 1, // [10:10] 108 chk_2k_mode : 1, // [9:9] 109 rty : 1, // [8:8] 110 bar : 1, // [7:7] 111 ac : 2, // [6:5] 112 soft_reorder_enable : 1, // [4:4] 113 disable_duplicate_detection : 1, // [3:3] 114 associated_link_descriptor_counter : 2, // [2:1] 115 vld : 1; // [0:0] 116 uint32_t pn_valid : 1, // [31:31] 117 reserved_3a : 6, // [30:25] 118 pn_error_detected_flag : 1, // [24:24] 119 seq_2k_error_detected_flag : 1, // [23:23] 120 current_index : 10, // [22:13] 121 ssn : 12, // [12:1] 122 svld : 1; // [0:0] 123 uint32_t pn_31_0 : 32; // [31:0] 124 uint32_t pn_63_32 : 32; // [31:0] 125 uint32_t pn_95_64 : 32; // [31:0] 126 uint32_t pn_127_96 : 32; // [31:0] 127 uint32_t last_rx_enqueue_timestamp : 32; // [31:0] 128 uint32_t last_rx_dequeue_timestamp : 32; // [31:0] 129 uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] 130 uint32_t reserved_11a : 24, // [31:8] 131 ptr_to_next_aging_queue_39_32 : 8; // [7:0] 132 uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] 133 uint32_t reserved_13a : 18, // [31:14] 134 statistics_counter_index : 6, // [13:8] 135 ptr_to_previous_aging_queue_39_32 : 8; // [7:0] 136 uint32_t rx_bitmap_31_0 : 32; // [31:0] 137 uint32_t rx_bitmap_63_32 : 32; // [31:0] 138 uint32_t rx_bitmap_95_64 : 32; // [31:0] 139 uint32_t rx_bitmap_127_96 : 32; // [31:0] 140 uint32_t rx_bitmap_159_128 : 32; // [31:0] 141 uint32_t rx_bitmap_191_160 : 32; // [31:0] 142 uint32_t rx_bitmap_223_192 : 32; // [31:0] 143 uint32_t rx_bitmap_255_224 : 32; // [31:0] 144 uint32_t rx_bitmap_287_256 : 32; // [31:0] 145 uint32_t current_msdu_count : 25, // [31:7] 146 current_mpdu_count : 7; // [6:0] 147 uint32_t duplicate_count : 16, // [31:16] 148 forward_due_to_bar_count : 6, // [15:10] 149 timeout_count : 6, // [9:4] 150 last_sn_reg_index : 4; // [3:0] 151 uint32_t bar_received_count : 8, // [31:24] 152 frames_in_order_count : 24; // [23:0] 153 uint32_t mpdu_frames_processed_count : 32; // [31:0] 154 uint32_t msdu_frames_processed_count : 32; // [31:0] 155 uint32_t total_processed_byte_count : 32; // [31:0] 156 uint32_t hole_count : 16, // [31:16] 157 window_jump_2k : 4, // [15:12] 158 late_receive_mpdu_count : 12; // [11:0] 159 uint32_t reserved_30 : 8, // [31:24] 160 aging_drop_interval : 8, // [23:16] 161 aging_drop_mpdu_count : 16; // [15:0] 162 uint32_t reserved_31 : 32; // [31:0] 163 #endif 164 }; 165 166 167 /* Description DESCRIPTOR_HEADER 168 169 Details about which module owns this struct. 170 Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_descriptor" 171 172 */ 173 174 175 /* Description OWNER 176 177 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 178 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 179 180 The owner of this data structure: 181 <enum 0 WBM_owned> Buffer Manager currently owns this data 182 structure. 183 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 184 data structure. 185 <enum 2 TQM_owned> Transmit Queue Manager currently owns 186 this data structure. 187 <enum 3 RXDMA_owned> Receive DMA currently owns this data 188 structure. 189 <enum 4 REO_owned> Reorder currently owns this data structure. 190 191 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 192 193 194 <legal 0-5> 195 */ 196 197 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 198 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 199 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 200 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 201 202 203 /* Description BUFFER_TYPE 204 205 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 206 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 207 208 Field describing what contents format is of this descriptor 209 210 211 <enum 0 Transmit_MSDU_Link_descriptor> 212 <enum 1 Transmit_MPDU_Link_descriptor> 213 <enum 2 Transmit_MPDU_Queue_head_descriptor> 214 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 215 <enum 4 Transmit_flow_descriptor> 216 <enum 5 Transmit_buffer> NOT TO BE USED: 217 218 <enum 6 Receive_MSDU_Link_descriptor> 219 <enum 7 Receive_MPDU_Link_descriptor> 220 <enum 8 Receive_REO_queue_descriptor> 221 <enum 9 Receive_REO_queue_1k_descriptor> 222 <enum 10 Receive_REO_queue_ext_descriptor> 223 224 <enum 11 Receive_buffer> 225 226 <enum 12 Idle_link_list_entry> 227 228 <legal 0-12> 229 */ 230 231 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 232 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 233 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 234 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 235 236 237 /* Description TX_MPDU_QUEUE_NUMBER 238 239 Consumer: TQM/Debug 240 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 241 242 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 243 244 245 Indicates the MPDU queue ID to which this MPDU descriptor 246 belongs 247 Used for tracking and debugging 248 249 <legal all> 250 */ 251 252 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 253 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 254 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 255 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 256 257 258 /* Description RESERVED_0A 259 260 <legal 0> 261 */ 262 263 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 264 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 265 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 266 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 267 268 269 /* Description RECEIVE_QUEUE_NUMBER 270 271 Indicates the MPDU queue ID to which this MPDU link descriptor 272 belongs 273 Used for tracking and debugging 274 <legal all> 275 */ 276 277 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 278 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 279 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 280 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 281 282 283 /* Description RESERVED_1B 284 285 <legal 0> 286 */ 287 288 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 289 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 290 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 291 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 292 293 294 /* Description VLD 295 296 Valid bit indicating a session is established and the queue 297 descriptor is valid(Filled by SW) 298 <legal all> 299 */ 300 301 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 302 #define RX_REO_QUEUE_VLD_LSB 0 303 #define RX_REO_QUEUE_VLD_MSB 0 304 #define RX_REO_QUEUE_VLD_MASK 0x00000001 305 306 307 /* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER 308 309 Indicates which of the 3 link descriptor counters shall 310 be incremented or decremented when link descriptors are 311 added or removed from this flow queue. 312 MSDU link descriptors related with MPDUs stored in the re-order 313 buffer shall also be included in this count. 314 315 <legal 0-2> 316 */ 317 318 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 319 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 320 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 321 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 322 323 324 /* Description DISABLE_DUPLICATE_DETECTION 325 326 When set, do not perform any duplicate detection. 327 328 <legal all> 329 */ 330 331 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 332 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 333 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 334 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 335 336 337 /* Description SOFT_REORDER_ENABLE 338 339 When set, REO has been instructed to not perform the actual 340 re-ordering of frames for this queue, but just to insert 341 the reorder opcodes. 342 343 Note that this implies that REO is also not going to perform 344 any MSDU level operations, and the entire MPDU (and thus 345 pointer to the MSDU link descriptor) will be pushed to 346 a destination ring that SW has programmed in a SW programmable 347 configuration register in REO 348 349 <legal all> 350 */ 351 352 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 353 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 354 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 355 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 356 357 358 /* Description AC 359 360 Indicates which access category the queue descriptor belongs 361 to(filled by SW) 362 <legal all> 363 */ 364 365 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 366 #define RX_REO_QUEUE_AC_LSB 5 367 #define RX_REO_QUEUE_AC_MSB 6 368 #define RX_REO_QUEUE_AC_MASK 0x00000060 369 370 371 /* Description BAR 372 373 Indicates if BAR has been received (mostly used for debug 374 purpose and this is filled by REO) 375 <legal all> 376 */ 377 378 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 379 #define RX_REO_QUEUE_BAR_LSB 7 380 #define RX_REO_QUEUE_BAR_MSB 7 381 #define RX_REO_QUEUE_BAR_MASK 0x00000080 382 383 384 /* Description RTY 385 386 Retry bit is checked if this bit is set. 387 <legal all> 388 */ 389 390 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 391 #define RX_REO_QUEUE_RTY_LSB 8 392 #define RX_REO_QUEUE_RTY_MSB 8 393 #define RX_REO_QUEUE_RTY_MASK 0x00000100 394 395 396 /* Description CHK_2K_MODE 397 398 Indicates what type of operation is expected from Reo when 399 the received frame SN falls within the 2K window 400 401 <legal all> 402 */ 403 404 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 405 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 406 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 407 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 408 409 410 /* Description OOR_MODE 411 412 Out of Order mode: 413 Indicates what type of operation is expected when the received 414 frame falls within the OOR window. 415 416 <legal all> 417 */ 418 419 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 420 #define RX_REO_QUEUE_OOR_MODE_LSB 10 421 #define RX_REO_QUEUE_OOR_MODE_MSB 10 422 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 423 424 425 /* Description BA_WINDOW_SIZE 426 427 Indicates the negotiated (window size + 1). 428 It can go up to Max of 256bits. 429 430 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means 431 non-BA session, with window size of 0). The 3 values here 432 are the main values validated, but other values should 433 work as well. 434 435 A value 1023 means 1024 bitmap, 511 means 512 bitmap. The 436 2 values here are the main values validated for 1k-bitmap 437 support, but other values should work as well. 438 439 A BA window size of 0 (=> one frame entry bitmap), means 440 that there is NO RX_REO_QUEUE_EXT descriptor following 441 this RX_REO_QUEUE STRUCT in memory 442 443 A BA window size of 1 - 105 means that there is 1 RX_REO_QUEUE_EXT 444 descriptor directly following this RX_REO_QUEUE STRUCT 445 in memory. 446 447 A BA window size of 106 - 210 means that there are 2 RX_REO_QUEUE_EXT 448 descriptors directly following this RX_REO_QUEUE STRUCT 449 in memory 450 451 A BA window size of 211 - 256 means that there are 3 RX_REO_QUEUE_EXT 452 descriptors directly following this RX_REO_QUEUE STRUCT 453 in memory 454 455 A BA window size of 257 - 315 means that there is one RX_REO_QUEUE_1K 456 descriptor followed by 3 RX_REO_QUEUE_EXT descriptors directly 457 following this RX_REO_QUEUE STRUCT in memory 458 459 A BA window size of 316 - 420 means that there is one RX_REO_QUEUE_1K 460 descriptor followed by 4 RX_REO_QUEUE_EXT descriptors directly 461 following this RX_REO_QUEUE STRUCT in memory 462 ... 463 A BA window size of 946 - 1024 means that there is one RX_REO_QUEUE_1K 464 descriptor followed by 10 RX_REO_QUEUE_EXT descriptors 465 directly following this RX_REO_QUEUE STRUCT in memory 466 467 TODO: Should the above text use '255' and '1023' instead 468 of '256' and '1024'? 469 <legal 0 - 1023> 470 */ 471 472 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 473 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 474 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 475 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 476 477 478 /* Description PN_CHECK_NEEDED 479 480 When set, REO shall perform the PN increment check 481 <legal all> 482 */ 483 484 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 485 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 486 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 487 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 488 489 490 /* Description PN_SHALL_BE_EVEN 491 492 Field only valid when 'pn_check_needed' is set. 493 494 When set, REO shall confirm that the received PN number 495 is not only incremented, but also always an even number 496 <legal all> 497 */ 498 499 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 500 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 501 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 502 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 503 504 505 /* Description PN_SHALL_BE_UNEVEN 506 507 Field only valid when 'pn_check_needed' is set. 508 509 When set, REO shall confirm that the received PN number 510 is not only incremented, but also always an uneven number 511 512 <legal all> 513 */ 514 515 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 516 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 517 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 518 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 519 520 521 /* Description PN_HANDLING_ENABLE 522 523 Field only valid when 'pn_check_needed' is set. 524 525 When set, and REO detected a PN error, HW shall set the 'pn_error_detected_flag'. 526 527 <legal all> 528 */ 529 530 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 531 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 532 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 533 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 534 535 536 /* Description PN_SIZE 537 538 Size of the PN field check. 539 Needed for wrap around handling... 540 541 <enum 0 pn_size_24> 542 <enum 1 pn_size_48> 543 <enum 2 pn_size_128> 544 545 <legal 0-2> 546 */ 547 548 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 549 #define RX_REO_QUEUE_PN_SIZE_LSB 25 550 #define RX_REO_QUEUE_PN_SIZE_MSB 26 551 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 552 553 554 /* Description IGNORE_AMPDU_FLAG 555 556 When set, REO shall ignore the ampdu_flag on the entrance 557 descriptor for this queue. 558 <legal all> 559 */ 560 561 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 562 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 563 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 564 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 565 566 567 /* Description RESERVED_2B 568 569 <legal 0> 570 */ 571 572 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 573 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 574 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 575 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 576 577 578 /* Description SVLD 579 580 Sequence number in next field is valid one. It can be filled 581 by SW if the want to fill in the any negotiated SSN, otherwise 582 REO will fill the sequence number of first received packet 583 and set this bit to 1. 584 <legal all> 585 */ 586 587 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 588 #define RX_REO_QUEUE_SVLD_LSB 0 589 #define RX_REO_QUEUE_SVLD_MSB 0 590 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 591 592 593 /* Description SSN 594 595 Starting Sequence number of the session, this changes whenever 596 window moves. (can be filled by SW then maintained by REO) 597 598 <legal all> 599 */ 600 601 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 602 #define RX_REO_QUEUE_SSN_LSB 1 603 #define RX_REO_QUEUE_SSN_MSB 12 604 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 605 606 607 /* Description CURRENT_INDEX 608 609 Points to last forwarded packet 610 <legal all> 611 */ 612 613 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 614 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 615 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 616 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 617 618 619 /* Description SEQ_2K_ERROR_DETECTED_FLAG 620 621 Set by REO, can only be cleared by SW 622 623 When set, REO has detected a 2k error jump in the sequence 624 number and from that moment forward, all new frames are 625 forwarded directly to FW, without duplicate detect, reordering, 626 etc. 627 <legal all> 628 */ 629 630 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 631 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 632 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 633 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 634 635 636 /* Description PN_ERROR_DETECTED_FLAG 637 638 Set by REO, can only be cleared by SW 639 640 When set, REO has detected a PN error and from that moment 641 forward, all new frames are forwarded directly to FW, without 642 duplicate detect, reordering, etc. 643 <legal all> 644 */ 645 646 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 647 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 648 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 649 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 650 651 652 /* Description RESERVED_3A 653 654 <legal 0> 655 */ 656 657 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 658 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 659 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 660 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 661 662 663 /* Description PN_VALID 664 665 PN number in next fields are valid. It can be filled by 666 SW if it wants to fill in the any negotiated SSN, otherwise 667 REO will fill the pn based on the first received packet 668 and set this bit to 1. 669 <legal all> 670 */ 671 672 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 673 #define RX_REO_QUEUE_PN_VALID_LSB 31 674 #define RX_REO_QUEUE_PN_VALID_MSB 31 675 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 676 677 678 /* Description PN_31_0 679 680 Bits [31:0] of the PN number extracted from the IV field 681 682 <legal all> 683 */ 684 685 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 686 #define RX_REO_QUEUE_PN_31_0_LSB 0 687 #define RX_REO_QUEUE_PN_31_0_MSB 31 688 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 689 690 691 /* Description PN_63_32 692 693 Bits [63:32] of the PN number. 694 <legal all> 695 */ 696 697 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 698 #define RX_REO_QUEUE_PN_63_32_LSB 0 699 #define RX_REO_QUEUE_PN_63_32_MSB 31 700 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 701 702 703 /* Description PN_95_64 704 705 Bits [95:64] of the PN number. 706 <legal all> 707 */ 708 709 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 710 #define RX_REO_QUEUE_PN_95_64_LSB 0 711 #define RX_REO_QUEUE_PN_95_64_MSB 31 712 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 713 714 715 /* Description PN_127_96 716 717 Bits [127:96] of the PN number. 718 <legal all> 719 */ 720 721 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 722 #define RX_REO_QUEUE_PN_127_96_LSB 0 723 #define RX_REO_QUEUE_PN_127_96_MSB 31 724 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 725 726 727 /* Description LAST_RX_ENQUEUE_TIMESTAMP 728 729 This timestamp is updated when an MPDU is received and accesses 730 this Queue Descriptor. It does not include the access due 731 to Command TLVs or Aging (which will be updated in Last_rx_dequeue_timestamp). 732 733 <legal all> 734 */ 735 736 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 737 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 738 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 739 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 740 741 742 /* Description LAST_RX_DEQUEUE_TIMESTAMP 743 744 This timestamp is used for Aging. When an MPDU or multiple 745 MPDUs are forwarded, either due to window movement, bar, 746 aging or command flush, this timestamp is updated. Also 747 when the bitmap is all zero and the first time an MPDU is 748 queued (opcode=QCUR), this timestamp is updated for aging. 749 750 <legal all> 751 */ 752 753 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 754 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 755 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 756 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 757 758 759 /* Description PTR_TO_NEXT_AGING_QUEUE_31_0 760 761 Address (address bits 31-0)of next RX_REO_QUEUE descriptor 762 in the 'receive timestamp' ordered list. 763 From it the Position of this queue descriptor in the per 764 AC aging waitlist can be derived. 765 Value 0x0 indicates the 'NULL' pointer which implies that 766 this is the last entry in the list. 767 <legal all> 768 */ 769 770 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 771 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 772 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 773 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 774 775 776 /* Description PTR_TO_NEXT_AGING_QUEUE_39_32 777 778 Address (address bits 39-32)of next RX_REO_QUEUE descriptor 779 in the 'receive timestamp' ordered list. 780 From it the Position of this queue descriptor in the per 781 AC aging waitlist can be derived. 782 Value 0x0 indicates the 'NULL' pointer which implies that 783 this is the last entry in the list. 784 <legal all> 785 */ 786 787 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 788 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 789 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 790 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 791 792 793 /* Description RESERVED_11A 794 795 <legal 0> 796 */ 797 798 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 799 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 800 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 801 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 802 803 804 /* Description PTR_TO_PREVIOUS_AGING_QUEUE_31_0 805 806 Address (address bits 31-0)of next RX_REO_QUEUE descriptor 807 in the 'receive timestamp' ordered list. 808 From it the Position of this queue descriptor in the per 809 AC aging waitlist can be derived. 810 Value 0x0 indicates the 'NULL' pointer which implies that 811 this is the first entry in the list. 812 <legal all> 813 */ 814 815 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 816 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 817 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 818 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 819 820 821 /* Description PTR_TO_PREVIOUS_AGING_QUEUE_39_32 822 823 Address (address bits 39-32)of next RX_REO_QUEUE descriptor 824 in the 'receive timestamp' ordered list. 825 From it the Position of this queue descriptor in the per 826 AC aging waitlist can be derived. 827 Value 0x0 indicates the 'NULL' pointer which implies that 828 this is the first entry in the list. 829 <legal all> 830 */ 831 832 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 833 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 834 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 835 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 836 837 838 /* Description STATISTICS_COUNTER_INDEX 839 840 Usually all the queues pertaining to one virtual device 841 use one statistics register set, and each virtual device 842 maps to a different set in case of not too many virtual 843 devices. 844 <legal 0-47> 845 */ 846 847 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 848 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 849 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 850 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 851 852 853 /* Description RESERVED_13A 854 855 <legal 0> 856 */ 857 858 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 859 #define RX_REO_QUEUE_RESERVED_13A_LSB 14 860 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 861 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 862 863 864 /* Description RX_BITMAP_31_0 865 866 When a bit is set, the corresponding frame is currently 867 held in the re-order queue. 868 The bitmap is Fully managed by HW. 869 SW shall init this to 0, and then never ever change it 870 <legal all> 871 */ 872 873 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 874 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 875 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 876 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 877 878 879 /* Description RX_BITMAP_63_32 880 881 See Rx_bitmap_31_0 description 882 <legal all> 883 */ 884 885 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 886 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 887 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 888 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 889 890 891 /* Description RX_BITMAP_95_64 892 893 See Rx_bitmap_31_0 description 894 <legal all> 895 */ 896 897 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 898 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 899 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 900 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 901 902 903 /* Description RX_BITMAP_127_96 904 905 See Rx_bitmap_31_0 description 906 <legal all> 907 */ 908 909 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 910 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 911 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 912 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 913 914 915 /* Description RX_BITMAP_159_128 916 917 See Rx_bitmap_31_0 description 918 <legal all> 919 */ 920 921 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 922 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 923 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 924 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 925 926 927 /* Description RX_BITMAP_191_160 928 929 See Rx_bitmap_31_0 description 930 <legal all> 931 */ 932 933 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 934 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 935 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 936 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 937 938 939 /* Description RX_BITMAP_223_192 940 941 See Rx_bitmap_31_0 description 942 <legal all> 943 */ 944 945 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 946 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 947 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 948 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 949 950 951 /* Description RX_BITMAP_255_224 952 953 See Rx_bitmap_31_0 description 954 <legal all> 955 */ 956 957 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 958 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 959 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 960 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 961 962 963 /* Description RX_BITMAP_287_256 964 965 See Rx_bitmap_31_0 description 966 <legal all> 967 */ 968 969 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 970 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 971 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 972 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 973 974 975 /* Description CURRENT_MPDU_COUNT 976 977 The number of MPDUs in the queue. 978 979 <legal all> 980 */ 981 982 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 983 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 984 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 985 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 986 987 988 /* Description CURRENT_MSDU_COUNT 989 990 The number of MSDUs in the queue. 991 <legal all> 992 */ 993 994 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 995 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 996 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 997 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 998 999 1000 /* Description LAST_SN_REG_INDEX 1001 1002 REO has registers to save the last SN seen in up to 9 REO 1003 queues, to support "leaky APs." 1004 1005 This field gives the register number to use for saving the 1006 last SN of this REO queue. 1007 <legal 0-8> 1008 */ 1009 1010 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 1011 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 1012 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 1013 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 1014 1015 1016 /* Description TIMEOUT_COUNT 1017 1018 The number of times that REO started forwarding frames even 1019 though there is a hole in the bitmap. Forwarding reason 1020 is Timeout 1021 1022 The counter saturates and freezes at 0x3F 1023 1024 <legal all> 1025 */ 1026 1027 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 1028 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 1029 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 1030 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 1031 1032 1033 /* Description FORWARD_DUE_TO_BAR_COUNT 1034 1035 The number of times that REO started forwarding frames even 1036 though there is a hole in the bitmap. Forwarding reason 1037 is reception of BAR frame. 1038 1039 The counter saturates and freezes at 0x3F 1040 1041 <legal all> 1042 */ 1043 1044 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 1045 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1046 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 1047 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1048 1049 1050 /* Description DUPLICATE_COUNT 1051 1052 The number of duplicate frames that have been detected 1053 <legal all> 1054 */ 1055 1056 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 1057 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 1058 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 1059 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 1060 1061 1062 /* Description FRAMES_IN_ORDER_COUNT 1063 1064 The number of frames that have been received in order (without 1065 a hole that prevented them from being forwarded immediately) 1066 1067 1068 This corresponds to the Reorder opcodes: 1069 'FWDCUR' and 'FWD BUF' 1070 1071 <legal all> 1072 */ 1073 1074 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 1075 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 1076 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 1077 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1078 1079 1080 /* Description BAR_RECEIVED_COUNT 1081 1082 The number of times a BAR frame is received. 1083 1084 This corresponds to the Reorder opcodes with 'DROP' 1085 1086 The counter saturates and freezes at 0xFF 1087 <legal all> 1088 */ 1089 1090 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 1091 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 1092 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 1093 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 1094 1095 1096 /* Description MPDU_FRAMES_PROCESSED_COUNT 1097 1098 The total number of MPDU frames that have been processed 1099 by REO. 'Processing' here means that REO has received them 1100 out of the entrance ring, and retrieved the corresponding 1101 RX_REO_QUEUE Descriptor. 1102 1103 Note that this count includes duplicates, frames that later 1104 had errors, etc. 1105 1106 Note that field 'Duplicate_count' indicates how many of 1107 these MPDUs were duplicates. 1108 1109 <legal all> 1110 */ 1111 1112 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1113 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1114 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 1115 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1116 1117 1118 /* Description MSDU_FRAMES_PROCESSED_COUNT 1119 1120 The total number of MSDU frames that have been processed 1121 by REO. 'Processing' here means that REO has received them 1122 out of the entrance ring, and retrieved the corresponding 1123 RX_REO_QUEUE Descriptor. 1124 1125 Note that this count includes duplicates, frames that later 1126 had errors, etc. 1127 1128 <legal all> 1129 */ 1130 1131 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 1132 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1133 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 1134 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1135 1136 1137 /* Description TOTAL_PROCESSED_BYTE_COUNT 1138 1139 An approximation of the number of bytes processed for this 1140 queue. 1141 'Processing' here means that REO has received them out of 1142 the entrance ring, and retrieved the corresponding RX_REO_QUEUE 1143 Descriptor. 1144 1145 Note that this count includes duplicates, frames that later 1146 had errors, etc. 1147 1148 In 64 byte units 1149 <legal all> 1150 */ 1151 1152 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 1153 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1154 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 1155 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1156 1157 1158 /* Description LATE_RECEIVE_MPDU_COUNT 1159 1160 The number of MPDUs received after the window had already 1161 moved on. The 'late' sequence window is defined as (Window 1162 SSN - 256) - (Window SSN - 1) 1163 1164 This corresponds with Out of order detection in duplicate 1165 detect FSM 1166 1167 The counter saturates and freezes at 0xFFF 1168 1169 <legal all> 1170 */ 1171 1172 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 1173 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 1174 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 1175 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1176 1177 1178 /* Description WINDOW_JUMP_2K 1179 1180 The number of times the window moved more then 2K 1181 1182 The counter saturates and freezes at 0xF 1183 1184 (Note: field name can not start with number: previous 2k_window_jump) 1185 1186 1187 <legal all> 1188 */ 1189 1190 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 1191 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 1192 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 1193 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 1194 1195 1196 /* Description HOLE_COUNT 1197 1198 The number of times a hole was created in the receive bitmap. 1199 1200 1201 This corresponds to the Reorder opcodes with 'QCUR' 1202 1203 <legal all> 1204 */ 1205 1206 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 1207 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 1208 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 1209 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 1210 1211 1212 /* Description AGING_DROP_MPDU_COUNT 1213 1214 The number of holes in the bitmap that moved due to aging 1215 counter expiry 1216 <legal all> 1217 */ 1218 1219 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 1220 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 1221 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 1222 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff 1223 1224 1225 /* Description AGING_DROP_INTERVAL 1226 1227 The number of times holes got removed from the bitmap due 1228 to aging counter expiry 1229 <legal all> 1230 */ 1231 1232 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 1233 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 1234 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 1235 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 1236 1237 1238 /* Description RESERVED_30 1239 1240 <legal 0> 1241 */ 1242 1243 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 1244 #define RX_REO_QUEUE_RESERVED_30_LSB 24 1245 #define RX_REO_QUEUE_RESERVED_30_MSB 31 1246 #define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 1247 1248 1249 /* Description RESERVED_31 1250 1251 <legal 0> 1252 */ 1253 1254 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 1255 #define RX_REO_QUEUE_RESERVED_31_LSB 0 1256 #define RX_REO_QUEUE_RESERVED_31_MSB 31 1257 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 1258 1259 1260 1261 #endif // RX_REO_QUEUE 1262