1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_1K_H_ 18 #define _RX_REO_QUEUE_1K_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 24 25 26 struct rx_reo_queue_1k { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct uniform_descriptor_header descriptor_header; 29 uint32_t rx_bitmap_319_288 : 32; // [31:0] 30 uint32_t rx_bitmap_351_320 : 32; // [31:0] 31 uint32_t rx_bitmap_383_352 : 32; // [31:0] 32 uint32_t rx_bitmap_415_384 : 32; // [31:0] 33 uint32_t rx_bitmap_447_416 : 32; // [31:0] 34 uint32_t rx_bitmap_479_448 : 32; // [31:0] 35 uint32_t rx_bitmap_511_480 : 32; // [31:0] 36 uint32_t rx_bitmap_543_512 : 32; // [31:0] 37 uint32_t rx_bitmap_575_544 : 32; // [31:0] 38 uint32_t rx_bitmap_607_576 : 32; // [31:0] 39 uint32_t rx_bitmap_639_608 : 32; // [31:0] 40 uint32_t rx_bitmap_671_640 : 32; // [31:0] 41 uint32_t rx_bitmap_703_672 : 32; // [31:0] 42 uint32_t rx_bitmap_735_704 : 32; // [31:0] 43 uint32_t rx_bitmap_767_736 : 32; // [31:0] 44 uint32_t rx_bitmap_799_768 : 32; // [31:0] 45 uint32_t rx_bitmap_831_800 : 32; // [31:0] 46 uint32_t rx_bitmap_863_832 : 32; // [31:0] 47 uint32_t rx_bitmap_895_864 : 32; // [31:0] 48 uint32_t rx_bitmap_927_896 : 32; // [31:0] 49 uint32_t rx_bitmap_959_928 : 32; // [31:0] 50 uint32_t rx_bitmap_991_960 : 32; // [31:0] 51 uint32_t rx_bitmap_1023_992 : 32; // [31:0] 52 uint32_t reserved_24 : 32; // [31:0] 53 uint32_t reserved_25 : 32; // [31:0] 54 uint32_t reserved_26 : 32; // [31:0] 55 uint32_t reserved_27 : 32; // [31:0] 56 uint32_t reserved_28 : 32; // [31:0] 57 uint32_t reserved_29 : 32; // [31:0] 58 uint32_t reserved_30 : 32; // [31:0] 59 uint32_t reserved_31 : 32; // [31:0] 60 #else 61 struct uniform_descriptor_header descriptor_header; 62 uint32_t rx_bitmap_319_288 : 32; // [31:0] 63 uint32_t rx_bitmap_351_320 : 32; // [31:0] 64 uint32_t rx_bitmap_383_352 : 32; // [31:0] 65 uint32_t rx_bitmap_415_384 : 32; // [31:0] 66 uint32_t rx_bitmap_447_416 : 32; // [31:0] 67 uint32_t rx_bitmap_479_448 : 32; // [31:0] 68 uint32_t rx_bitmap_511_480 : 32; // [31:0] 69 uint32_t rx_bitmap_543_512 : 32; // [31:0] 70 uint32_t rx_bitmap_575_544 : 32; // [31:0] 71 uint32_t rx_bitmap_607_576 : 32; // [31:0] 72 uint32_t rx_bitmap_639_608 : 32; // [31:0] 73 uint32_t rx_bitmap_671_640 : 32; // [31:0] 74 uint32_t rx_bitmap_703_672 : 32; // [31:0] 75 uint32_t rx_bitmap_735_704 : 32; // [31:0] 76 uint32_t rx_bitmap_767_736 : 32; // [31:0] 77 uint32_t rx_bitmap_799_768 : 32; // [31:0] 78 uint32_t rx_bitmap_831_800 : 32; // [31:0] 79 uint32_t rx_bitmap_863_832 : 32; // [31:0] 80 uint32_t rx_bitmap_895_864 : 32; // [31:0] 81 uint32_t rx_bitmap_927_896 : 32; // [31:0] 82 uint32_t rx_bitmap_959_928 : 32; // [31:0] 83 uint32_t rx_bitmap_991_960 : 32; // [31:0] 84 uint32_t rx_bitmap_1023_992 : 32; // [31:0] 85 uint32_t reserved_24 : 32; // [31:0] 86 uint32_t reserved_25 : 32; // [31:0] 87 uint32_t reserved_26 : 32; // [31:0] 88 uint32_t reserved_27 : 32; // [31:0] 89 uint32_t reserved_28 : 32; // [31:0] 90 uint32_t reserved_29 : 32; // [31:0] 91 uint32_t reserved_30 : 32; // [31:0] 92 uint32_t reserved_31 : 32; // [31:0] 93 #endif 94 }; 95 96 97 /* Description DESCRIPTOR_HEADER 98 99 Details about which module owns this struct. 100 Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_1k_descriptor" 101 102 */ 103 104 105 /* Description OWNER 106 107 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 108 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 109 110 The owner of this data structure: 111 <enum 0 WBM_owned> Buffer Manager currently owns this data 112 structure. 113 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 114 data structure. 115 <enum 2 TQM_owned> Transmit Queue Manager currently owns 116 this data structure. 117 <enum 3 RXDMA_owned> Receive DMA currently owns this data 118 structure. 119 <enum 4 REO_owned> Reorder currently owns this data structure. 120 121 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 122 123 124 <legal 0-5> 125 */ 126 127 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 128 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 129 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 130 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 131 132 133 /* Description BUFFER_TYPE 134 135 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 136 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 137 138 Field describing what contents format is of this descriptor 139 140 141 <enum 0 Transmit_MSDU_Link_descriptor> 142 <enum 1 Transmit_MPDU_Link_descriptor> 143 <enum 2 Transmit_MPDU_Queue_head_descriptor> 144 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 145 <enum 4 Transmit_flow_descriptor> 146 <enum 5 Transmit_buffer> NOT TO BE USED: 147 148 <enum 6 Receive_MSDU_Link_descriptor> 149 <enum 7 Receive_MPDU_Link_descriptor> 150 <enum 8 Receive_REO_queue_descriptor> 151 <enum 9 Receive_REO_queue_1k_descriptor> 152 <enum 10 Receive_REO_queue_ext_descriptor> 153 154 <enum 11 Receive_buffer> 155 156 <enum 12 Idle_link_list_entry> 157 158 <legal 0-12> 159 */ 160 161 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 162 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 163 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 164 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 165 166 167 /* Description TX_MPDU_QUEUE_NUMBER 168 169 Consumer: TQM/Debug 170 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 171 172 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 173 174 175 Indicates the MPDU queue ID to which this MPDU descriptor 176 belongs 177 Used for tracking and debugging 178 179 <legal all> 180 */ 181 182 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 183 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 184 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 185 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 186 187 188 /* Description RESERVED_0A 189 190 <legal 0> 191 */ 192 193 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 194 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 195 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 196 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 197 198 199 /* Description RX_BITMAP_319_288 200 201 When a bit is set, the corresponding frame is currently 202 held in the re-order queue. 203 The bitmap is Fully managed by HW. 204 SW shall init this to 0, and then never ever change it 205 <legal all> 206 */ 207 208 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 209 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 210 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 211 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff 212 213 214 /* Description RX_BITMAP_351_320 215 216 See Rx_bitmap_319_288 description 217 <legal all> 218 */ 219 220 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 221 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 222 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 223 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff 224 225 226 /* Description RX_BITMAP_383_352 227 228 See Rx_bitmap_319_288 description 229 <legal all> 230 */ 231 232 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c 233 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 234 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 235 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff 236 237 238 /* Description RX_BITMAP_415_384 239 240 See Rx_bitmap_319_288 description 241 <legal all> 242 */ 243 244 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 245 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 246 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 247 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff 248 249 250 /* Description RX_BITMAP_447_416 251 252 See Rx_bitmap_319_288 description 253 <legal all> 254 */ 255 256 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 257 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 258 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 259 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff 260 261 262 /* Description RX_BITMAP_479_448 263 264 See Rx_bitmap_319_288 description 265 <legal all> 266 */ 267 268 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 269 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 270 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 271 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff 272 273 274 /* Description RX_BITMAP_511_480 275 276 See Rx_bitmap_319_288 description 277 <legal all> 278 */ 279 280 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c 281 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 282 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 283 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff 284 285 286 /* Description RX_BITMAP_543_512 287 288 See Rx_bitmap_319_288 description 289 <legal all> 290 */ 291 292 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 293 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 294 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 295 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff 296 297 298 /* Description RX_BITMAP_575_544 299 300 See Rx_bitmap_319_288 description 301 <legal all> 302 */ 303 304 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 305 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 306 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 307 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff 308 309 310 /* Description RX_BITMAP_607_576 311 312 See Rx_bitmap_319_288 description 313 <legal all> 314 */ 315 316 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 317 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 318 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 319 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff 320 321 322 /* Description RX_BITMAP_639_608 323 324 See Rx_bitmap_319_288 description 325 <legal all> 326 */ 327 328 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c 329 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 330 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 331 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff 332 333 334 /* Description RX_BITMAP_671_640 335 336 See Rx_bitmap_319_288 description 337 <legal all> 338 */ 339 340 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 341 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 342 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 343 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff 344 345 346 /* Description RX_BITMAP_703_672 347 348 See Rx_bitmap_319_288 description 349 <legal all> 350 */ 351 352 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 353 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 354 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 355 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff 356 357 358 /* Description RX_BITMAP_735_704 359 360 See Rx_bitmap_319_288 description 361 <legal all> 362 */ 363 364 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 365 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 366 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 367 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff 368 369 370 /* Description RX_BITMAP_767_736 371 372 See Rx_bitmap_319_288 description 373 <legal all> 374 */ 375 376 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c 377 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 378 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 379 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff 380 381 382 /* Description RX_BITMAP_799_768 383 384 See Rx_bitmap_319_288 description 385 <legal all> 386 */ 387 388 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 389 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 390 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 391 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff 392 393 394 /* Description RX_BITMAP_831_800 395 396 See Rx_bitmap_319_288 description 397 <legal all> 398 */ 399 400 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 401 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 402 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 403 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff 404 405 406 /* Description RX_BITMAP_863_832 407 408 See Rx_bitmap_319_288 description 409 <legal all> 410 */ 411 412 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 413 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 414 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 415 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff 416 417 418 /* Description RX_BITMAP_895_864 419 420 See Rx_bitmap_319_288 description 421 <legal all> 422 */ 423 424 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c 425 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 426 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 427 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff 428 429 430 /* Description RX_BITMAP_927_896 431 432 See Rx_bitmap_319_288 description 433 <legal all> 434 */ 435 436 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 437 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 438 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 439 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff 440 441 442 /* Description RX_BITMAP_959_928 443 444 See Rx_bitmap_319_288 description 445 <legal all> 446 */ 447 448 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 449 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 450 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 451 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff 452 453 454 /* Description RX_BITMAP_991_960 455 456 See Rx_bitmap_319_288 description 457 <legal all> 458 */ 459 460 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 461 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 462 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 463 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff 464 465 466 /* Description RX_BITMAP_1023_992 467 468 See Rx_bitmap_319_288 description 469 <legal all> 470 */ 471 472 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c 473 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 474 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 475 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff 476 477 478 /* Description RESERVED_24 479 480 <legal 0> 481 */ 482 483 #define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 484 #define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 485 #define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 486 #define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff 487 488 489 /* Description RESERVED_25 490 491 <legal 0> 492 */ 493 494 #define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 495 #define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 496 #define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 497 #define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff 498 499 500 /* Description RESERVED_26 501 502 <legal 0> 503 */ 504 505 #define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 506 #define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 507 #define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 508 #define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff 509 510 511 /* Description RESERVED_27 512 513 <legal 0> 514 */ 515 516 #define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c 517 #define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 518 #define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 519 #define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff 520 521 522 /* Description RESERVED_28 523 524 <legal 0> 525 */ 526 527 #define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 528 #define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 529 #define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 530 #define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff 531 532 533 /* Description RESERVED_29 534 535 <legal 0> 536 */ 537 538 #define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 539 #define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 540 #define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 541 #define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff 542 543 544 /* Description RESERVED_30 545 546 <legal 0> 547 */ 548 549 #define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 550 #define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 551 #define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 552 #define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff 553 554 555 /* Description RESERVED_31 556 557 <legal 0> 558 */ 559 560 #define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c 561 #define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 562 #define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 563 #define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff 564 565 566 567 #endif // RX_REO_QUEUE_1K 568