1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _RX_REO_QUEUE_EXT_H_ 18*5113495bSYour Name #define _RX_REO_QUEUE_EXT_H_ 19*5113495bSYour Name #if !defined(__ASSEMBLER__) 20*5113495bSYour Name #endif 21*5113495bSYour Name 22*5113495bSYour Name #include "rx_mpdu_link_ptr.h" 23*5113495bSYour Name #include "uniform_descriptor_header.h" 24*5113495bSYour Name #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 25*5113495bSYour Name 26*5113495bSYour Name 27*5113495bSYour Name struct rx_reo_queue_ext { 28*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29*5113495bSYour Name struct uniform_descriptor_header descriptor_header; 30*5113495bSYour Name uint32_t reserved_1a : 32; // [31:0] 31*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_0; 32*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_1; 33*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_2; 34*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_3; 35*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_4; 36*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_5; 37*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_6; 38*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_7; 39*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_8; 40*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_9; 41*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_10; 42*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_11; 43*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_12; 44*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_13; 45*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_14; 46*5113495bSYour Name #else 47*5113495bSYour Name struct uniform_descriptor_header descriptor_header; 48*5113495bSYour Name uint32_t reserved_1a : 32; // [31:0] 49*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_0; 50*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_1; 51*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_2; 52*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_3; 53*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_4; 54*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_5; 55*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_6; 56*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_7; 57*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_8; 58*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_9; 59*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_10; 60*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_11; 61*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_12; 62*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_13; 63*5113495bSYour Name struct rx_mpdu_link_ptr mpdu_link_pointer_14; 64*5113495bSYour Name #endif 65*5113495bSYour Name }; 66*5113495bSYour Name 67*5113495bSYour Name 68*5113495bSYour Name /* Description DESCRIPTOR_HEADER 69*5113495bSYour Name 70*5113495bSYour Name Details about which module owns this struct. 71*5113495bSYour Name Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor" 72*5113495bSYour Name 73*5113495bSYour Name */ 74*5113495bSYour Name 75*5113495bSYour Name 76*5113495bSYour Name /* Description OWNER 77*5113495bSYour Name 78*5113495bSYour Name Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 79*5113495bSYour Name Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 80*5113495bSYour Name 81*5113495bSYour Name The owner of this data structure: 82*5113495bSYour Name <enum 0 WBM_owned> Buffer Manager currently owns this data 83*5113495bSYour Name structure. 84*5113495bSYour Name <enum 1 SW_OR_FW_owned> Software of FW currently owns this 85*5113495bSYour Name data structure. 86*5113495bSYour Name <enum 2 TQM_owned> Transmit Queue Manager currently owns 87*5113495bSYour Name this data structure. 88*5113495bSYour Name <enum 3 RXDMA_owned> Receive DMA currently owns this data 89*5113495bSYour Name structure. 90*5113495bSYour Name <enum 4 REO_owned> Reorder currently owns this data structure. 91*5113495bSYour Name 92*5113495bSYour Name <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 93*5113495bSYour Name 94*5113495bSYour Name 95*5113495bSYour Name <legal 0-5> 96*5113495bSYour Name */ 97*5113495bSYour Name 98*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 99*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 100*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 101*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 102*5113495bSYour Name 103*5113495bSYour Name 104*5113495bSYour Name /* Description BUFFER_TYPE 105*5113495bSYour Name 106*5113495bSYour Name Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 107*5113495bSYour Name Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 108*5113495bSYour Name 109*5113495bSYour Name Field describing what contents format is of this descriptor 110*5113495bSYour Name 111*5113495bSYour Name 112*5113495bSYour Name <enum 0 Transmit_MSDU_Link_descriptor> 113*5113495bSYour Name <enum 1 Transmit_MPDU_Link_descriptor> 114*5113495bSYour Name <enum 2 Transmit_MPDU_Queue_head_descriptor> 115*5113495bSYour Name <enum 3 Transmit_MPDU_Queue_ext_descriptor> 116*5113495bSYour Name <enum 4 Transmit_flow_descriptor> 117*5113495bSYour Name <enum 5 Transmit_buffer> NOT TO BE USED: 118*5113495bSYour Name 119*5113495bSYour Name <enum 6 Receive_MSDU_Link_descriptor> 120*5113495bSYour Name <enum 7 Receive_MPDU_Link_descriptor> 121*5113495bSYour Name <enum 8 Receive_REO_queue_descriptor> 122*5113495bSYour Name <enum 9 Receive_REO_queue_1k_descriptor> 123*5113495bSYour Name <enum 10 Receive_REO_queue_ext_descriptor> 124*5113495bSYour Name 125*5113495bSYour Name <enum 11 Receive_buffer> 126*5113495bSYour Name 127*5113495bSYour Name <enum 12 Idle_link_list_entry> 128*5113495bSYour Name 129*5113495bSYour Name <legal 0-12> 130*5113495bSYour Name */ 131*5113495bSYour Name 132*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 133*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 134*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 135*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 136*5113495bSYour Name 137*5113495bSYour Name 138*5113495bSYour Name /* Description TX_MPDU_QUEUE_NUMBER 139*5113495bSYour Name 140*5113495bSYour Name Consumer: TQM/Debug 141*5113495bSYour Name Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 142*5113495bSYour Name 143*5113495bSYour Name Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 144*5113495bSYour Name 145*5113495bSYour Name 146*5113495bSYour Name Indicates the MPDU queue ID to which this MPDU descriptor 147*5113495bSYour Name belongs 148*5113495bSYour Name Used for tracking and debugging 149*5113495bSYour Name 150*5113495bSYour Name <legal all> 151*5113495bSYour Name */ 152*5113495bSYour Name 153*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 154*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 155*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 156*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 157*5113495bSYour Name 158*5113495bSYour Name 159*5113495bSYour Name /* Description RESERVED_0A 160*5113495bSYour Name 161*5113495bSYour Name <legal 0> 162*5113495bSYour Name */ 163*5113495bSYour Name 164*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 165*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 166*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 167*5113495bSYour Name #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 168*5113495bSYour Name 169*5113495bSYour Name 170*5113495bSYour Name /* Description RESERVED_1A 171*5113495bSYour Name 172*5113495bSYour Name <legal 0> 173*5113495bSYour Name */ 174*5113495bSYour Name 175*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 176*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 177*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 178*5113495bSYour Name #define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff 179*5113495bSYour Name 180*5113495bSYour Name 181*5113495bSYour Name /* Description MPDU_LINK_POINTER_0 182*5113495bSYour Name 183*5113495bSYour Name Consumer: REO 184*5113495bSYour Name Producer: REO 185*5113495bSYour Name 186*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 187*5113495bSYour Name 188*5113495bSYour Name */ 189*5113495bSYour Name 190*5113495bSYour Name 191*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 192*5113495bSYour Name 193*5113495bSYour Name Details of the physical address of an MPDU link descriptor 194*5113495bSYour Name 195*5113495bSYour Name */ 196*5113495bSYour Name 197*5113495bSYour Name 198*5113495bSYour Name /* Description BUFFER_ADDR_31_0 199*5113495bSYour Name 200*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 201*5113495bSYour Name descriptor OR Link Descriptor 202*5113495bSYour Name 203*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 204*5113495bSYour Name <legal all> 205*5113495bSYour Name */ 206*5113495bSYour Name 207*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 208*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 209*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 210*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 211*5113495bSYour Name 212*5113495bSYour Name 213*5113495bSYour Name /* Description BUFFER_ADDR_39_32 214*5113495bSYour Name 215*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 216*5113495bSYour Name descriptor OR Link Descriptor 217*5113495bSYour Name 218*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 219*5113495bSYour Name <legal all> 220*5113495bSYour Name */ 221*5113495bSYour Name 222*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 223*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 224*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 225*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 226*5113495bSYour Name 227*5113495bSYour Name 228*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 229*5113495bSYour Name 230*5113495bSYour Name Consumer: WBM 231*5113495bSYour Name Producer: SW/FW 232*5113495bSYour Name 233*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 234*5113495bSYour Name 235*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 236*5113495bSYour Name descriptor OR link descriptor that is being pointed to 237*5113495bSYour Name shall be returned after the frame has been processed. It 238*5113495bSYour Name is used by WBM for routing purposes. 239*5113495bSYour Name 240*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 241*5113495bSYour Name to the WMB buffer idle list 242*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 243*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 244*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 245*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 246*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 247*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 248*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 249*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 250*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 251*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 252*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 253*5113495bSYour Name ring 0 254*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 255*5113495bSYour Name ring 1 256*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 257*5113495bSYour Name ring 2 258*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 259*5113495bSYour Name ring 3 260*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 261*5113495bSYour Name ring 4 262*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 263*5113495bSYour Name ring 5 264*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 265*5113495bSYour Name ring 6 266*5113495bSYour Name 267*5113495bSYour Name <legal 0-12> 268*5113495bSYour Name */ 269*5113495bSYour Name 270*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 271*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 272*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 273*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 274*5113495bSYour Name 275*5113495bSYour Name 276*5113495bSYour Name /* Description SW_BUFFER_COOKIE 277*5113495bSYour Name 278*5113495bSYour Name Cookie field exclusively used by SW. 279*5113495bSYour Name 280*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 281*5113495bSYour Name 282*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 283*5113495bSYour Name value on to other descriptors together with the physical 284*5113495bSYour Name address 285*5113495bSYour Name 286*5113495bSYour Name Field can be used by SW to for example associate the buffers 287*5113495bSYour Name physical address with the virtual address 288*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 289*5113495bSYour Name 290*5113495bSYour Name 291*5113495bSYour Name NOTE1: 292*5113495bSYour Name The three most significant bits can have a special meaning 293*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 294*5113495bSYour Name and field transmit_bw_restriction is set 295*5113495bSYour Name 296*5113495bSYour Name In case of NON punctured transmission: 297*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 298*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 299*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 300*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 301*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 302*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 303*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 304*5113495bSYour Name 305*5113495bSYour Name In case of punctured transmission: 306*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 307*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 308*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 309*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 310*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 311*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 312*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 313*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 314*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 315*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 316*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 317*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 318*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 319*5113495bSYour Name 320*5113495bSYour Name Note: a punctured transmission is indicated by the presence 321*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 322*5113495bSYour Name 323*5113495bSYour Name <legal all> 324*5113495bSYour Name */ 325*5113495bSYour Name 326*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 327*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 328*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 329*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 330*5113495bSYour Name 331*5113495bSYour Name 332*5113495bSYour Name /* Description MPDU_LINK_POINTER_1 333*5113495bSYour Name 334*5113495bSYour Name Consumer: REO 335*5113495bSYour Name Producer: REO 336*5113495bSYour Name 337*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 338*5113495bSYour Name 339*5113495bSYour Name */ 340*5113495bSYour Name 341*5113495bSYour Name 342*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 343*5113495bSYour Name 344*5113495bSYour Name Details of the physical address of an MPDU link descriptor 345*5113495bSYour Name 346*5113495bSYour Name */ 347*5113495bSYour Name 348*5113495bSYour Name 349*5113495bSYour Name /* Description BUFFER_ADDR_31_0 350*5113495bSYour Name 351*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 352*5113495bSYour Name descriptor OR Link Descriptor 353*5113495bSYour Name 354*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 355*5113495bSYour Name <legal all> 356*5113495bSYour Name */ 357*5113495bSYour Name 358*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 359*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 360*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 361*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 362*5113495bSYour Name 363*5113495bSYour Name 364*5113495bSYour Name /* Description BUFFER_ADDR_39_32 365*5113495bSYour Name 366*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 367*5113495bSYour Name descriptor OR Link Descriptor 368*5113495bSYour Name 369*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 370*5113495bSYour Name <legal all> 371*5113495bSYour Name */ 372*5113495bSYour Name 373*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 374*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 375*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 376*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 377*5113495bSYour Name 378*5113495bSYour Name 379*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 380*5113495bSYour Name 381*5113495bSYour Name Consumer: WBM 382*5113495bSYour Name Producer: SW/FW 383*5113495bSYour Name 384*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 385*5113495bSYour Name 386*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 387*5113495bSYour Name descriptor OR link descriptor that is being pointed to 388*5113495bSYour Name shall be returned after the frame has been processed. It 389*5113495bSYour Name is used by WBM for routing purposes. 390*5113495bSYour Name 391*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 392*5113495bSYour Name to the WMB buffer idle list 393*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 394*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 395*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 396*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 397*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 398*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 399*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 400*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 401*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 402*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 403*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 404*5113495bSYour Name ring 0 405*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 406*5113495bSYour Name ring 1 407*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 408*5113495bSYour Name ring 2 409*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 410*5113495bSYour Name ring 3 411*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 412*5113495bSYour Name ring 4 413*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 414*5113495bSYour Name ring 5 415*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 416*5113495bSYour Name ring 6 417*5113495bSYour Name 418*5113495bSYour Name <legal 0-12> 419*5113495bSYour Name */ 420*5113495bSYour Name 421*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 422*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 423*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 424*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 425*5113495bSYour Name 426*5113495bSYour Name 427*5113495bSYour Name /* Description SW_BUFFER_COOKIE 428*5113495bSYour Name 429*5113495bSYour Name Cookie field exclusively used by SW. 430*5113495bSYour Name 431*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 432*5113495bSYour Name 433*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 434*5113495bSYour Name value on to other descriptors together with the physical 435*5113495bSYour Name address 436*5113495bSYour Name 437*5113495bSYour Name Field can be used by SW to for example associate the buffers 438*5113495bSYour Name physical address with the virtual address 439*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 440*5113495bSYour Name 441*5113495bSYour Name 442*5113495bSYour Name NOTE1: 443*5113495bSYour Name The three most significant bits can have a special meaning 444*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 445*5113495bSYour Name and field transmit_bw_restriction is set 446*5113495bSYour Name 447*5113495bSYour Name In case of NON punctured transmission: 448*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 449*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 450*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 451*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 452*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 453*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 454*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 455*5113495bSYour Name 456*5113495bSYour Name In case of punctured transmission: 457*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 458*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 459*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 460*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 461*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 462*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 463*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 464*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 465*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 466*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 467*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 468*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 469*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 470*5113495bSYour Name 471*5113495bSYour Name Note: a punctured transmission is indicated by the presence 472*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 473*5113495bSYour Name 474*5113495bSYour Name <legal all> 475*5113495bSYour Name */ 476*5113495bSYour Name 477*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 478*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 479*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 480*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 481*5113495bSYour Name 482*5113495bSYour Name 483*5113495bSYour Name /* Description MPDU_LINK_POINTER_2 484*5113495bSYour Name 485*5113495bSYour Name Consumer: REO 486*5113495bSYour Name Producer: REO 487*5113495bSYour Name 488*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 489*5113495bSYour Name 490*5113495bSYour Name */ 491*5113495bSYour Name 492*5113495bSYour Name 493*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 494*5113495bSYour Name 495*5113495bSYour Name Details of the physical address of an MPDU link descriptor 496*5113495bSYour Name 497*5113495bSYour Name */ 498*5113495bSYour Name 499*5113495bSYour Name 500*5113495bSYour Name /* Description BUFFER_ADDR_31_0 501*5113495bSYour Name 502*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 503*5113495bSYour Name descriptor OR Link Descriptor 504*5113495bSYour Name 505*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 506*5113495bSYour Name <legal all> 507*5113495bSYour Name */ 508*5113495bSYour Name 509*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 510*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 511*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 512*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 513*5113495bSYour Name 514*5113495bSYour Name 515*5113495bSYour Name /* Description BUFFER_ADDR_39_32 516*5113495bSYour Name 517*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 518*5113495bSYour Name descriptor OR Link Descriptor 519*5113495bSYour Name 520*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 521*5113495bSYour Name <legal all> 522*5113495bSYour Name */ 523*5113495bSYour Name 524*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 525*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 526*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 527*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 528*5113495bSYour Name 529*5113495bSYour Name 530*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 531*5113495bSYour Name 532*5113495bSYour Name Consumer: WBM 533*5113495bSYour Name Producer: SW/FW 534*5113495bSYour Name 535*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 536*5113495bSYour Name 537*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 538*5113495bSYour Name descriptor OR link descriptor that is being pointed to 539*5113495bSYour Name shall be returned after the frame has been processed. It 540*5113495bSYour Name is used by WBM for routing purposes. 541*5113495bSYour Name 542*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 543*5113495bSYour Name to the WMB buffer idle list 544*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 545*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 546*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 547*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 548*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 549*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 550*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 551*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 552*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 553*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 554*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 555*5113495bSYour Name ring 0 556*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 557*5113495bSYour Name ring 1 558*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 559*5113495bSYour Name ring 2 560*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 561*5113495bSYour Name ring 3 562*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 563*5113495bSYour Name ring 4 564*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 565*5113495bSYour Name ring 5 566*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 567*5113495bSYour Name ring 6 568*5113495bSYour Name 569*5113495bSYour Name <legal 0-12> 570*5113495bSYour Name */ 571*5113495bSYour Name 572*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 573*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 574*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 575*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 576*5113495bSYour Name 577*5113495bSYour Name 578*5113495bSYour Name /* Description SW_BUFFER_COOKIE 579*5113495bSYour Name 580*5113495bSYour Name Cookie field exclusively used by SW. 581*5113495bSYour Name 582*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 583*5113495bSYour Name 584*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 585*5113495bSYour Name value on to other descriptors together with the physical 586*5113495bSYour Name address 587*5113495bSYour Name 588*5113495bSYour Name Field can be used by SW to for example associate the buffers 589*5113495bSYour Name physical address with the virtual address 590*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 591*5113495bSYour Name 592*5113495bSYour Name 593*5113495bSYour Name NOTE1: 594*5113495bSYour Name The three most significant bits can have a special meaning 595*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 596*5113495bSYour Name and field transmit_bw_restriction is set 597*5113495bSYour Name 598*5113495bSYour Name In case of NON punctured transmission: 599*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 600*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 601*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 602*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 603*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 604*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 605*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 606*5113495bSYour Name 607*5113495bSYour Name In case of punctured transmission: 608*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 609*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 610*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 611*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 612*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 613*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 614*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 615*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 616*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 617*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 618*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 619*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 620*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 621*5113495bSYour Name 622*5113495bSYour Name Note: a punctured transmission is indicated by the presence 623*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 624*5113495bSYour Name 625*5113495bSYour Name <legal all> 626*5113495bSYour Name */ 627*5113495bSYour Name 628*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 629*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 630*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 631*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 632*5113495bSYour Name 633*5113495bSYour Name 634*5113495bSYour Name /* Description MPDU_LINK_POINTER_3 635*5113495bSYour Name 636*5113495bSYour Name Consumer: REO 637*5113495bSYour Name Producer: REO 638*5113495bSYour Name 639*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 640*5113495bSYour Name 641*5113495bSYour Name */ 642*5113495bSYour Name 643*5113495bSYour Name 644*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 645*5113495bSYour Name 646*5113495bSYour Name Details of the physical address of an MPDU link descriptor 647*5113495bSYour Name 648*5113495bSYour Name */ 649*5113495bSYour Name 650*5113495bSYour Name 651*5113495bSYour Name /* Description BUFFER_ADDR_31_0 652*5113495bSYour Name 653*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 654*5113495bSYour Name descriptor OR Link Descriptor 655*5113495bSYour Name 656*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 657*5113495bSYour Name <legal all> 658*5113495bSYour Name */ 659*5113495bSYour Name 660*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 661*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 662*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 663*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 664*5113495bSYour Name 665*5113495bSYour Name 666*5113495bSYour Name /* Description BUFFER_ADDR_39_32 667*5113495bSYour Name 668*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 669*5113495bSYour Name descriptor OR Link Descriptor 670*5113495bSYour Name 671*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 672*5113495bSYour Name <legal all> 673*5113495bSYour Name */ 674*5113495bSYour Name 675*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 676*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 677*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 678*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 679*5113495bSYour Name 680*5113495bSYour Name 681*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 682*5113495bSYour Name 683*5113495bSYour Name Consumer: WBM 684*5113495bSYour Name Producer: SW/FW 685*5113495bSYour Name 686*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 687*5113495bSYour Name 688*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 689*5113495bSYour Name descriptor OR link descriptor that is being pointed to 690*5113495bSYour Name shall be returned after the frame has been processed. It 691*5113495bSYour Name is used by WBM for routing purposes. 692*5113495bSYour Name 693*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 694*5113495bSYour Name to the WMB buffer idle list 695*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 696*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 697*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 698*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 699*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 700*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 701*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 702*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 703*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 704*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 705*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 706*5113495bSYour Name ring 0 707*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 708*5113495bSYour Name ring 1 709*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 710*5113495bSYour Name ring 2 711*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 712*5113495bSYour Name ring 3 713*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 714*5113495bSYour Name ring 4 715*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 716*5113495bSYour Name ring 5 717*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 718*5113495bSYour Name ring 6 719*5113495bSYour Name 720*5113495bSYour Name <legal 0-12> 721*5113495bSYour Name */ 722*5113495bSYour Name 723*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 724*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 725*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 726*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 727*5113495bSYour Name 728*5113495bSYour Name 729*5113495bSYour Name /* Description SW_BUFFER_COOKIE 730*5113495bSYour Name 731*5113495bSYour Name Cookie field exclusively used by SW. 732*5113495bSYour Name 733*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 734*5113495bSYour Name 735*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 736*5113495bSYour Name value on to other descriptors together with the physical 737*5113495bSYour Name address 738*5113495bSYour Name 739*5113495bSYour Name Field can be used by SW to for example associate the buffers 740*5113495bSYour Name physical address with the virtual address 741*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 742*5113495bSYour Name 743*5113495bSYour Name 744*5113495bSYour Name NOTE1: 745*5113495bSYour Name The three most significant bits can have a special meaning 746*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 747*5113495bSYour Name and field transmit_bw_restriction is set 748*5113495bSYour Name 749*5113495bSYour Name In case of NON punctured transmission: 750*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 751*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 752*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 753*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 754*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 755*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 756*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 757*5113495bSYour Name 758*5113495bSYour Name In case of punctured transmission: 759*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 760*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 761*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 762*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 763*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 764*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 765*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 766*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 767*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 768*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 769*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 770*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 771*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 772*5113495bSYour Name 773*5113495bSYour Name Note: a punctured transmission is indicated by the presence 774*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 775*5113495bSYour Name 776*5113495bSYour Name <legal all> 777*5113495bSYour Name */ 778*5113495bSYour Name 779*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 780*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 781*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 782*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 783*5113495bSYour Name 784*5113495bSYour Name 785*5113495bSYour Name /* Description MPDU_LINK_POINTER_4 786*5113495bSYour Name 787*5113495bSYour Name Consumer: REO 788*5113495bSYour Name Producer: REO 789*5113495bSYour Name 790*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 791*5113495bSYour Name 792*5113495bSYour Name */ 793*5113495bSYour Name 794*5113495bSYour Name 795*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 796*5113495bSYour Name 797*5113495bSYour Name Details of the physical address of an MPDU link descriptor 798*5113495bSYour Name 799*5113495bSYour Name */ 800*5113495bSYour Name 801*5113495bSYour Name 802*5113495bSYour Name /* Description BUFFER_ADDR_31_0 803*5113495bSYour Name 804*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 805*5113495bSYour Name descriptor OR Link Descriptor 806*5113495bSYour Name 807*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 808*5113495bSYour Name <legal all> 809*5113495bSYour Name */ 810*5113495bSYour Name 811*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 812*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 813*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 814*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 815*5113495bSYour Name 816*5113495bSYour Name 817*5113495bSYour Name /* Description BUFFER_ADDR_39_32 818*5113495bSYour Name 819*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 820*5113495bSYour Name descriptor OR Link Descriptor 821*5113495bSYour Name 822*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 823*5113495bSYour Name <legal all> 824*5113495bSYour Name */ 825*5113495bSYour Name 826*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 827*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 828*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 829*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 830*5113495bSYour Name 831*5113495bSYour Name 832*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 833*5113495bSYour Name 834*5113495bSYour Name Consumer: WBM 835*5113495bSYour Name Producer: SW/FW 836*5113495bSYour Name 837*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 838*5113495bSYour Name 839*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 840*5113495bSYour Name descriptor OR link descriptor that is being pointed to 841*5113495bSYour Name shall be returned after the frame has been processed. It 842*5113495bSYour Name is used by WBM for routing purposes. 843*5113495bSYour Name 844*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 845*5113495bSYour Name to the WMB buffer idle list 846*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 847*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 848*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 849*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 850*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 851*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 852*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 853*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 854*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 855*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 856*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 857*5113495bSYour Name ring 0 858*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 859*5113495bSYour Name ring 1 860*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 861*5113495bSYour Name ring 2 862*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 863*5113495bSYour Name ring 3 864*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 865*5113495bSYour Name ring 4 866*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 867*5113495bSYour Name ring 5 868*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 869*5113495bSYour Name ring 6 870*5113495bSYour Name 871*5113495bSYour Name <legal 0-12> 872*5113495bSYour Name */ 873*5113495bSYour Name 874*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 875*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 876*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 877*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 878*5113495bSYour Name 879*5113495bSYour Name 880*5113495bSYour Name /* Description SW_BUFFER_COOKIE 881*5113495bSYour Name 882*5113495bSYour Name Cookie field exclusively used by SW. 883*5113495bSYour Name 884*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 885*5113495bSYour Name 886*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 887*5113495bSYour Name value on to other descriptors together with the physical 888*5113495bSYour Name address 889*5113495bSYour Name 890*5113495bSYour Name Field can be used by SW to for example associate the buffers 891*5113495bSYour Name physical address with the virtual address 892*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 893*5113495bSYour Name 894*5113495bSYour Name 895*5113495bSYour Name NOTE1: 896*5113495bSYour Name The three most significant bits can have a special meaning 897*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 898*5113495bSYour Name and field transmit_bw_restriction is set 899*5113495bSYour Name 900*5113495bSYour Name In case of NON punctured transmission: 901*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 902*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 903*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 904*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 905*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 906*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 907*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 908*5113495bSYour Name 909*5113495bSYour Name In case of punctured transmission: 910*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 911*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 912*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 913*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 914*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 915*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 916*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 917*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 918*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 919*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 920*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 921*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 922*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 923*5113495bSYour Name 924*5113495bSYour Name Note: a punctured transmission is indicated by the presence 925*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 926*5113495bSYour Name 927*5113495bSYour Name <legal all> 928*5113495bSYour Name */ 929*5113495bSYour Name 930*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 931*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 932*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 933*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 934*5113495bSYour Name 935*5113495bSYour Name 936*5113495bSYour Name /* Description MPDU_LINK_POINTER_5 937*5113495bSYour Name 938*5113495bSYour Name Consumer: REO 939*5113495bSYour Name Producer: REO 940*5113495bSYour Name 941*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 942*5113495bSYour Name 943*5113495bSYour Name */ 944*5113495bSYour Name 945*5113495bSYour Name 946*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 947*5113495bSYour Name 948*5113495bSYour Name Details of the physical address of an MPDU link descriptor 949*5113495bSYour Name 950*5113495bSYour Name */ 951*5113495bSYour Name 952*5113495bSYour Name 953*5113495bSYour Name /* Description BUFFER_ADDR_31_0 954*5113495bSYour Name 955*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 956*5113495bSYour Name descriptor OR Link Descriptor 957*5113495bSYour Name 958*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 959*5113495bSYour Name <legal all> 960*5113495bSYour Name */ 961*5113495bSYour Name 962*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 963*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 964*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 965*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 966*5113495bSYour Name 967*5113495bSYour Name 968*5113495bSYour Name /* Description BUFFER_ADDR_39_32 969*5113495bSYour Name 970*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 971*5113495bSYour Name descriptor OR Link Descriptor 972*5113495bSYour Name 973*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 974*5113495bSYour Name <legal all> 975*5113495bSYour Name */ 976*5113495bSYour Name 977*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 978*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 979*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 980*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 981*5113495bSYour Name 982*5113495bSYour Name 983*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 984*5113495bSYour Name 985*5113495bSYour Name Consumer: WBM 986*5113495bSYour Name Producer: SW/FW 987*5113495bSYour Name 988*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 989*5113495bSYour Name 990*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 991*5113495bSYour Name descriptor OR link descriptor that is being pointed to 992*5113495bSYour Name shall be returned after the frame has been processed. It 993*5113495bSYour Name is used by WBM for routing purposes. 994*5113495bSYour Name 995*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 996*5113495bSYour Name to the WMB buffer idle list 997*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 998*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 999*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1000*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1001*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1002*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1003*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1004*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1005*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1006*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1007*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1008*5113495bSYour Name ring 0 1009*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1010*5113495bSYour Name ring 1 1011*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1012*5113495bSYour Name ring 2 1013*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1014*5113495bSYour Name ring 3 1015*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1016*5113495bSYour Name ring 4 1017*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1018*5113495bSYour Name ring 5 1019*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1020*5113495bSYour Name ring 6 1021*5113495bSYour Name 1022*5113495bSYour Name <legal 0-12> 1023*5113495bSYour Name */ 1024*5113495bSYour Name 1025*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1026*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1027*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1028*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1029*5113495bSYour Name 1030*5113495bSYour Name 1031*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1032*5113495bSYour Name 1033*5113495bSYour Name Cookie field exclusively used by SW. 1034*5113495bSYour Name 1035*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1036*5113495bSYour Name 1037*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1038*5113495bSYour Name value on to other descriptors together with the physical 1039*5113495bSYour Name address 1040*5113495bSYour Name 1041*5113495bSYour Name Field can be used by SW to for example associate the buffers 1042*5113495bSYour Name physical address with the virtual address 1043*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1044*5113495bSYour Name 1045*5113495bSYour Name 1046*5113495bSYour Name NOTE1: 1047*5113495bSYour Name The three most significant bits can have a special meaning 1048*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1049*5113495bSYour Name and field transmit_bw_restriction is set 1050*5113495bSYour Name 1051*5113495bSYour Name In case of NON punctured transmission: 1052*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1053*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1054*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1055*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1056*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1057*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1058*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1059*5113495bSYour Name 1060*5113495bSYour Name In case of punctured transmission: 1061*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1062*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1063*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1064*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1065*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1066*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1067*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1068*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1069*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1070*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1071*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1072*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1073*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1074*5113495bSYour Name 1075*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1076*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1077*5113495bSYour Name 1078*5113495bSYour Name <legal all> 1079*5113495bSYour Name */ 1080*5113495bSYour Name 1081*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1082*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1083*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1084*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1085*5113495bSYour Name 1086*5113495bSYour Name 1087*5113495bSYour Name /* Description MPDU_LINK_POINTER_6 1088*5113495bSYour Name 1089*5113495bSYour Name Consumer: REO 1090*5113495bSYour Name Producer: REO 1091*5113495bSYour Name 1092*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1093*5113495bSYour Name 1094*5113495bSYour Name */ 1095*5113495bSYour Name 1096*5113495bSYour Name 1097*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1098*5113495bSYour Name 1099*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1100*5113495bSYour Name 1101*5113495bSYour Name */ 1102*5113495bSYour Name 1103*5113495bSYour Name 1104*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1105*5113495bSYour Name 1106*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1107*5113495bSYour Name descriptor OR Link Descriptor 1108*5113495bSYour Name 1109*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1110*5113495bSYour Name <legal all> 1111*5113495bSYour Name */ 1112*5113495bSYour Name 1113*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1114*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1115*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1116*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1117*5113495bSYour Name 1118*5113495bSYour Name 1119*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1120*5113495bSYour Name 1121*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1122*5113495bSYour Name descriptor OR Link Descriptor 1123*5113495bSYour Name 1124*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1125*5113495bSYour Name <legal all> 1126*5113495bSYour Name */ 1127*5113495bSYour Name 1128*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1129*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1130*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1131*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1132*5113495bSYour Name 1133*5113495bSYour Name 1134*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1135*5113495bSYour Name 1136*5113495bSYour Name Consumer: WBM 1137*5113495bSYour Name Producer: SW/FW 1138*5113495bSYour Name 1139*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1140*5113495bSYour Name 1141*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1142*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1143*5113495bSYour Name shall be returned after the frame has been processed. It 1144*5113495bSYour Name is used by WBM for routing purposes. 1145*5113495bSYour Name 1146*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1147*5113495bSYour Name to the WMB buffer idle list 1148*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1149*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1150*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1151*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1152*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1153*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1154*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1155*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1156*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1157*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1158*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1159*5113495bSYour Name ring 0 1160*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1161*5113495bSYour Name ring 1 1162*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1163*5113495bSYour Name ring 2 1164*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1165*5113495bSYour Name ring 3 1166*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1167*5113495bSYour Name ring 4 1168*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1169*5113495bSYour Name ring 5 1170*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1171*5113495bSYour Name ring 6 1172*5113495bSYour Name 1173*5113495bSYour Name <legal 0-12> 1174*5113495bSYour Name */ 1175*5113495bSYour Name 1176*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1177*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1178*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1179*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1180*5113495bSYour Name 1181*5113495bSYour Name 1182*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1183*5113495bSYour Name 1184*5113495bSYour Name Cookie field exclusively used by SW. 1185*5113495bSYour Name 1186*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1187*5113495bSYour Name 1188*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1189*5113495bSYour Name value on to other descriptors together with the physical 1190*5113495bSYour Name address 1191*5113495bSYour Name 1192*5113495bSYour Name Field can be used by SW to for example associate the buffers 1193*5113495bSYour Name physical address with the virtual address 1194*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1195*5113495bSYour Name 1196*5113495bSYour Name 1197*5113495bSYour Name NOTE1: 1198*5113495bSYour Name The three most significant bits can have a special meaning 1199*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1200*5113495bSYour Name and field transmit_bw_restriction is set 1201*5113495bSYour Name 1202*5113495bSYour Name In case of NON punctured transmission: 1203*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1204*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1205*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1206*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1207*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1208*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1209*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1210*5113495bSYour Name 1211*5113495bSYour Name In case of punctured transmission: 1212*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1213*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1214*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1215*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1216*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1217*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1218*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1219*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1220*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1221*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1222*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1223*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1224*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1225*5113495bSYour Name 1226*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1227*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1228*5113495bSYour Name 1229*5113495bSYour Name <legal all> 1230*5113495bSYour Name */ 1231*5113495bSYour Name 1232*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1233*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1234*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1235*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1236*5113495bSYour Name 1237*5113495bSYour Name 1238*5113495bSYour Name /* Description MPDU_LINK_POINTER_7 1239*5113495bSYour Name 1240*5113495bSYour Name Consumer: REO 1241*5113495bSYour Name Producer: REO 1242*5113495bSYour Name 1243*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1244*5113495bSYour Name 1245*5113495bSYour Name */ 1246*5113495bSYour Name 1247*5113495bSYour Name 1248*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1249*5113495bSYour Name 1250*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1251*5113495bSYour Name 1252*5113495bSYour Name */ 1253*5113495bSYour Name 1254*5113495bSYour Name 1255*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1256*5113495bSYour Name 1257*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1258*5113495bSYour Name descriptor OR Link Descriptor 1259*5113495bSYour Name 1260*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1261*5113495bSYour Name <legal all> 1262*5113495bSYour Name */ 1263*5113495bSYour Name 1264*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1265*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1266*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1267*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1268*5113495bSYour Name 1269*5113495bSYour Name 1270*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1271*5113495bSYour Name 1272*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1273*5113495bSYour Name descriptor OR Link Descriptor 1274*5113495bSYour Name 1275*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1276*5113495bSYour Name <legal all> 1277*5113495bSYour Name */ 1278*5113495bSYour Name 1279*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1280*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1281*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1282*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1283*5113495bSYour Name 1284*5113495bSYour Name 1285*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1286*5113495bSYour Name 1287*5113495bSYour Name Consumer: WBM 1288*5113495bSYour Name Producer: SW/FW 1289*5113495bSYour Name 1290*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1291*5113495bSYour Name 1292*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1293*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1294*5113495bSYour Name shall be returned after the frame has been processed. It 1295*5113495bSYour Name is used by WBM for routing purposes. 1296*5113495bSYour Name 1297*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1298*5113495bSYour Name to the WMB buffer idle list 1299*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1300*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1301*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1302*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1303*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1304*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1305*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1306*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1307*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1308*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1309*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1310*5113495bSYour Name ring 0 1311*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1312*5113495bSYour Name ring 1 1313*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1314*5113495bSYour Name ring 2 1315*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1316*5113495bSYour Name ring 3 1317*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1318*5113495bSYour Name ring 4 1319*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1320*5113495bSYour Name ring 5 1321*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1322*5113495bSYour Name ring 6 1323*5113495bSYour Name 1324*5113495bSYour Name <legal 0-12> 1325*5113495bSYour Name */ 1326*5113495bSYour Name 1327*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1328*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1329*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1330*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1331*5113495bSYour Name 1332*5113495bSYour Name 1333*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1334*5113495bSYour Name 1335*5113495bSYour Name Cookie field exclusively used by SW. 1336*5113495bSYour Name 1337*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1338*5113495bSYour Name 1339*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1340*5113495bSYour Name value on to other descriptors together with the physical 1341*5113495bSYour Name address 1342*5113495bSYour Name 1343*5113495bSYour Name Field can be used by SW to for example associate the buffers 1344*5113495bSYour Name physical address with the virtual address 1345*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1346*5113495bSYour Name 1347*5113495bSYour Name 1348*5113495bSYour Name NOTE1: 1349*5113495bSYour Name The three most significant bits can have a special meaning 1350*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1351*5113495bSYour Name and field transmit_bw_restriction is set 1352*5113495bSYour Name 1353*5113495bSYour Name In case of NON punctured transmission: 1354*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1355*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1356*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1357*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1358*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1359*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1360*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1361*5113495bSYour Name 1362*5113495bSYour Name In case of punctured transmission: 1363*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1364*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1365*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1366*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1367*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1368*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1369*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1370*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1371*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1372*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1373*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1374*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1375*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1376*5113495bSYour Name 1377*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1378*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1379*5113495bSYour Name 1380*5113495bSYour Name <legal all> 1381*5113495bSYour Name */ 1382*5113495bSYour Name 1383*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1384*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1385*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1386*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1387*5113495bSYour Name 1388*5113495bSYour Name 1389*5113495bSYour Name /* Description MPDU_LINK_POINTER_8 1390*5113495bSYour Name 1391*5113495bSYour Name Consumer: REO 1392*5113495bSYour Name Producer: REO 1393*5113495bSYour Name 1394*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1395*5113495bSYour Name 1396*5113495bSYour Name */ 1397*5113495bSYour Name 1398*5113495bSYour Name 1399*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1400*5113495bSYour Name 1401*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1402*5113495bSYour Name 1403*5113495bSYour Name */ 1404*5113495bSYour Name 1405*5113495bSYour Name 1406*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1407*5113495bSYour Name 1408*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1409*5113495bSYour Name descriptor OR Link Descriptor 1410*5113495bSYour Name 1411*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1412*5113495bSYour Name <legal all> 1413*5113495bSYour Name */ 1414*5113495bSYour Name 1415*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1416*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1417*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1418*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1419*5113495bSYour Name 1420*5113495bSYour Name 1421*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1422*5113495bSYour Name 1423*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1424*5113495bSYour Name descriptor OR Link Descriptor 1425*5113495bSYour Name 1426*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1427*5113495bSYour Name <legal all> 1428*5113495bSYour Name */ 1429*5113495bSYour Name 1430*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1431*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1432*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1433*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1434*5113495bSYour Name 1435*5113495bSYour Name 1436*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1437*5113495bSYour Name 1438*5113495bSYour Name Consumer: WBM 1439*5113495bSYour Name Producer: SW/FW 1440*5113495bSYour Name 1441*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1442*5113495bSYour Name 1443*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1444*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1445*5113495bSYour Name shall be returned after the frame has been processed. It 1446*5113495bSYour Name is used by WBM for routing purposes. 1447*5113495bSYour Name 1448*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1449*5113495bSYour Name to the WMB buffer idle list 1450*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1451*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1452*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1453*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1454*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1455*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1456*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1457*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1458*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1459*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1460*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1461*5113495bSYour Name ring 0 1462*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1463*5113495bSYour Name ring 1 1464*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1465*5113495bSYour Name ring 2 1466*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1467*5113495bSYour Name ring 3 1468*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1469*5113495bSYour Name ring 4 1470*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1471*5113495bSYour Name ring 5 1472*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1473*5113495bSYour Name ring 6 1474*5113495bSYour Name 1475*5113495bSYour Name <legal 0-12> 1476*5113495bSYour Name */ 1477*5113495bSYour Name 1478*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1479*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1480*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1481*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1482*5113495bSYour Name 1483*5113495bSYour Name 1484*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1485*5113495bSYour Name 1486*5113495bSYour Name Cookie field exclusively used by SW. 1487*5113495bSYour Name 1488*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1489*5113495bSYour Name 1490*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1491*5113495bSYour Name value on to other descriptors together with the physical 1492*5113495bSYour Name address 1493*5113495bSYour Name 1494*5113495bSYour Name Field can be used by SW to for example associate the buffers 1495*5113495bSYour Name physical address with the virtual address 1496*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1497*5113495bSYour Name 1498*5113495bSYour Name 1499*5113495bSYour Name NOTE1: 1500*5113495bSYour Name The three most significant bits can have a special meaning 1501*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1502*5113495bSYour Name and field transmit_bw_restriction is set 1503*5113495bSYour Name 1504*5113495bSYour Name In case of NON punctured transmission: 1505*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1506*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1507*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1508*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1509*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1510*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1511*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1512*5113495bSYour Name 1513*5113495bSYour Name In case of punctured transmission: 1514*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1515*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1516*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1517*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1518*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1519*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1520*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1521*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1522*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1523*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1524*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1525*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1526*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1527*5113495bSYour Name 1528*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1529*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1530*5113495bSYour Name 1531*5113495bSYour Name <legal all> 1532*5113495bSYour Name */ 1533*5113495bSYour Name 1534*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1535*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1536*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1537*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1538*5113495bSYour Name 1539*5113495bSYour Name 1540*5113495bSYour Name /* Description MPDU_LINK_POINTER_9 1541*5113495bSYour Name 1542*5113495bSYour Name Consumer: REO 1543*5113495bSYour Name Producer: REO 1544*5113495bSYour Name 1545*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1546*5113495bSYour Name 1547*5113495bSYour Name */ 1548*5113495bSYour Name 1549*5113495bSYour Name 1550*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1551*5113495bSYour Name 1552*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1553*5113495bSYour Name 1554*5113495bSYour Name */ 1555*5113495bSYour Name 1556*5113495bSYour Name 1557*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1558*5113495bSYour Name 1559*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1560*5113495bSYour Name descriptor OR Link Descriptor 1561*5113495bSYour Name 1562*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1563*5113495bSYour Name <legal all> 1564*5113495bSYour Name */ 1565*5113495bSYour Name 1566*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1567*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1568*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1569*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1570*5113495bSYour Name 1571*5113495bSYour Name 1572*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1573*5113495bSYour Name 1574*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1575*5113495bSYour Name descriptor OR Link Descriptor 1576*5113495bSYour Name 1577*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1578*5113495bSYour Name <legal all> 1579*5113495bSYour Name */ 1580*5113495bSYour Name 1581*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1582*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1583*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1584*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1585*5113495bSYour Name 1586*5113495bSYour Name 1587*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1588*5113495bSYour Name 1589*5113495bSYour Name Consumer: WBM 1590*5113495bSYour Name Producer: SW/FW 1591*5113495bSYour Name 1592*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1593*5113495bSYour Name 1594*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1595*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1596*5113495bSYour Name shall be returned after the frame has been processed. It 1597*5113495bSYour Name is used by WBM for routing purposes. 1598*5113495bSYour Name 1599*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1600*5113495bSYour Name to the WMB buffer idle list 1601*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1602*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1603*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1604*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1605*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1606*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1607*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1608*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1609*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1610*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1611*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1612*5113495bSYour Name ring 0 1613*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1614*5113495bSYour Name ring 1 1615*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1616*5113495bSYour Name ring 2 1617*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1618*5113495bSYour Name ring 3 1619*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1620*5113495bSYour Name ring 4 1621*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1622*5113495bSYour Name ring 5 1623*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1624*5113495bSYour Name ring 6 1625*5113495bSYour Name 1626*5113495bSYour Name <legal 0-12> 1627*5113495bSYour Name */ 1628*5113495bSYour Name 1629*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1630*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1631*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1632*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1633*5113495bSYour Name 1634*5113495bSYour Name 1635*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1636*5113495bSYour Name 1637*5113495bSYour Name Cookie field exclusively used by SW. 1638*5113495bSYour Name 1639*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1640*5113495bSYour Name 1641*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1642*5113495bSYour Name value on to other descriptors together with the physical 1643*5113495bSYour Name address 1644*5113495bSYour Name 1645*5113495bSYour Name Field can be used by SW to for example associate the buffers 1646*5113495bSYour Name physical address with the virtual address 1647*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1648*5113495bSYour Name 1649*5113495bSYour Name 1650*5113495bSYour Name NOTE1: 1651*5113495bSYour Name The three most significant bits can have a special meaning 1652*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1653*5113495bSYour Name and field transmit_bw_restriction is set 1654*5113495bSYour Name 1655*5113495bSYour Name In case of NON punctured transmission: 1656*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1657*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1658*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1659*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1660*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1661*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1662*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1663*5113495bSYour Name 1664*5113495bSYour Name In case of punctured transmission: 1665*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1666*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1667*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1668*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1669*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1670*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1671*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1672*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1673*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1674*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1675*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1676*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1677*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1678*5113495bSYour Name 1679*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1680*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1681*5113495bSYour Name 1682*5113495bSYour Name <legal all> 1683*5113495bSYour Name */ 1684*5113495bSYour Name 1685*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1686*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1687*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1688*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1689*5113495bSYour Name 1690*5113495bSYour Name 1691*5113495bSYour Name /* Description MPDU_LINK_POINTER_10 1692*5113495bSYour Name 1693*5113495bSYour Name Consumer: REO 1694*5113495bSYour Name Producer: REO 1695*5113495bSYour Name 1696*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1697*5113495bSYour Name 1698*5113495bSYour Name */ 1699*5113495bSYour Name 1700*5113495bSYour Name 1701*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1702*5113495bSYour Name 1703*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1704*5113495bSYour Name 1705*5113495bSYour Name */ 1706*5113495bSYour Name 1707*5113495bSYour Name 1708*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1709*5113495bSYour Name 1710*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1711*5113495bSYour Name descriptor OR Link Descriptor 1712*5113495bSYour Name 1713*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1714*5113495bSYour Name <legal all> 1715*5113495bSYour Name */ 1716*5113495bSYour Name 1717*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 1718*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1719*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1720*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1721*5113495bSYour Name 1722*5113495bSYour Name 1723*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1724*5113495bSYour Name 1725*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1726*5113495bSYour Name descriptor OR Link Descriptor 1727*5113495bSYour Name 1728*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1729*5113495bSYour Name <legal all> 1730*5113495bSYour Name */ 1731*5113495bSYour Name 1732*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 1733*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1734*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1735*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1736*5113495bSYour Name 1737*5113495bSYour Name 1738*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1739*5113495bSYour Name 1740*5113495bSYour Name Consumer: WBM 1741*5113495bSYour Name Producer: SW/FW 1742*5113495bSYour Name 1743*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1744*5113495bSYour Name 1745*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1746*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1747*5113495bSYour Name shall be returned after the frame has been processed. It 1748*5113495bSYour Name is used by WBM for routing purposes. 1749*5113495bSYour Name 1750*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1751*5113495bSYour Name to the WMB buffer idle list 1752*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1753*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1754*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1755*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1756*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1757*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1758*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1759*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1760*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1761*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1762*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1763*5113495bSYour Name ring 0 1764*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1765*5113495bSYour Name ring 1 1766*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1767*5113495bSYour Name ring 2 1768*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1769*5113495bSYour Name ring 3 1770*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1771*5113495bSYour Name ring 4 1772*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1773*5113495bSYour Name ring 5 1774*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1775*5113495bSYour Name ring 6 1776*5113495bSYour Name 1777*5113495bSYour Name <legal 0-12> 1778*5113495bSYour Name */ 1779*5113495bSYour Name 1780*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 1781*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1782*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1783*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1784*5113495bSYour Name 1785*5113495bSYour Name 1786*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1787*5113495bSYour Name 1788*5113495bSYour Name Cookie field exclusively used by SW. 1789*5113495bSYour Name 1790*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1791*5113495bSYour Name 1792*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1793*5113495bSYour Name value on to other descriptors together with the physical 1794*5113495bSYour Name address 1795*5113495bSYour Name 1796*5113495bSYour Name Field can be used by SW to for example associate the buffers 1797*5113495bSYour Name physical address with the virtual address 1798*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1799*5113495bSYour Name 1800*5113495bSYour Name 1801*5113495bSYour Name NOTE1: 1802*5113495bSYour Name The three most significant bits can have a special meaning 1803*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1804*5113495bSYour Name and field transmit_bw_restriction is set 1805*5113495bSYour Name 1806*5113495bSYour Name In case of NON punctured transmission: 1807*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1808*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1809*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1810*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1811*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1812*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1813*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1814*5113495bSYour Name 1815*5113495bSYour Name In case of punctured transmission: 1816*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1817*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1818*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1819*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1820*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1821*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1822*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1823*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1824*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1825*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1826*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1827*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1828*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1829*5113495bSYour Name 1830*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1831*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1832*5113495bSYour Name 1833*5113495bSYour Name <legal all> 1834*5113495bSYour Name */ 1835*5113495bSYour Name 1836*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 1837*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1838*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1839*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1840*5113495bSYour Name 1841*5113495bSYour Name 1842*5113495bSYour Name /* Description MPDU_LINK_POINTER_11 1843*5113495bSYour Name 1844*5113495bSYour Name Consumer: REO 1845*5113495bSYour Name Producer: REO 1846*5113495bSYour Name 1847*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1848*5113495bSYour Name 1849*5113495bSYour Name */ 1850*5113495bSYour Name 1851*5113495bSYour Name 1852*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 1853*5113495bSYour Name 1854*5113495bSYour Name Details of the physical address of an MPDU link descriptor 1855*5113495bSYour Name 1856*5113495bSYour Name */ 1857*5113495bSYour Name 1858*5113495bSYour Name 1859*5113495bSYour Name /* Description BUFFER_ADDR_31_0 1860*5113495bSYour Name 1861*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1862*5113495bSYour Name descriptor OR Link Descriptor 1863*5113495bSYour Name 1864*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1865*5113495bSYour Name <legal all> 1866*5113495bSYour Name */ 1867*5113495bSYour Name 1868*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 1869*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1870*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1871*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1872*5113495bSYour Name 1873*5113495bSYour Name 1874*5113495bSYour Name /* Description BUFFER_ADDR_39_32 1875*5113495bSYour Name 1876*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1877*5113495bSYour Name descriptor OR Link Descriptor 1878*5113495bSYour Name 1879*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1880*5113495bSYour Name <legal all> 1881*5113495bSYour Name */ 1882*5113495bSYour Name 1883*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 1884*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1885*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1886*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1887*5113495bSYour Name 1888*5113495bSYour Name 1889*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 1890*5113495bSYour Name 1891*5113495bSYour Name Consumer: WBM 1892*5113495bSYour Name Producer: SW/FW 1893*5113495bSYour Name 1894*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1895*5113495bSYour Name 1896*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1897*5113495bSYour Name descriptor OR link descriptor that is being pointed to 1898*5113495bSYour Name shall be returned after the frame has been processed. It 1899*5113495bSYour Name is used by WBM for routing purposes. 1900*5113495bSYour Name 1901*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1902*5113495bSYour Name to the WMB buffer idle list 1903*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1904*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 1905*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 1906*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1907*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 1908*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1909*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 1910*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1911*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 1912*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 1913*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 1914*5113495bSYour Name ring 0 1915*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 1916*5113495bSYour Name ring 1 1917*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 1918*5113495bSYour Name ring 2 1919*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 1920*5113495bSYour Name ring 3 1921*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 1922*5113495bSYour Name ring 4 1923*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 1924*5113495bSYour Name ring 5 1925*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 1926*5113495bSYour Name ring 6 1927*5113495bSYour Name 1928*5113495bSYour Name <legal 0-12> 1929*5113495bSYour Name */ 1930*5113495bSYour Name 1931*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 1932*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1933*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1934*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1935*5113495bSYour Name 1936*5113495bSYour Name 1937*5113495bSYour Name /* Description SW_BUFFER_COOKIE 1938*5113495bSYour Name 1939*5113495bSYour Name Cookie field exclusively used by SW. 1940*5113495bSYour Name 1941*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 1942*5113495bSYour Name 1943*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 1944*5113495bSYour Name value on to other descriptors together with the physical 1945*5113495bSYour Name address 1946*5113495bSYour Name 1947*5113495bSYour Name Field can be used by SW to for example associate the buffers 1948*5113495bSYour Name physical address with the virtual address 1949*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 1950*5113495bSYour Name 1951*5113495bSYour Name 1952*5113495bSYour Name NOTE1: 1953*5113495bSYour Name The three most significant bits can have a special meaning 1954*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1955*5113495bSYour Name and field transmit_bw_restriction is set 1956*5113495bSYour Name 1957*5113495bSYour Name In case of NON punctured transmission: 1958*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1959*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1960*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1961*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1962*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1963*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1964*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1965*5113495bSYour Name 1966*5113495bSYour Name In case of punctured transmission: 1967*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1968*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1969*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1970*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1971*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1972*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1973*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1974*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1975*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1976*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1977*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1978*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1979*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 1980*5113495bSYour Name 1981*5113495bSYour Name Note: a punctured transmission is indicated by the presence 1982*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1983*5113495bSYour Name 1984*5113495bSYour Name <legal all> 1985*5113495bSYour Name */ 1986*5113495bSYour Name 1987*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 1988*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1989*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1990*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1991*5113495bSYour Name 1992*5113495bSYour Name 1993*5113495bSYour Name /* Description MPDU_LINK_POINTER_12 1994*5113495bSYour Name 1995*5113495bSYour Name Consumer: REO 1996*5113495bSYour Name Producer: REO 1997*5113495bSYour Name 1998*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 1999*5113495bSYour Name 2000*5113495bSYour Name */ 2001*5113495bSYour Name 2002*5113495bSYour Name 2003*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 2004*5113495bSYour Name 2005*5113495bSYour Name Details of the physical address of an MPDU link descriptor 2006*5113495bSYour Name 2007*5113495bSYour Name */ 2008*5113495bSYour Name 2009*5113495bSYour Name 2010*5113495bSYour Name /* Description BUFFER_ADDR_31_0 2011*5113495bSYour Name 2012*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2013*5113495bSYour Name descriptor OR Link Descriptor 2014*5113495bSYour Name 2015*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2016*5113495bSYour Name <legal all> 2017*5113495bSYour Name */ 2018*5113495bSYour Name 2019*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2020*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2021*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2022*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2023*5113495bSYour Name 2024*5113495bSYour Name 2025*5113495bSYour Name /* Description BUFFER_ADDR_39_32 2026*5113495bSYour Name 2027*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2028*5113495bSYour Name descriptor OR Link Descriptor 2029*5113495bSYour Name 2030*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2031*5113495bSYour Name <legal all> 2032*5113495bSYour Name */ 2033*5113495bSYour Name 2034*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2035*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2036*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2037*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2038*5113495bSYour Name 2039*5113495bSYour Name 2040*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 2041*5113495bSYour Name 2042*5113495bSYour Name Consumer: WBM 2043*5113495bSYour Name Producer: SW/FW 2044*5113495bSYour Name 2045*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2046*5113495bSYour Name 2047*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2048*5113495bSYour Name descriptor OR link descriptor that is being pointed to 2049*5113495bSYour Name shall be returned after the frame has been processed. It 2050*5113495bSYour Name is used by WBM for routing purposes. 2051*5113495bSYour Name 2052*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2053*5113495bSYour Name to the WMB buffer idle list 2054*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2055*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 2056*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 2057*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2058*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 2059*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2060*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 2061*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2062*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 2063*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 2064*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 2065*5113495bSYour Name ring 0 2066*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 2067*5113495bSYour Name ring 1 2068*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 2069*5113495bSYour Name ring 2 2070*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 2071*5113495bSYour Name ring 3 2072*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 2073*5113495bSYour Name ring 4 2074*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 2075*5113495bSYour Name ring 5 2076*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 2077*5113495bSYour Name ring 6 2078*5113495bSYour Name 2079*5113495bSYour Name <legal 0-12> 2080*5113495bSYour Name */ 2081*5113495bSYour Name 2082*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2083*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2084*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2085*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2086*5113495bSYour Name 2087*5113495bSYour Name 2088*5113495bSYour Name /* Description SW_BUFFER_COOKIE 2089*5113495bSYour Name 2090*5113495bSYour Name Cookie field exclusively used by SW. 2091*5113495bSYour Name 2092*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2093*5113495bSYour Name 2094*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 2095*5113495bSYour Name value on to other descriptors together with the physical 2096*5113495bSYour Name address 2097*5113495bSYour Name 2098*5113495bSYour Name Field can be used by SW to for example associate the buffers 2099*5113495bSYour Name physical address with the virtual address 2100*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 2101*5113495bSYour Name 2102*5113495bSYour Name 2103*5113495bSYour Name NOTE1: 2104*5113495bSYour Name The three most significant bits can have a special meaning 2105*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2106*5113495bSYour Name and field transmit_bw_restriction is set 2107*5113495bSYour Name 2108*5113495bSYour Name In case of NON punctured transmission: 2109*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2110*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2111*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2112*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2113*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2114*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2115*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2116*5113495bSYour Name 2117*5113495bSYour Name In case of punctured transmission: 2118*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2119*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2120*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2121*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2122*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2123*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2124*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2125*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2126*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2127*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2128*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2129*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2130*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2131*5113495bSYour Name 2132*5113495bSYour Name Note: a punctured transmission is indicated by the presence 2133*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2134*5113495bSYour Name 2135*5113495bSYour Name <legal all> 2136*5113495bSYour Name */ 2137*5113495bSYour Name 2138*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2139*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2140*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2141*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2142*5113495bSYour Name 2143*5113495bSYour Name 2144*5113495bSYour Name /* Description MPDU_LINK_POINTER_13 2145*5113495bSYour Name 2146*5113495bSYour Name Consumer: REO 2147*5113495bSYour Name Producer: REO 2148*5113495bSYour Name 2149*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 2150*5113495bSYour Name 2151*5113495bSYour Name */ 2152*5113495bSYour Name 2153*5113495bSYour Name 2154*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 2155*5113495bSYour Name 2156*5113495bSYour Name Details of the physical address of an MPDU link descriptor 2157*5113495bSYour Name 2158*5113495bSYour Name */ 2159*5113495bSYour Name 2160*5113495bSYour Name 2161*5113495bSYour Name /* Description BUFFER_ADDR_31_0 2162*5113495bSYour Name 2163*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2164*5113495bSYour Name descriptor OR Link Descriptor 2165*5113495bSYour Name 2166*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2167*5113495bSYour Name <legal all> 2168*5113495bSYour Name */ 2169*5113495bSYour Name 2170*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2171*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2172*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2173*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2174*5113495bSYour Name 2175*5113495bSYour Name 2176*5113495bSYour Name /* Description BUFFER_ADDR_39_32 2177*5113495bSYour Name 2178*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2179*5113495bSYour Name descriptor OR Link Descriptor 2180*5113495bSYour Name 2181*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2182*5113495bSYour Name <legal all> 2183*5113495bSYour Name */ 2184*5113495bSYour Name 2185*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2186*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2187*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2188*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2189*5113495bSYour Name 2190*5113495bSYour Name 2191*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 2192*5113495bSYour Name 2193*5113495bSYour Name Consumer: WBM 2194*5113495bSYour Name Producer: SW/FW 2195*5113495bSYour Name 2196*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2197*5113495bSYour Name 2198*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2199*5113495bSYour Name descriptor OR link descriptor that is being pointed to 2200*5113495bSYour Name shall be returned after the frame has been processed. It 2201*5113495bSYour Name is used by WBM for routing purposes. 2202*5113495bSYour Name 2203*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2204*5113495bSYour Name to the WMB buffer idle list 2205*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2206*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 2207*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 2208*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2209*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 2210*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2211*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 2212*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2213*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 2214*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 2215*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 2216*5113495bSYour Name ring 0 2217*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 2218*5113495bSYour Name ring 1 2219*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 2220*5113495bSYour Name ring 2 2221*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 2222*5113495bSYour Name ring 3 2223*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 2224*5113495bSYour Name ring 4 2225*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 2226*5113495bSYour Name ring 5 2227*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 2228*5113495bSYour Name ring 6 2229*5113495bSYour Name 2230*5113495bSYour Name <legal 0-12> 2231*5113495bSYour Name */ 2232*5113495bSYour Name 2233*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2234*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2235*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2236*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2237*5113495bSYour Name 2238*5113495bSYour Name 2239*5113495bSYour Name /* Description SW_BUFFER_COOKIE 2240*5113495bSYour Name 2241*5113495bSYour Name Cookie field exclusively used by SW. 2242*5113495bSYour Name 2243*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2244*5113495bSYour Name 2245*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 2246*5113495bSYour Name value on to other descriptors together with the physical 2247*5113495bSYour Name address 2248*5113495bSYour Name 2249*5113495bSYour Name Field can be used by SW to for example associate the buffers 2250*5113495bSYour Name physical address with the virtual address 2251*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 2252*5113495bSYour Name 2253*5113495bSYour Name 2254*5113495bSYour Name NOTE1: 2255*5113495bSYour Name The three most significant bits can have a special meaning 2256*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2257*5113495bSYour Name and field transmit_bw_restriction is set 2258*5113495bSYour Name 2259*5113495bSYour Name In case of NON punctured transmission: 2260*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2261*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2262*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2263*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2264*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2265*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2266*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2267*5113495bSYour Name 2268*5113495bSYour Name In case of punctured transmission: 2269*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2270*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2271*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2272*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2273*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2274*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2275*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2276*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2277*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2278*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2279*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2280*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2281*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2282*5113495bSYour Name 2283*5113495bSYour Name Note: a punctured transmission is indicated by the presence 2284*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2285*5113495bSYour Name 2286*5113495bSYour Name <legal all> 2287*5113495bSYour Name */ 2288*5113495bSYour Name 2289*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2290*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2291*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2292*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2293*5113495bSYour Name 2294*5113495bSYour Name 2295*5113495bSYour Name /* Description MPDU_LINK_POINTER_14 2296*5113495bSYour Name 2297*5113495bSYour Name Consumer: REO 2298*5113495bSYour Name Producer: REO 2299*5113495bSYour Name 2300*5113495bSYour Name Pointer to the next MPDU_link descriptor in the MPDU queue 2301*5113495bSYour Name 2302*5113495bSYour Name */ 2303*5113495bSYour Name 2304*5113495bSYour Name 2305*5113495bSYour Name /* Description MPDU_LINK_DESC_ADDR_INFO 2306*5113495bSYour Name 2307*5113495bSYour Name Details of the physical address of an MPDU link descriptor 2308*5113495bSYour Name 2309*5113495bSYour Name */ 2310*5113495bSYour Name 2311*5113495bSYour Name 2312*5113495bSYour Name /* Description BUFFER_ADDR_31_0 2313*5113495bSYour Name 2314*5113495bSYour Name Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2315*5113495bSYour Name descriptor OR Link Descriptor 2316*5113495bSYour Name 2317*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2318*5113495bSYour Name <legal all> 2319*5113495bSYour Name */ 2320*5113495bSYour Name 2321*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2322*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2323*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2324*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2325*5113495bSYour Name 2326*5113495bSYour Name 2327*5113495bSYour Name /* Description BUFFER_ADDR_39_32 2328*5113495bSYour Name 2329*5113495bSYour Name Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2330*5113495bSYour Name descriptor OR Link Descriptor 2331*5113495bSYour Name 2332*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2333*5113495bSYour Name <legal all> 2334*5113495bSYour Name */ 2335*5113495bSYour Name 2336*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2337*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2338*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2339*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2340*5113495bSYour Name 2341*5113495bSYour Name 2342*5113495bSYour Name /* Description RETURN_BUFFER_MANAGER 2343*5113495bSYour Name 2344*5113495bSYour Name Consumer: WBM 2345*5113495bSYour Name Producer: SW/FW 2346*5113495bSYour Name 2347*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2348*5113495bSYour Name 2349*5113495bSYour Name Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2350*5113495bSYour Name descriptor OR link descriptor that is being pointed to 2351*5113495bSYour Name shall be returned after the frame has been processed. It 2352*5113495bSYour Name is used by WBM for routing purposes. 2353*5113495bSYour Name 2354*5113495bSYour Name <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2355*5113495bSYour Name to the WMB buffer idle list 2356*5113495bSYour Name <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2357*5113495bSYour Name to the WBM idle link descriptor idle list, where the chip 2358*5113495bSYour Name 0 WBM is chosen in case of a multi-chip config 2359*5113495bSYour Name <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2360*5113495bSYour Name to the chip 1 WBM idle link descriptor idle list 2361*5113495bSYour Name <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2362*5113495bSYour Name to the chip 2 WBM idle link descriptor idle list 2363*5113495bSYour Name <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2364*5113495bSYour Name returned to chip 3 WBM idle link descriptor idle list 2365*5113495bSYour Name <enum 4 FW_BM> This buffer shall be returned to the FW 2366*5113495bSYour Name <enum 5 SW0_BM> This buffer shall be returned to the SW, 2367*5113495bSYour Name ring 0 2368*5113495bSYour Name <enum 6 SW1_BM> This buffer shall be returned to the SW, 2369*5113495bSYour Name ring 1 2370*5113495bSYour Name <enum 7 SW2_BM> This buffer shall be returned to the SW, 2371*5113495bSYour Name ring 2 2372*5113495bSYour Name <enum 8 SW3_BM> This buffer shall be returned to the SW, 2373*5113495bSYour Name ring 3 2374*5113495bSYour Name <enum 9 SW4_BM> This buffer shall be returned to the SW, 2375*5113495bSYour Name ring 4 2376*5113495bSYour Name <enum 10 SW5_BM> This buffer shall be returned to the SW, 2377*5113495bSYour Name ring 5 2378*5113495bSYour Name <enum 11 SW6_BM> This buffer shall be returned to the SW, 2379*5113495bSYour Name ring 6 2380*5113495bSYour Name 2381*5113495bSYour Name <legal 0-12> 2382*5113495bSYour Name */ 2383*5113495bSYour Name 2384*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2385*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2386*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2387*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2388*5113495bSYour Name 2389*5113495bSYour Name 2390*5113495bSYour Name /* Description SW_BUFFER_COOKIE 2391*5113495bSYour Name 2392*5113495bSYour Name Cookie field exclusively used by SW. 2393*5113495bSYour Name 2394*5113495bSYour Name In case of 'NULL' pointer, this field is set to 0 2395*5113495bSYour Name 2396*5113495bSYour Name HW ignores the contents, accept that it passes the programmed 2397*5113495bSYour Name value on to other descriptors together with the physical 2398*5113495bSYour Name address 2399*5113495bSYour Name 2400*5113495bSYour Name Field can be used by SW to for example associate the buffers 2401*5113495bSYour Name physical address with the virtual address 2402*5113495bSYour Name The bit definitions as used by SW are within SW HLD specification 2403*5113495bSYour Name 2404*5113495bSYour Name 2405*5113495bSYour Name NOTE1: 2406*5113495bSYour Name The three most significant bits can have a special meaning 2407*5113495bSYour Name in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2408*5113495bSYour Name and field transmit_bw_restriction is set 2409*5113495bSYour Name 2410*5113495bSYour Name In case of NON punctured transmission: 2411*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2412*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2413*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2414*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2415*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2416*5113495bSYour Name Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2417*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2418*5113495bSYour Name 2419*5113495bSYour Name In case of punctured transmission: 2420*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2421*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2422*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2423*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2424*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2425*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2426*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2427*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2428*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2429*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2430*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2431*5113495bSYour Name Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2432*5113495bSYour Name Sw_buffer_cookie[19:18] = 2'b11: reserved 2433*5113495bSYour Name 2434*5113495bSYour Name Note: a punctured transmission is indicated by the presence 2435*5113495bSYour Name of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2436*5113495bSYour Name 2437*5113495bSYour Name <legal all> 2438*5113495bSYour Name */ 2439*5113495bSYour Name 2440*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2441*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2442*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2443*5113495bSYour Name #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2444*5113495bSYour Name 2445*5113495bSYour Name 2446*5113495bSYour Name 2447*5113495bSYour Name #endif // RX_REO_QUEUE_EXT 2448