1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_EXT_H_ 18 #define _RX_REO_QUEUE_EXT_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "rx_mpdu_link_ptr.h" 23 #include "uniform_descriptor_header.h" 24 #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 25 26 27 struct rx_reo_queue_ext { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 struct uniform_descriptor_header descriptor_header; 30 uint32_t reserved_1a : 32; // [31:0] 31 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 32 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 33 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 34 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 35 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 36 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 37 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 38 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 39 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 40 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 41 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 42 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 43 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 44 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 45 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 46 #else 47 struct uniform_descriptor_header descriptor_header; 48 uint32_t reserved_1a : 32; // [31:0] 49 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 50 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 51 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 52 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 53 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 54 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 55 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 56 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 57 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 58 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 59 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 60 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 61 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 62 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 63 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 64 #endif 65 }; 66 67 68 /* Description DESCRIPTOR_HEADER 69 70 Details about which module owns this struct. 71 Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor" 72 73 */ 74 75 76 /* Description OWNER 77 78 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 79 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 80 81 The owner of this data structure: 82 <enum 0 WBM_owned> Buffer Manager currently owns this data 83 structure. 84 <enum 1 SW_OR_FW_owned> Software of FW currently owns this 85 data structure. 86 <enum 2 TQM_owned> Transmit Queue Manager currently owns 87 this data structure. 88 <enum 3 RXDMA_owned> Receive DMA currently owns this data 89 structure. 90 <enum 4 REO_owned> Reorder currently owns this data structure. 91 92 <enum 5 SWITCH_owned> SWITCH currently owns this data structure. 93 94 95 <legal 0-5> 96 */ 97 98 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 99 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 100 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 101 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 102 103 104 /* Description BUFFER_TYPE 105 106 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 107 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 108 109 Field describing what contents format is of this descriptor 110 111 112 <enum 0 Transmit_MSDU_Link_descriptor> 113 <enum 1 Transmit_MPDU_Link_descriptor> 114 <enum 2 Transmit_MPDU_Queue_head_descriptor> 115 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 116 <enum 4 Transmit_flow_descriptor> 117 <enum 5 Transmit_buffer> NOT TO BE USED: 118 119 <enum 6 Receive_MSDU_Link_descriptor> 120 <enum 7 Receive_MPDU_Link_descriptor> 121 <enum 8 Receive_REO_queue_descriptor> 122 <enum 9 Receive_REO_queue_1k_descriptor> 123 <enum 10 Receive_REO_queue_ext_descriptor> 124 125 <enum 11 Receive_buffer> 126 127 <enum 12 Idle_link_list_entry> 128 129 <legal 0-12> 130 */ 131 132 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 133 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 134 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 135 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 136 137 138 /* Description TX_MPDU_QUEUE_NUMBER 139 140 Consumer: TQM/Debug 141 Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) 142 143 Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor 144 145 146 Indicates the MPDU queue ID to which this MPDU descriptor 147 belongs 148 Used for tracking and debugging 149 150 <legal all> 151 */ 152 153 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 154 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 155 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 156 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 157 158 159 /* Description RESERVED_0A 160 161 <legal 0> 162 */ 163 164 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 165 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 166 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 167 #define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 168 169 170 /* Description RESERVED_1A 171 172 <legal 0> 173 */ 174 175 #define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 176 #define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 177 #define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 178 #define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff 179 180 181 /* Description MPDU_LINK_POINTER_0 182 183 Consumer: REO 184 Producer: REO 185 186 Pointer to the next MPDU_link descriptor in the MPDU queue 187 188 */ 189 190 191 /* Description MPDU_LINK_DESC_ADDR_INFO 192 193 Details of the physical address of an MPDU link descriptor 194 195 */ 196 197 198 /* Description BUFFER_ADDR_31_0 199 200 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 201 descriptor OR Link Descriptor 202 203 In case of 'NULL' pointer, this field is set to 0 204 <legal all> 205 */ 206 207 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 208 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 209 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 210 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 211 212 213 /* Description BUFFER_ADDR_39_32 214 215 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 216 descriptor OR Link Descriptor 217 218 In case of 'NULL' pointer, this field is set to 0 219 <legal all> 220 */ 221 222 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 223 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 224 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 225 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 226 227 228 /* Description RETURN_BUFFER_MANAGER 229 230 Consumer: WBM 231 Producer: SW/FW 232 233 In case of 'NULL' pointer, this field is set to 0 234 235 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 236 descriptor OR link descriptor that is being pointed to 237 shall be returned after the frame has been processed. It 238 is used by WBM for routing purposes. 239 240 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 241 to the WMB buffer idle list 242 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 243 to the WBM idle link descriptor idle list, where the chip 244 0 WBM is chosen in case of a multi-chip config 245 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 246 to the chip 1 WBM idle link descriptor idle list 247 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 248 to the chip 2 WBM idle link descriptor idle list 249 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 250 returned to chip 3 WBM idle link descriptor idle list 251 <enum 4 FW_BM> This buffer shall be returned to the FW 252 <enum 5 SW0_BM> This buffer shall be returned to the SW, 253 ring 0 254 <enum 6 SW1_BM> This buffer shall be returned to the SW, 255 ring 1 256 <enum 7 SW2_BM> This buffer shall be returned to the SW, 257 ring 2 258 <enum 8 SW3_BM> This buffer shall be returned to the SW, 259 ring 3 260 <enum 9 SW4_BM> This buffer shall be returned to the SW, 261 ring 4 262 <enum 10 SW5_BM> This buffer shall be returned to the SW, 263 ring 5 264 <enum 11 SW6_BM> This buffer shall be returned to the SW, 265 ring 6 266 267 <legal 0-12> 268 */ 269 270 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 271 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 272 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 273 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 274 275 276 /* Description SW_BUFFER_COOKIE 277 278 Cookie field exclusively used by SW. 279 280 In case of 'NULL' pointer, this field is set to 0 281 282 HW ignores the contents, accept that it passes the programmed 283 value on to other descriptors together with the physical 284 address 285 286 Field can be used by SW to for example associate the buffers 287 physical address with the virtual address 288 The bit definitions as used by SW are within SW HLD specification 289 290 291 NOTE1: 292 The three most significant bits can have a special meaning 293 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 294 and field transmit_bw_restriction is set 295 296 In case of NON punctured transmission: 297 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 298 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 299 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 300 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 301 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 302 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 303 Sw_buffer_cookie[19:18] = 2'b11: reserved 304 305 In case of punctured transmission: 306 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 307 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 308 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 309 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 310 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 311 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 312 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 313 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 314 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 315 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 316 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 317 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 318 Sw_buffer_cookie[19:18] = 2'b11: reserved 319 320 Note: a punctured transmission is indicated by the presence 321 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 322 323 <legal all> 324 */ 325 326 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 327 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 328 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 329 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 330 331 332 /* Description MPDU_LINK_POINTER_1 333 334 Consumer: REO 335 Producer: REO 336 337 Pointer to the next MPDU_link descriptor in the MPDU queue 338 339 */ 340 341 342 /* Description MPDU_LINK_DESC_ADDR_INFO 343 344 Details of the physical address of an MPDU link descriptor 345 346 */ 347 348 349 /* Description BUFFER_ADDR_31_0 350 351 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 352 descriptor OR Link Descriptor 353 354 In case of 'NULL' pointer, this field is set to 0 355 <legal all> 356 */ 357 358 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 359 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 360 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 361 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 362 363 364 /* Description BUFFER_ADDR_39_32 365 366 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 367 descriptor OR Link Descriptor 368 369 In case of 'NULL' pointer, this field is set to 0 370 <legal all> 371 */ 372 373 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 374 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 375 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 376 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 377 378 379 /* Description RETURN_BUFFER_MANAGER 380 381 Consumer: WBM 382 Producer: SW/FW 383 384 In case of 'NULL' pointer, this field is set to 0 385 386 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 387 descriptor OR link descriptor that is being pointed to 388 shall be returned after the frame has been processed. It 389 is used by WBM for routing purposes. 390 391 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 392 to the WMB buffer idle list 393 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 394 to the WBM idle link descriptor idle list, where the chip 395 0 WBM is chosen in case of a multi-chip config 396 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 397 to the chip 1 WBM idle link descriptor idle list 398 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 399 to the chip 2 WBM idle link descriptor idle list 400 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 401 returned to chip 3 WBM idle link descriptor idle list 402 <enum 4 FW_BM> This buffer shall be returned to the FW 403 <enum 5 SW0_BM> This buffer shall be returned to the SW, 404 ring 0 405 <enum 6 SW1_BM> This buffer shall be returned to the SW, 406 ring 1 407 <enum 7 SW2_BM> This buffer shall be returned to the SW, 408 ring 2 409 <enum 8 SW3_BM> This buffer shall be returned to the SW, 410 ring 3 411 <enum 9 SW4_BM> This buffer shall be returned to the SW, 412 ring 4 413 <enum 10 SW5_BM> This buffer shall be returned to the SW, 414 ring 5 415 <enum 11 SW6_BM> This buffer shall be returned to the SW, 416 ring 6 417 418 <legal 0-12> 419 */ 420 421 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 422 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 423 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 424 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 425 426 427 /* Description SW_BUFFER_COOKIE 428 429 Cookie field exclusively used by SW. 430 431 In case of 'NULL' pointer, this field is set to 0 432 433 HW ignores the contents, accept that it passes the programmed 434 value on to other descriptors together with the physical 435 address 436 437 Field can be used by SW to for example associate the buffers 438 physical address with the virtual address 439 The bit definitions as used by SW are within SW HLD specification 440 441 442 NOTE1: 443 The three most significant bits can have a special meaning 444 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 445 and field transmit_bw_restriction is set 446 447 In case of NON punctured transmission: 448 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 449 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 450 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 451 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 452 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 453 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 454 Sw_buffer_cookie[19:18] = 2'b11: reserved 455 456 In case of punctured transmission: 457 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 458 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 459 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 460 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 461 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 462 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 463 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 464 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 465 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 466 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 467 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 468 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 469 Sw_buffer_cookie[19:18] = 2'b11: reserved 470 471 Note: a punctured transmission is indicated by the presence 472 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 473 474 <legal all> 475 */ 476 477 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 478 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 479 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 480 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 481 482 483 /* Description MPDU_LINK_POINTER_2 484 485 Consumer: REO 486 Producer: REO 487 488 Pointer to the next MPDU_link descriptor in the MPDU queue 489 490 */ 491 492 493 /* Description MPDU_LINK_DESC_ADDR_INFO 494 495 Details of the physical address of an MPDU link descriptor 496 497 */ 498 499 500 /* Description BUFFER_ADDR_31_0 501 502 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 503 descriptor OR Link Descriptor 504 505 In case of 'NULL' pointer, this field is set to 0 506 <legal all> 507 */ 508 509 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 510 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 511 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 512 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 513 514 515 /* Description BUFFER_ADDR_39_32 516 517 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 518 descriptor OR Link Descriptor 519 520 In case of 'NULL' pointer, this field is set to 0 521 <legal all> 522 */ 523 524 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 525 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 526 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 527 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 528 529 530 /* Description RETURN_BUFFER_MANAGER 531 532 Consumer: WBM 533 Producer: SW/FW 534 535 In case of 'NULL' pointer, this field is set to 0 536 537 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 538 descriptor OR link descriptor that is being pointed to 539 shall be returned after the frame has been processed. It 540 is used by WBM for routing purposes. 541 542 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 543 to the WMB buffer idle list 544 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 545 to the WBM idle link descriptor idle list, where the chip 546 0 WBM is chosen in case of a multi-chip config 547 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 548 to the chip 1 WBM idle link descriptor idle list 549 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 550 to the chip 2 WBM idle link descriptor idle list 551 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 552 returned to chip 3 WBM idle link descriptor idle list 553 <enum 4 FW_BM> This buffer shall be returned to the FW 554 <enum 5 SW0_BM> This buffer shall be returned to the SW, 555 ring 0 556 <enum 6 SW1_BM> This buffer shall be returned to the SW, 557 ring 1 558 <enum 7 SW2_BM> This buffer shall be returned to the SW, 559 ring 2 560 <enum 8 SW3_BM> This buffer shall be returned to the SW, 561 ring 3 562 <enum 9 SW4_BM> This buffer shall be returned to the SW, 563 ring 4 564 <enum 10 SW5_BM> This buffer shall be returned to the SW, 565 ring 5 566 <enum 11 SW6_BM> This buffer shall be returned to the SW, 567 ring 6 568 569 <legal 0-12> 570 */ 571 572 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 573 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 574 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 575 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 576 577 578 /* Description SW_BUFFER_COOKIE 579 580 Cookie field exclusively used by SW. 581 582 In case of 'NULL' pointer, this field is set to 0 583 584 HW ignores the contents, accept that it passes the programmed 585 value on to other descriptors together with the physical 586 address 587 588 Field can be used by SW to for example associate the buffers 589 physical address with the virtual address 590 The bit definitions as used by SW are within SW HLD specification 591 592 593 NOTE1: 594 The three most significant bits can have a special meaning 595 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 596 and field transmit_bw_restriction is set 597 598 In case of NON punctured transmission: 599 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 600 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 601 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 602 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 603 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 604 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 605 Sw_buffer_cookie[19:18] = 2'b11: reserved 606 607 In case of punctured transmission: 608 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 609 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 610 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 611 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 612 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 613 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 614 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 615 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 616 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 617 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 618 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 619 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 620 Sw_buffer_cookie[19:18] = 2'b11: reserved 621 622 Note: a punctured transmission is indicated by the presence 623 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 624 625 <legal all> 626 */ 627 628 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 629 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 630 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 631 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 632 633 634 /* Description MPDU_LINK_POINTER_3 635 636 Consumer: REO 637 Producer: REO 638 639 Pointer to the next MPDU_link descriptor in the MPDU queue 640 641 */ 642 643 644 /* Description MPDU_LINK_DESC_ADDR_INFO 645 646 Details of the physical address of an MPDU link descriptor 647 648 */ 649 650 651 /* Description BUFFER_ADDR_31_0 652 653 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 654 descriptor OR Link Descriptor 655 656 In case of 'NULL' pointer, this field is set to 0 657 <legal all> 658 */ 659 660 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 661 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 662 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 663 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 664 665 666 /* Description BUFFER_ADDR_39_32 667 668 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 669 descriptor OR Link Descriptor 670 671 In case of 'NULL' pointer, this field is set to 0 672 <legal all> 673 */ 674 675 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 676 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 677 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 678 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 679 680 681 /* Description RETURN_BUFFER_MANAGER 682 683 Consumer: WBM 684 Producer: SW/FW 685 686 In case of 'NULL' pointer, this field is set to 0 687 688 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 689 descriptor OR link descriptor that is being pointed to 690 shall be returned after the frame has been processed. It 691 is used by WBM for routing purposes. 692 693 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 694 to the WMB buffer idle list 695 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 696 to the WBM idle link descriptor idle list, where the chip 697 0 WBM is chosen in case of a multi-chip config 698 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 699 to the chip 1 WBM idle link descriptor idle list 700 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 701 to the chip 2 WBM idle link descriptor idle list 702 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 703 returned to chip 3 WBM idle link descriptor idle list 704 <enum 4 FW_BM> This buffer shall be returned to the FW 705 <enum 5 SW0_BM> This buffer shall be returned to the SW, 706 ring 0 707 <enum 6 SW1_BM> This buffer shall be returned to the SW, 708 ring 1 709 <enum 7 SW2_BM> This buffer shall be returned to the SW, 710 ring 2 711 <enum 8 SW3_BM> This buffer shall be returned to the SW, 712 ring 3 713 <enum 9 SW4_BM> This buffer shall be returned to the SW, 714 ring 4 715 <enum 10 SW5_BM> This buffer shall be returned to the SW, 716 ring 5 717 <enum 11 SW6_BM> This buffer shall be returned to the SW, 718 ring 6 719 720 <legal 0-12> 721 */ 722 723 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 724 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 725 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 726 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 727 728 729 /* Description SW_BUFFER_COOKIE 730 731 Cookie field exclusively used by SW. 732 733 In case of 'NULL' pointer, this field is set to 0 734 735 HW ignores the contents, accept that it passes the programmed 736 value on to other descriptors together with the physical 737 address 738 739 Field can be used by SW to for example associate the buffers 740 physical address with the virtual address 741 The bit definitions as used by SW are within SW HLD specification 742 743 744 NOTE1: 745 The three most significant bits can have a special meaning 746 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 747 and field transmit_bw_restriction is set 748 749 In case of NON punctured transmission: 750 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 751 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 752 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 753 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 754 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 755 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 756 Sw_buffer_cookie[19:18] = 2'b11: reserved 757 758 In case of punctured transmission: 759 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 760 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 761 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 762 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 763 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 764 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 765 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 766 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 767 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 768 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 769 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 770 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 771 Sw_buffer_cookie[19:18] = 2'b11: reserved 772 773 Note: a punctured transmission is indicated by the presence 774 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 775 776 <legal all> 777 */ 778 779 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 780 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 781 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 782 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 783 784 785 /* Description MPDU_LINK_POINTER_4 786 787 Consumer: REO 788 Producer: REO 789 790 Pointer to the next MPDU_link descriptor in the MPDU queue 791 792 */ 793 794 795 /* Description MPDU_LINK_DESC_ADDR_INFO 796 797 Details of the physical address of an MPDU link descriptor 798 799 */ 800 801 802 /* Description BUFFER_ADDR_31_0 803 804 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 805 descriptor OR Link Descriptor 806 807 In case of 'NULL' pointer, this field is set to 0 808 <legal all> 809 */ 810 811 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 812 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 813 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 814 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 815 816 817 /* Description BUFFER_ADDR_39_32 818 819 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 820 descriptor OR Link Descriptor 821 822 In case of 'NULL' pointer, this field is set to 0 823 <legal all> 824 */ 825 826 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 827 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 828 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 829 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 830 831 832 /* Description RETURN_BUFFER_MANAGER 833 834 Consumer: WBM 835 Producer: SW/FW 836 837 In case of 'NULL' pointer, this field is set to 0 838 839 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 840 descriptor OR link descriptor that is being pointed to 841 shall be returned after the frame has been processed. It 842 is used by WBM for routing purposes. 843 844 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 845 to the WMB buffer idle list 846 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 847 to the WBM idle link descriptor idle list, where the chip 848 0 WBM is chosen in case of a multi-chip config 849 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 850 to the chip 1 WBM idle link descriptor idle list 851 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 852 to the chip 2 WBM idle link descriptor idle list 853 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 854 returned to chip 3 WBM idle link descriptor idle list 855 <enum 4 FW_BM> This buffer shall be returned to the FW 856 <enum 5 SW0_BM> This buffer shall be returned to the SW, 857 ring 0 858 <enum 6 SW1_BM> This buffer shall be returned to the SW, 859 ring 1 860 <enum 7 SW2_BM> This buffer shall be returned to the SW, 861 ring 2 862 <enum 8 SW3_BM> This buffer shall be returned to the SW, 863 ring 3 864 <enum 9 SW4_BM> This buffer shall be returned to the SW, 865 ring 4 866 <enum 10 SW5_BM> This buffer shall be returned to the SW, 867 ring 5 868 <enum 11 SW6_BM> This buffer shall be returned to the SW, 869 ring 6 870 871 <legal 0-12> 872 */ 873 874 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 875 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 876 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 877 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 878 879 880 /* Description SW_BUFFER_COOKIE 881 882 Cookie field exclusively used by SW. 883 884 In case of 'NULL' pointer, this field is set to 0 885 886 HW ignores the contents, accept that it passes the programmed 887 value on to other descriptors together with the physical 888 address 889 890 Field can be used by SW to for example associate the buffers 891 physical address with the virtual address 892 The bit definitions as used by SW are within SW HLD specification 893 894 895 NOTE1: 896 The three most significant bits can have a special meaning 897 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 898 and field transmit_bw_restriction is set 899 900 In case of NON punctured transmission: 901 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 902 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 903 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 904 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 905 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 906 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 907 Sw_buffer_cookie[19:18] = 2'b11: reserved 908 909 In case of punctured transmission: 910 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 911 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 912 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 913 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 914 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 915 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 916 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 917 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 918 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 919 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 920 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 921 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 922 Sw_buffer_cookie[19:18] = 2'b11: reserved 923 924 Note: a punctured transmission is indicated by the presence 925 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 926 927 <legal all> 928 */ 929 930 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 931 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 932 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 933 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 934 935 936 /* Description MPDU_LINK_POINTER_5 937 938 Consumer: REO 939 Producer: REO 940 941 Pointer to the next MPDU_link descriptor in the MPDU queue 942 943 */ 944 945 946 /* Description MPDU_LINK_DESC_ADDR_INFO 947 948 Details of the physical address of an MPDU link descriptor 949 950 */ 951 952 953 /* Description BUFFER_ADDR_31_0 954 955 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 956 descriptor OR Link Descriptor 957 958 In case of 'NULL' pointer, this field is set to 0 959 <legal all> 960 */ 961 962 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 963 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 964 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 965 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 966 967 968 /* Description BUFFER_ADDR_39_32 969 970 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 971 descriptor OR Link Descriptor 972 973 In case of 'NULL' pointer, this field is set to 0 974 <legal all> 975 */ 976 977 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 978 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 979 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 980 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 981 982 983 /* Description RETURN_BUFFER_MANAGER 984 985 Consumer: WBM 986 Producer: SW/FW 987 988 In case of 'NULL' pointer, this field is set to 0 989 990 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 991 descriptor OR link descriptor that is being pointed to 992 shall be returned after the frame has been processed. It 993 is used by WBM for routing purposes. 994 995 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 996 to the WMB buffer idle list 997 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 998 to the WBM idle link descriptor idle list, where the chip 999 0 WBM is chosen in case of a multi-chip config 1000 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1001 to the chip 1 WBM idle link descriptor idle list 1002 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1003 to the chip 2 WBM idle link descriptor idle list 1004 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1005 returned to chip 3 WBM idle link descriptor idle list 1006 <enum 4 FW_BM> This buffer shall be returned to the FW 1007 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1008 ring 0 1009 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1010 ring 1 1011 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1012 ring 2 1013 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1014 ring 3 1015 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1016 ring 4 1017 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1018 ring 5 1019 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1020 ring 6 1021 1022 <legal 0-12> 1023 */ 1024 1025 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1026 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1027 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1028 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1029 1030 1031 /* Description SW_BUFFER_COOKIE 1032 1033 Cookie field exclusively used by SW. 1034 1035 In case of 'NULL' pointer, this field is set to 0 1036 1037 HW ignores the contents, accept that it passes the programmed 1038 value on to other descriptors together with the physical 1039 address 1040 1041 Field can be used by SW to for example associate the buffers 1042 physical address with the virtual address 1043 The bit definitions as used by SW are within SW HLD specification 1044 1045 1046 NOTE1: 1047 The three most significant bits can have a special meaning 1048 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1049 and field transmit_bw_restriction is set 1050 1051 In case of NON punctured transmission: 1052 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1053 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1054 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1055 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1056 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1057 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1058 Sw_buffer_cookie[19:18] = 2'b11: reserved 1059 1060 In case of punctured transmission: 1061 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1062 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1063 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1064 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1065 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1066 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1067 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1068 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1069 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1070 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1071 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1072 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1073 Sw_buffer_cookie[19:18] = 2'b11: reserved 1074 1075 Note: a punctured transmission is indicated by the presence 1076 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1077 1078 <legal all> 1079 */ 1080 1081 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1082 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1083 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1084 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1085 1086 1087 /* Description MPDU_LINK_POINTER_6 1088 1089 Consumer: REO 1090 Producer: REO 1091 1092 Pointer to the next MPDU_link descriptor in the MPDU queue 1093 1094 */ 1095 1096 1097 /* Description MPDU_LINK_DESC_ADDR_INFO 1098 1099 Details of the physical address of an MPDU link descriptor 1100 1101 */ 1102 1103 1104 /* Description BUFFER_ADDR_31_0 1105 1106 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1107 descriptor OR Link Descriptor 1108 1109 In case of 'NULL' pointer, this field is set to 0 1110 <legal all> 1111 */ 1112 1113 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1114 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1115 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1116 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1117 1118 1119 /* Description BUFFER_ADDR_39_32 1120 1121 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1122 descriptor OR Link Descriptor 1123 1124 In case of 'NULL' pointer, this field is set to 0 1125 <legal all> 1126 */ 1127 1128 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1129 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1130 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1131 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1132 1133 1134 /* Description RETURN_BUFFER_MANAGER 1135 1136 Consumer: WBM 1137 Producer: SW/FW 1138 1139 In case of 'NULL' pointer, this field is set to 0 1140 1141 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1142 descriptor OR link descriptor that is being pointed to 1143 shall be returned after the frame has been processed. It 1144 is used by WBM for routing purposes. 1145 1146 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1147 to the WMB buffer idle list 1148 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1149 to the WBM idle link descriptor idle list, where the chip 1150 0 WBM is chosen in case of a multi-chip config 1151 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1152 to the chip 1 WBM idle link descriptor idle list 1153 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1154 to the chip 2 WBM idle link descriptor idle list 1155 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1156 returned to chip 3 WBM idle link descriptor idle list 1157 <enum 4 FW_BM> This buffer shall be returned to the FW 1158 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1159 ring 0 1160 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1161 ring 1 1162 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1163 ring 2 1164 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1165 ring 3 1166 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1167 ring 4 1168 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1169 ring 5 1170 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1171 ring 6 1172 1173 <legal 0-12> 1174 */ 1175 1176 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1177 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1178 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1179 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1180 1181 1182 /* Description SW_BUFFER_COOKIE 1183 1184 Cookie field exclusively used by SW. 1185 1186 In case of 'NULL' pointer, this field is set to 0 1187 1188 HW ignores the contents, accept that it passes the programmed 1189 value on to other descriptors together with the physical 1190 address 1191 1192 Field can be used by SW to for example associate the buffers 1193 physical address with the virtual address 1194 The bit definitions as used by SW are within SW HLD specification 1195 1196 1197 NOTE1: 1198 The three most significant bits can have a special meaning 1199 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1200 and field transmit_bw_restriction is set 1201 1202 In case of NON punctured transmission: 1203 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1204 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1205 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1206 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1207 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1208 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1209 Sw_buffer_cookie[19:18] = 2'b11: reserved 1210 1211 In case of punctured transmission: 1212 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1213 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1214 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1215 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1216 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1217 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1218 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1219 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1220 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1221 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1222 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1223 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1224 Sw_buffer_cookie[19:18] = 2'b11: reserved 1225 1226 Note: a punctured transmission is indicated by the presence 1227 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1228 1229 <legal all> 1230 */ 1231 1232 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1233 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1234 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1235 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1236 1237 1238 /* Description MPDU_LINK_POINTER_7 1239 1240 Consumer: REO 1241 Producer: REO 1242 1243 Pointer to the next MPDU_link descriptor in the MPDU queue 1244 1245 */ 1246 1247 1248 /* Description MPDU_LINK_DESC_ADDR_INFO 1249 1250 Details of the physical address of an MPDU link descriptor 1251 1252 */ 1253 1254 1255 /* Description BUFFER_ADDR_31_0 1256 1257 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1258 descriptor OR Link Descriptor 1259 1260 In case of 'NULL' pointer, this field is set to 0 1261 <legal all> 1262 */ 1263 1264 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1265 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1266 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1267 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1268 1269 1270 /* Description BUFFER_ADDR_39_32 1271 1272 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1273 descriptor OR Link Descriptor 1274 1275 In case of 'NULL' pointer, this field is set to 0 1276 <legal all> 1277 */ 1278 1279 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1280 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1281 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1282 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1283 1284 1285 /* Description RETURN_BUFFER_MANAGER 1286 1287 Consumer: WBM 1288 Producer: SW/FW 1289 1290 In case of 'NULL' pointer, this field is set to 0 1291 1292 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1293 descriptor OR link descriptor that is being pointed to 1294 shall be returned after the frame has been processed. It 1295 is used by WBM for routing purposes. 1296 1297 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1298 to the WMB buffer idle list 1299 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1300 to the WBM idle link descriptor idle list, where the chip 1301 0 WBM is chosen in case of a multi-chip config 1302 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1303 to the chip 1 WBM idle link descriptor idle list 1304 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1305 to the chip 2 WBM idle link descriptor idle list 1306 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1307 returned to chip 3 WBM idle link descriptor idle list 1308 <enum 4 FW_BM> This buffer shall be returned to the FW 1309 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1310 ring 0 1311 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1312 ring 1 1313 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1314 ring 2 1315 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1316 ring 3 1317 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1318 ring 4 1319 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1320 ring 5 1321 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1322 ring 6 1323 1324 <legal 0-12> 1325 */ 1326 1327 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1328 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1329 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1330 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1331 1332 1333 /* Description SW_BUFFER_COOKIE 1334 1335 Cookie field exclusively used by SW. 1336 1337 In case of 'NULL' pointer, this field is set to 0 1338 1339 HW ignores the contents, accept that it passes the programmed 1340 value on to other descriptors together with the physical 1341 address 1342 1343 Field can be used by SW to for example associate the buffers 1344 physical address with the virtual address 1345 The bit definitions as used by SW are within SW HLD specification 1346 1347 1348 NOTE1: 1349 The three most significant bits can have a special meaning 1350 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1351 and field transmit_bw_restriction is set 1352 1353 In case of NON punctured transmission: 1354 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1355 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1356 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1357 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1358 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1359 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1360 Sw_buffer_cookie[19:18] = 2'b11: reserved 1361 1362 In case of punctured transmission: 1363 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1364 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1365 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1366 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1367 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1368 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1369 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1370 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1371 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1372 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1373 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1374 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1375 Sw_buffer_cookie[19:18] = 2'b11: reserved 1376 1377 Note: a punctured transmission is indicated by the presence 1378 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1379 1380 <legal all> 1381 */ 1382 1383 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1384 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1385 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1386 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1387 1388 1389 /* Description MPDU_LINK_POINTER_8 1390 1391 Consumer: REO 1392 Producer: REO 1393 1394 Pointer to the next MPDU_link descriptor in the MPDU queue 1395 1396 */ 1397 1398 1399 /* Description MPDU_LINK_DESC_ADDR_INFO 1400 1401 Details of the physical address of an MPDU link descriptor 1402 1403 */ 1404 1405 1406 /* Description BUFFER_ADDR_31_0 1407 1408 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1409 descriptor OR Link Descriptor 1410 1411 In case of 'NULL' pointer, this field is set to 0 1412 <legal all> 1413 */ 1414 1415 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1416 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1417 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1418 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1419 1420 1421 /* Description BUFFER_ADDR_39_32 1422 1423 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1424 descriptor OR Link Descriptor 1425 1426 In case of 'NULL' pointer, this field is set to 0 1427 <legal all> 1428 */ 1429 1430 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1431 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1432 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1433 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1434 1435 1436 /* Description RETURN_BUFFER_MANAGER 1437 1438 Consumer: WBM 1439 Producer: SW/FW 1440 1441 In case of 'NULL' pointer, this field is set to 0 1442 1443 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1444 descriptor OR link descriptor that is being pointed to 1445 shall be returned after the frame has been processed. It 1446 is used by WBM for routing purposes. 1447 1448 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1449 to the WMB buffer idle list 1450 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1451 to the WBM idle link descriptor idle list, where the chip 1452 0 WBM is chosen in case of a multi-chip config 1453 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1454 to the chip 1 WBM idle link descriptor idle list 1455 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1456 to the chip 2 WBM idle link descriptor idle list 1457 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1458 returned to chip 3 WBM idle link descriptor idle list 1459 <enum 4 FW_BM> This buffer shall be returned to the FW 1460 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1461 ring 0 1462 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1463 ring 1 1464 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1465 ring 2 1466 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1467 ring 3 1468 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1469 ring 4 1470 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1471 ring 5 1472 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1473 ring 6 1474 1475 <legal 0-12> 1476 */ 1477 1478 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1479 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1480 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1481 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1482 1483 1484 /* Description SW_BUFFER_COOKIE 1485 1486 Cookie field exclusively used by SW. 1487 1488 In case of 'NULL' pointer, this field is set to 0 1489 1490 HW ignores the contents, accept that it passes the programmed 1491 value on to other descriptors together with the physical 1492 address 1493 1494 Field can be used by SW to for example associate the buffers 1495 physical address with the virtual address 1496 The bit definitions as used by SW are within SW HLD specification 1497 1498 1499 NOTE1: 1500 The three most significant bits can have a special meaning 1501 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1502 and field transmit_bw_restriction is set 1503 1504 In case of NON punctured transmission: 1505 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1506 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1507 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1508 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1509 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1510 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1511 Sw_buffer_cookie[19:18] = 2'b11: reserved 1512 1513 In case of punctured transmission: 1514 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1515 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1516 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1517 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1518 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1519 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1520 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1521 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1522 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1523 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1524 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1525 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1526 Sw_buffer_cookie[19:18] = 2'b11: reserved 1527 1528 Note: a punctured transmission is indicated by the presence 1529 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1530 1531 <legal all> 1532 */ 1533 1534 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1535 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1536 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1537 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1538 1539 1540 /* Description MPDU_LINK_POINTER_9 1541 1542 Consumer: REO 1543 Producer: REO 1544 1545 Pointer to the next MPDU_link descriptor in the MPDU queue 1546 1547 */ 1548 1549 1550 /* Description MPDU_LINK_DESC_ADDR_INFO 1551 1552 Details of the physical address of an MPDU link descriptor 1553 1554 */ 1555 1556 1557 /* Description BUFFER_ADDR_31_0 1558 1559 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1560 descriptor OR Link Descriptor 1561 1562 In case of 'NULL' pointer, this field is set to 0 1563 <legal all> 1564 */ 1565 1566 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1567 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1568 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1569 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1570 1571 1572 /* Description BUFFER_ADDR_39_32 1573 1574 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1575 descriptor OR Link Descriptor 1576 1577 In case of 'NULL' pointer, this field is set to 0 1578 <legal all> 1579 */ 1580 1581 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1582 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1583 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1584 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1585 1586 1587 /* Description RETURN_BUFFER_MANAGER 1588 1589 Consumer: WBM 1590 Producer: SW/FW 1591 1592 In case of 'NULL' pointer, this field is set to 0 1593 1594 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1595 descriptor OR link descriptor that is being pointed to 1596 shall be returned after the frame has been processed. It 1597 is used by WBM for routing purposes. 1598 1599 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1600 to the WMB buffer idle list 1601 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1602 to the WBM idle link descriptor idle list, where the chip 1603 0 WBM is chosen in case of a multi-chip config 1604 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1605 to the chip 1 WBM idle link descriptor idle list 1606 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1607 to the chip 2 WBM idle link descriptor idle list 1608 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1609 returned to chip 3 WBM idle link descriptor idle list 1610 <enum 4 FW_BM> This buffer shall be returned to the FW 1611 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1612 ring 0 1613 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1614 ring 1 1615 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1616 ring 2 1617 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1618 ring 3 1619 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1620 ring 4 1621 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1622 ring 5 1623 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1624 ring 6 1625 1626 <legal 0-12> 1627 */ 1628 1629 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1630 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1631 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1632 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1633 1634 1635 /* Description SW_BUFFER_COOKIE 1636 1637 Cookie field exclusively used by SW. 1638 1639 In case of 'NULL' pointer, this field is set to 0 1640 1641 HW ignores the contents, accept that it passes the programmed 1642 value on to other descriptors together with the physical 1643 address 1644 1645 Field can be used by SW to for example associate the buffers 1646 physical address with the virtual address 1647 The bit definitions as used by SW are within SW HLD specification 1648 1649 1650 NOTE1: 1651 The three most significant bits can have a special meaning 1652 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1653 and field transmit_bw_restriction is set 1654 1655 In case of NON punctured transmission: 1656 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1657 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1658 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1659 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1660 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1661 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1662 Sw_buffer_cookie[19:18] = 2'b11: reserved 1663 1664 In case of punctured transmission: 1665 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1666 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1667 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1668 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1669 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1670 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1671 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1672 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1673 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1674 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1675 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1676 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1677 Sw_buffer_cookie[19:18] = 2'b11: reserved 1678 1679 Note: a punctured transmission is indicated by the presence 1680 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1681 1682 <legal all> 1683 */ 1684 1685 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1686 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1687 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1688 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1689 1690 1691 /* Description MPDU_LINK_POINTER_10 1692 1693 Consumer: REO 1694 Producer: REO 1695 1696 Pointer to the next MPDU_link descriptor in the MPDU queue 1697 1698 */ 1699 1700 1701 /* Description MPDU_LINK_DESC_ADDR_INFO 1702 1703 Details of the physical address of an MPDU link descriptor 1704 1705 */ 1706 1707 1708 /* Description BUFFER_ADDR_31_0 1709 1710 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1711 descriptor OR Link Descriptor 1712 1713 In case of 'NULL' pointer, this field is set to 0 1714 <legal all> 1715 */ 1716 1717 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 1718 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1719 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1720 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1721 1722 1723 /* Description BUFFER_ADDR_39_32 1724 1725 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1726 descriptor OR Link Descriptor 1727 1728 In case of 'NULL' pointer, this field is set to 0 1729 <legal all> 1730 */ 1731 1732 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 1733 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1734 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1735 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1736 1737 1738 /* Description RETURN_BUFFER_MANAGER 1739 1740 Consumer: WBM 1741 Producer: SW/FW 1742 1743 In case of 'NULL' pointer, this field is set to 0 1744 1745 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1746 descriptor OR link descriptor that is being pointed to 1747 shall be returned after the frame has been processed. It 1748 is used by WBM for routing purposes. 1749 1750 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1751 to the WMB buffer idle list 1752 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1753 to the WBM idle link descriptor idle list, where the chip 1754 0 WBM is chosen in case of a multi-chip config 1755 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1756 to the chip 1 WBM idle link descriptor idle list 1757 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1758 to the chip 2 WBM idle link descriptor idle list 1759 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1760 returned to chip 3 WBM idle link descriptor idle list 1761 <enum 4 FW_BM> This buffer shall be returned to the FW 1762 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1763 ring 0 1764 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1765 ring 1 1766 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1767 ring 2 1768 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1769 ring 3 1770 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1771 ring 4 1772 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1773 ring 5 1774 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1775 ring 6 1776 1777 <legal 0-12> 1778 */ 1779 1780 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 1781 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1782 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1783 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1784 1785 1786 /* Description SW_BUFFER_COOKIE 1787 1788 Cookie field exclusively used by SW. 1789 1790 In case of 'NULL' pointer, this field is set to 0 1791 1792 HW ignores the contents, accept that it passes the programmed 1793 value on to other descriptors together with the physical 1794 address 1795 1796 Field can be used by SW to for example associate the buffers 1797 physical address with the virtual address 1798 The bit definitions as used by SW are within SW HLD specification 1799 1800 1801 NOTE1: 1802 The three most significant bits can have a special meaning 1803 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1804 and field transmit_bw_restriction is set 1805 1806 In case of NON punctured transmission: 1807 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1808 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1809 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1810 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1811 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1812 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1813 Sw_buffer_cookie[19:18] = 2'b11: reserved 1814 1815 In case of punctured transmission: 1816 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1817 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1818 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1819 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1820 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1821 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1822 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1823 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1824 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1825 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1826 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1827 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1828 Sw_buffer_cookie[19:18] = 2'b11: reserved 1829 1830 Note: a punctured transmission is indicated by the presence 1831 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1832 1833 <legal all> 1834 */ 1835 1836 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 1837 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1838 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1839 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1840 1841 1842 /* Description MPDU_LINK_POINTER_11 1843 1844 Consumer: REO 1845 Producer: REO 1846 1847 Pointer to the next MPDU_link descriptor in the MPDU queue 1848 1849 */ 1850 1851 1852 /* Description MPDU_LINK_DESC_ADDR_INFO 1853 1854 Details of the physical address of an MPDU link descriptor 1855 1856 */ 1857 1858 1859 /* Description BUFFER_ADDR_31_0 1860 1861 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 1862 descriptor OR Link Descriptor 1863 1864 In case of 'NULL' pointer, this field is set to 0 1865 <legal all> 1866 */ 1867 1868 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 1869 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1870 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 1871 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1872 1873 1874 /* Description BUFFER_ADDR_39_32 1875 1876 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 1877 descriptor OR Link Descriptor 1878 1879 In case of 'NULL' pointer, this field is set to 0 1880 <legal all> 1881 */ 1882 1883 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 1884 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1885 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 1886 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1887 1888 1889 /* Description RETURN_BUFFER_MANAGER 1890 1891 Consumer: WBM 1892 Producer: SW/FW 1893 1894 In case of 'NULL' pointer, this field is set to 0 1895 1896 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 1897 descriptor OR link descriptor that is being pointed to 1898 shall be returned after the frame has been processed. It 1899 is used by WBM for routing purposes. 1900 1901 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1902 to the WMB buffer idle list 1903 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 1904 to the WBM idle link descriptor idle list, where the chip 1905 0 WBM is chosen in case of a multi-chip config 1906 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 1907 to the chip 1 WBM idle link descriptor idle list 1908 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 1909 to the chip 2 WBM idle link descriptor idle list 1910 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 1911 returned to chip 3 WBM idle link descriptor idle list 1912 <enum 4 FW_BM> This buffer shall be returned to the FW 1913 <enum 5 SW0_BM> This buffer shall be returned to the SW, 1914 ring 0 1915 <enum 6 SW1_BM> This buffer shall be returned to the SW, 1916 ring 1 1917 <enum 7 SW2_BM> This buffer shall be returned to the SW, 1918 ring 2 1919 <enum 8 SW3_BM> This buffer shall be returned to the SW, 1920 ring 3 1921 <enum 9 SW4_BM> This buffer shall be returned to the SW, 1922 ring 4 1923 <enum 10 SW5_BM> This buffer shall be returned to the SW, 1924 ring 5 1925 <enum 11 SW6_BM> This buffer shall be returned to the SW, 1926 ring 6 1927 1928 <legal 0-12> 1929 */ 1930 1931 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 1932 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1933 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 1934 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 1935 1936 1937 /* Description SW_BUFFER_COOKIE 1938 1939 Cookie field exclusively used by SW. 1940 1941 In case of 'NULL' pointer, this field is set to 0 1942 1943 HW ignores the contents, accept that it passes the programmed 1944 value on to other descriptors together with the physical 1945 address 1946 1947 Field can be used by SW to for example associate the buffers 1948 physical address with the virtual address 1949 The bit definitions as used by SW are within SW HLD specification 1950 1951 1952 NOTE1: 1953 The three most significant bits can have a special meaning 1954 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 1955 and field transmit_bw_restriction is set 1956 1957 In case of NON punctured transmission: 1958 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 1959 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 1960 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 1961 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 1962 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 1963 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 1964 Sw_buffer_cookie[19:18] = 2'b11: reserved 1965 1966 In case of punctured transmission: 1967 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 1968 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 1969 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 1970 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 1971 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 1972 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 1973 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 1974 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 1975 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 1976 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 1977 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 1978 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 1979 Sw_buffer_cookie[19:18] = 2'b11: reserved 1980 1981 Note: a punctured transmission is indicated by the presence 1982 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 1983 1984 <legal all> 1985 */ 1986 1987 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 1988 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 1989 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 1990 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 1991 1992 1993 /* Description MPDU_LINK_POINTER_12 1994 1995 Consumer: REO 1996 Producer: REO 1997 1998 Pointer to the next MPDU_link descriptor in the MPDU queue 1999 2000 */ 2001 2002 2003 /* Description MPDU_LINK_DESC_ADDR_INFO 2004 2005 Details of the physical address of an MPDU link descriptor 2006 2007 */ 2008 2009 2010 /* Description BUFFER_ADDR_31_0 2011 2012 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2013 descriptor OR Link Descriptor 2014 2015 In case of 'NULL' pointer, this field is set to 0 2016 <legal all> 2017 */ 2018 2019 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2020 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2021 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2022 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2023 2024 2025 /* Description BUFFER_ADDR_39_32 2026 2027 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2028 descriptor OR Link Descriptor 2029 2030 In case of 'NULL' pointer, this field is set to 0 2031 <legal all> 2032 */ 2033 2034 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2035 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2036 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2037 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2038 2039 2040 /* Description RETURN_BUFFER_MANAGER 2041 2042 Consumer: WBM 2043 Producer: SW/FW 2044 2045 In case of 'NULL' pointer, this field is set to 0 2046 2047 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2048 descriptor OR link descriptor that is being pointed to 2049 shall be returned after the frame has been processed. It 2050 is used by WBM for routing purposes. 2051 2052 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2053 to the WMB buffer idle list 2054 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2055 to the WBM idle link descriptor idle list, where the chip 2056 0 WBM is chosen in case of a multi-chip config 2057 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2058 to the chip 1 WBM idle link descriptor idle list 2059 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2060 to the chip 2 WBM idle link descriptor idle list 2061 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2062 returned to chip 3 WBM idle link descriptor idle list 2063 <enum 4 FW_BM> This buffer shall be returned to the FW 2064 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2065 ring 0 2066 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2067 ring 1 2068 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2069 ring 2 2070 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2071 ring 3 2072 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2073 ring 4 2074 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2075 ring 5 2076 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2077 ring 6 2078 2079 <legal 0-12> 2080 */ 2081 2082 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2083 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2084 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2085 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2086 2087 2088 /* Description SW_BUFFER_COOKIE 2089 2090 Cookie field exclusively used by SW. 2091 2092 In case of 'NULL' pointer, this field is set to 0 2093 2094 HW ignores the contents, accept that it passes the programmed 2095 value on to other descriptors together with the physical 2096 address 2097 2098 Field can be used by SW to for example associate the buffers 2099 physical address with the virtual address 2100 The bit definitions as used by SW are within SW HLD specification 2101 2102 2103 NOTE1: 2104 The three most significant bits can have a special meaning 2105 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2106 and field transmit_bw_restriction is set 2107 2108 In case of NON punctured transmission: 2109 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2110 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2111 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2112 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2113 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2114 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2115 Sw_buffer_cookie[19:18] = 2'b11: reserved 2116 2117 In case of punctured transmission: 2118 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2119 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2120 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2121 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2122 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2123 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2124 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2125 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2126 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2127 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2128 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2129 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2130 Sw_buffer_cookie[19:18] = 2'b11: reserved 2131 2132 Note: a punctured transmission is indicated by the presence 2133 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2134 2135 <legal all> 2136 */ 2137 2138 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2139 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2140 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2141 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2142 2143 2144 /* Description MPDU_LINK_POINTER_13 2145 2146 Consumer: REO 2147 Producer: REO 2148 2149 Pointer to the next MPDU_link descriptor in the MPDU queue 2150 2151 */ 2152 2153 2154 /* Description MPDU_LINK_DESC_ADDR_INFO 2155 2156 Details of the physical address of an MPDU link descriptor 2157 2158 */ 2159 2160 2161 /* Description BUFFER_ADDR_31_0 2162 2163 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2164 descriptor OR Link Descriptor 2165 2166 In case of 'NULL' pointer, this field is set to 0 2167 <legal all> 2168 */ 2169 2170 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2171 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2172 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2173 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2174 2175 2176 /* Description BUFFER_ADDR_39_32 2177 2178 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2179 descriptor OR Link Descriptor 2180 2181 In case of 'NULL' pointer, this field is set to 0 2182 <legal all> 2183 */ 2184 2185 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2186 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2187 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2188 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2189 2190 2191 /* Description RETURN_BUFFER_MANAGER 2192 2193 Consumer: WBM 2194 Producer: SW/FW 2195 2196 In case of 'NULL' pointer, this field is set to 0 2197 2198 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2199 descriptor OR link descriptor that is being pointed to 2200 shall be returned after the frame has been processed. It 2201 is used by WBM for routing purposes. 2202 2203 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2204 to the WMB buffer idle list 2205 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2206 to the WBM idle link descriptor idle list, where the chip 2207 0 WBM is chosen in case of a multi-chip config 2208 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2209 to the chip 1 WBM idle link descriptor idle list 2210 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2211 to the chip 2 WBM idle link descriptor idle list 2212 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2213 returned to chip 3 WBM idle link descriptor idle list 2214 <enum 4 FW_BM> This buffer shall be returned to the FW 2215 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2216 ring 0 2217 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2218 ring 1 2219 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2220 ring 2 2221 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2222 ring 3 2223 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2224 ring 4 2225 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2226 ring 5 2227 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2228 ring 6 2229 2230 <legal 0-12> 2231 */ 2232 2233 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2234 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2235 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2236 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2237 2238 2239 /* Description SW_BUFFER_COOKIE 2240 2241 Cookie field exclusively used by SW. 2242 2243 In case of 'NULL' pointer, this field is set to 0 2244 2245 HW ignores the contents, accept that it passes the programmed 2246 value on to other descriptors together with the physical 2247 address 2248 2249 Field can be used by SW to for example associate the buffers 2250 physical address with the virtual address 2251 The bit definitions as used by SW are within SW HLD specification 2252 2253 2254 NOTE1: 2255 The three most significant bits can have a special meaning 2256 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2257 and field transmit_bw_restriction is set 2258 2259 In case of NON punctured transmission: 2260 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2261 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2262 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2263 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2264 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2265 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2266 Sw_buffer_cookie[19:18] = 2'b11: reserved 2267 2268 In case of punctured transmission: 2269 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2270 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2271 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2272 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2273 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2274 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2275 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2276 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2277 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2278 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2279 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2280 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2281 Sw_buffer_cookie[19:18] = 2'b11: reserved 2282 2283 Note: a punctured transmission is indicated by the presence 2284 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2285 2286 <legal all> 2287 */ 2288 2289 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2290 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2291 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2292 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2293 2294 2295 /* Description MPDU_LINK_POINTER_14 2296 2297 Consumer: REO 2298 Producer: REO 2299 2300 Pointer to the next MPDU_link descriptor in the MPDU queue 2301 2302 */ 2303 2304 2305 /* Description MPDU_LINK_DESC_ADDR_INFO 2306 2307 Details of the physical address of an MPDU link descriptor 2308 2309 */ 2310 2311 2312 /* Description BUFFER_ADDR_31_0 2313 2314 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 2315 descriptor OR Link Descriptor 2316 2317 In case of 'NULL' pointer, this field is set to 0 2318 <legal all> 2319 */ 2320 2321 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2322 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2323 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 2324 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2325 2326 2327 /* Description BUFFER_ADDR_39_32 2328 2329 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 2330 descriptor OR Link Descriptor 2331 2332 In case of 'NULL' pointer, this field is set to 0 2333 <legal all> 2334 */ 2335 2336 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2337 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2338 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 2339 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2340 2341 2342 /* Description RETURN_BUFFER_MANAGER 2343 2344 Consumer: WBM 2345 Producer: SW/FW 2346 2347 In case of 'NULL' pointer, this field is set to 0 2348 2349 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 2350 descriptor OR link descriptor that is being pointed to 2351 shall be returned after the frame has been processed. It 2352 is used by WBM for routing purposes. 2353 2354 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2355 to the WMB buffer idle list 2356 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 2357 to the WBM idle link descriptor idle list, where the chip 2358 0 WBM is chosen in case of a multi-chip config 2359 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 2360 to the chip 1 WBM idle link descriptor idle list 2361 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 2362 to the chip 2 WBM idle link descriptor idle list 2363 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 2364 returned to chip 3 WBM idle link descriptor idle list 2365 <enum 4 FW_BM> This buffer shall be returned to the FW 2366 <enum 5 SW0_BM> This buffer shall be returned to the SW, 2367 ring 0 2368 <enum 6 SW1_BM> This buffer shall be returned to the SW, 2369 ring 1 2370 <enum 7 SW2_BM> This buffer shall be returned to the SW, 2371 ring 2 2372 <enum 8 SW3_BM> This buffer shall be returned to the SW, 2373 ring 3 2374 <enum 9 SW4_BM> This buffer shall be returned to the SW, 2375 ring 4 2376 <enum 10 SW5_BM> This buffer shall be returned to the SW, 2377 ring 5 2378 <enum 11 SW6_BM> This buffer shall be returned to the SW, 2379 ring 6 2380 2381 <legal 0-12> 2382 */ 2383 2384 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2385 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2386 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 2387 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 2388 2389 2390 /* Description SW_BUFFER_COOKIE 2391 2392 Cookie field exclusively used by SW. 2393 2394 In case of 'NULL' pointer, this field is set to 0 2395 2396 HW ignores the contents, accept that it passes the programmed 2397 value on to other descriptors together with the physical 2398 address 2399 2400 Field can be used by SW to for example associate the buffers 2401 physical address with the virtual address 2402 The bit definitions as used by SW are within SW HLD specification 2403 2404 2405 NOTE1: 2406 The three most significant bits can have a special meaning 2407 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 2408 and field transmit_bw_restriction is set 2409 2410 In case of NON punctured transmission: 2411 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 2412 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 2413 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 2414 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 2415 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 2416 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 2417 Sw_buffer_cookie[19:18] = 2'b11: reserved 2418 2419 In case of punctured transmission: 2420 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 2421 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 2422 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 2423 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 2424 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 2425 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 2426 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 2427 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 2428 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 2429 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 2430 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 2431 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 2432 Sw_buffer_cookie[19:18] = 2'b11: reserved 2433 2434 Note: a punctured transmission is indicated by the presence 2435 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 2436 2437 <legal all> 2438 */ 2439 2440 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2441 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 2442 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 2443 #define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 2444 2445 2446 2447 #endif // RX_REO_QUEUE_EXT 2448