1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _RX_REO_QUEUE_REFERENCE_H_ 18*5113495bSYour Name #define _RX_REO_QUEUE_REFERENCE_H_ 19*5113495bSYour Name #if !defined(__ASSEMBLER__) 20*5113495bSYour Name #endif 21*5113495bSYour Name 22*5113495bSYour Name #define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name struct rx_reo_queue_reference { 26*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27*5113495bSYour Name uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 28*5113495bSYour Name uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 29*5113495bSYour Name reserved_1 : 8, // [15:8] 30*5113495bSYour Name receive_queue_number : 16; // [31:16] 31*5113495bSYour Name #else 32*5113495bSYour Name uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 33*5113495bSYour Name uint32_t receive_queue_number : 16, // [31:16] 34*5113495bSYour Name reserved_1 : 8, // [15:8] 35*5113495bSYour Name rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 36*5113495bSYour Name #endif 37*5113495bSYour Name }; 38*5113495bSYour Name 39*5113495bSYour Name 40*5113495bSYour Name /* Description RX_REO_QUEUE_DESC_ADDR_31_0 41*5113495bSYour Name 42*5113495bSYour Name Consumer: RXDMA 43*5113495bSYour Name Producer: RXOLE 44*5113495bSYour Name 45*5113495bSYour Name Address (lower 32 bits) of the REO queue descriptor. 46*5113495bSYour Name <legal all> 47*5113495bSYour Name */ 48*5113495bSYour Name 49*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 50*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 51*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 52*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 53*5113495bSYour Name 54*5113495bSYour Name 55*5113495bSYour Name /* Description RX_REO_QUEUE_DESC_ADDR_39_32 56*5113495bSYour Name 57*5113495bSYour Name Consumer: RXDMA 58*5113495bSYour Name Producer: RXOLE 59*5113495bSYour Name 60*5113495bSYour Name Address (upper 8 bits) of the REO queue descriptor. 61*5113495bSYour Name <legal all> 62*5113495bSYour Name */ 63*5113495bSYour Name 64*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 65*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 66*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 67*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 68*5113495bSYour Name 69*5113495bSYour Name 70*5113495bSYour Name /* Description RESERVED_1 71*5113495bSYour Name 72*5113495bSYour Name <legal 0> 73*5113495bSYour Name */ 74*5113495bSYour Name 75*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 76*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 77*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 78*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 79*5113495bSYour Name 80*5113495bSYour Name 81*5113495bSYour Name /* Description RECEIVE_QUEUE_NUMBER 82*5113495bSYour Name 83*5113495bSYour Name Indicates the MPDU queue ID to which this MPDU link descriptor 84*5113495bSYour Name belongs 85*5113495bSYour Name Used for tracking and debugging 86*5113495bSYour Name <legal all> 87*5113495bSYour Name */ 88*5113495bSYour Name 89*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 90*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 91*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 92*5113495bSYour Name #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 93*5113495bSYour Name 94*5113495bSYour Name 95*5113495bSYour Name 96*5113495bSYour Name #endif // RX_REO_QUEUE_REFERENCE 97