1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_REFERENCE_H_ 18 #define _RX_REO_QUEUE_REFERENCE_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 23 24 25 struct rx_reo_queue_reference { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 28 uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] 29 reserved_1 : 8, // [15:8] 30 receive_queue_number : 16; // [31:16] 31 #else 32 uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] 33 uint32_t receive_queue_number : 16, // [31:16] 34 reserved_1 : 8, // [15:8] 35 rx_reo_queue_desc_addr_39_32 : 8; // [7:0] 36 #endif 37 }; 38 39 40 /* Description RX_REO_QUEUE_DESC_ADDR_31_0 41 42 Consumer: RXDMA 43 Producer: RXOLE 44 45 Address (lower 32 bits) of the REO queue descriptor. 46 <legal all> 47 */ 48 49 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 50 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 51 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 52 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 53 54 55 /* Description RX_REO_QUEUE_DESC_ADDR_39_32 56 57 Consumer: RXDMA 58 Producer: RXOLE 59 60 Address (upper 8 bits) of the REO queue descriptor. 61 <legal all> 62 */ 63 64 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 65 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 66 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 67 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 68 69 70 /* Description RESERVED_1 71 72 <legal 0> 73 */ 74 75 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 76 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 77 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 78 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 79 80 81 /* Description RECEIVE_QUEUE_NUMBER 82 83 Indicates the MPDU queue ID to which this MPDU link descriptor 84 belongs 85 Used for tracking and debugging 86 <legal all> 87 */ 88 89 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 90 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 91 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 92 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 93 94 95 96 #endif // RX_REO_QUEUE_REFERENCE 97