1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _RXPCU_PPDU_END_INFO_H_ 18*5113495bSYour Name #define _RXPCU_PPDU_END_INFO_H_ 19*5113495bSYour Name #if !defined(__ASSEMBLER__) 20*5113495bSYour Name #endif 21*5113495bSYour Name 22*5113495bSYour Name #include "phyrx_abort_request_info.h" 23*5113495bSYour Name #include "macrx_abort_request_info.h" 24*5113495bSYour Name #include "rxpcu_ppdu_end_layout_info.h" 25*5113495bSYour Name #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 26*5113495bSYour Name 27*5113495bSYour Name #define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 28*5113495bSYour Name 29*5113495bSYour Name 30*5113495bSYour Name struct rxpcu_ppdu_end_info { 31*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32*5113495bSYour Name uint32_t wb_timestamp_lower_32 : 32; // [31:0] 33*5113495bSYour Name uint32_t wb_timestamp_upper_32 : 32; // [31:0] 34*5113495bSYour Name uint32_t rx_antenna : 24, // [23:0] 35*5113495bSYour Name tx_ht_vht_ack : 1, // [24:24] 36*5113495bSYour Name unsupported_mu_nc : 1, // [25:25] 37*5113495bSYour Name otp_txbf_disable : 1, // [26:26] 38*5113495bSYour Name previous_tlv_corrupted : 1, // [27:27] 39*5113495bSYour Name phyrx_abort_request_info_valid : 1, // [28:28] 40*5113495bSYour Name macrx_abort_request_info_valid : 1, // [29:29] 41*5113495bSYour Name reserved : 2; // [31:30] 42*5113495bSYour Name uint32_t coex_bt_tx_from_start_of_rx : 1, // [0:0] 43*5113495bSYour Name coex_bt_tx_after_start_of_rx : 1, // [1:1] 44*5113495bSYour Name coex_wan_tx_from_start_of_rx : 1, // [2:2] 45*5113495bSYour Name coex_wan_tx_after_start_of_rx : 1, // [3:3] 46*5113495bSYour Name coex_wlan_tx_from_start_of_rx : 1, // [4:4] 47*5113495bSYour Name coex_wlan_tx_after_start_of_rx : 1, // [5:5] 48*5113495bSYour Name mpdu_delimiter_errors_seen : 1, // [6:6] 49*5113495bSYour Name ftm_tm : 2, // [8:7] 50*5113495bSYour Name dialog_token : 8, // [16:9] 51*5113495bSYour Name follow_up_dialog_token : 8, // [24:17] 52*5113495bSYour Name bb_captured_channel : 1, // [25:25] 53*5113495bSYour Name bb_captured_reason : 3, // [28:26] 54*5113495bSYour Name bb_captured_timeout : 1, // [29:29] 55*5113495bSYour Name reserved_3 : 2; // [31:30] 56*5113495bSYour Name uint32_t before_mpdu_count_passing_fcs : 10, // [9:0] 57*5113495bSYour Name before_mpdu_count_failing_fcs : 10, // [19:10] 58*5113495bSYour Name after_mpdu_count_passing_fcs : 10, // [29:20] 59*5113495bSYour Name reserved_4 : 2; // [31:30] 60*5113495bSYour Name uint32_t after_mpdu_count_failing_fcs : 10, // [9:0] 61*5113495bSYour Name reserved_5 : 22; // [31:10] 62*5113495bSYour Name uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] 63*5113495bSYour Name uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] 64*5113495bSYour Name uint32_t bb_length : 16, // [15:0] 65*5113495bSYour Name bb_data : 1, // [16:16] 66*5113495bSYour Name reserved_8 : 3, // [19:17] 67*5113495bSYour Name first_bt_broadcast_status_details : 12; // [31:20] 68*5113495bSYour Name uint32_t rx_ppdu_duration : 24, // [23:0] 69*5113495bSYour Name reserved_9 : 8; // [31:24] 70*5113495bSYour Name uint32_t ast_index : 16, // [15:0] 71*5113495bSYour Name ast_index_valid : 1, // [16:16] 72*5113495bSYour Name reserved_10 : 3, // [19:17] 73*5113495bSYour Name second_bt_broadcast_status_details : 12; // [31:20] 74*5113495bSYour Name struct phyrx_abort_request_info phyrx_abort_request_info_details; 75*5113495bSYour Name struct macrx_abort_request_info macrx_abort_request_info_details; 76*5113495bSYour Name uint16_t pre_bt_broadcast_status_details : 12, // [27:16] 77*5113495bSYour Name reserved_12a : 4; // [31:28] 78*5113495bSYour Name uint32_t non_qos_sn_info_valid : 1, // [0:0] 79*5113495bSYour Name reserved_13a : 5, // [5:1] 80*5113495bSYour Name non_qos_sn_highest : 12, // [17:6] 81*5113495bSYour Name non_qos_sn_highest_retry_setting : 1, // [18:18] 82*5113495bSYour Name non_qos_sn_lowest : 12, // [30:19] 83*5113495bSYour Name non_qos_sn_lowest_retry_setting : 1; // [31:31] 84*5113495bSYour Name uint32_t qos_sn_1_info_valid : 1, // [0:0] 85*5113495bSYour Name reserved_14a : 1, // [1:1] 86*5113495bSYour Name qos_sn_1_tid : 4, // [5:2] 87*5113495bSYour Name qos_sn_1_highest : 12, // [17:6] 88*5113495bSYour Name qos_sn_1_highest_retry_setting : 1, // [18:18] 89*5113495bSYour Name qos_sn_1_lowest : 12, // [30:19] 90*5113495bSYour Name qos_sn_1_lowest_retry_setting : 1; // [31:31] 91*5113495bSYour Name uint32_t qos_sn_2_info_valid : 1, // [0:0] 92*5113495bSYour Name reserved_15a : 1, // [1:1] 93*5113495bSYour Name qos_sn_2_tid : 4, // [5:2] 94*5113495bSYour Name qos_sn_2_highest : 12, // [17:6] 95*5113495bSYour Name qos_sn_2_highest_retry_setting : 1, // [18:18] 96*5113495bSYour Name qos_sn_2_lowest : 12, // [30:19] 97*5113495bSYour Name qos_sn_2_lowest_retry_setting : 1; // [31:31] 98*5113495bSYour Name struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 99*5113495bSYour Name uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 100*5113495bSYour Name qos_sn_1_more_frag_state : 1, // [1:1] 101*5113495bSYour Name qos_sn_1_frag_num_state : 4, // [5:2] 102*5113495bSYour Name qos_sn_2_more_frag_state : 1, // [6:6] 103*5113495bSYour Name qos_sn_2_frag_num_state : 4, // [10:7] 104*5113495bSYour Name reserved_26a : 21; // [31:11] 105*5113495bSYour Name uint32_t rx_ppdu_end_marker : 32; // [31:0] 106*5113495bSYour Name #else 107*5113495bSYour Name uint32_t wb_timestamp_lower_32 : 32; // [31:0] 108*5113495bSYour Name uint32_t wb_timestamp_upper_32 : 32; // [31:0] 109*5113495bSYour Name uint32_t reserved : 2, // [31:30] 110*5113495bSYour Name macrx_abort_request_info_valid : 1, // [29:29] 111*5113495bSYour Name phyrx_abort_request_info_valid : 1, // [28:28] 112*5113495bSYour Name previous_tlv_corrupted : 1, // [27:27] 113*5113495bSYour Name otp_txbf_disable : 1, // [26:26] 114*5113495bSYour Name unsupported_mu_nc : 1, // [25:25] 115*5113495bSYour Name tx_ht_vht_ack : 1, // [24:24] 116*5113495bSYour Name rx_antenna : 24; // [23:0] 117*5113495bSYour Name uint32_t reserved_3 : 2, // [31:30] 118*5113495bSYour Name bb_captured_timeout : 1, // [29:29] 119*5113495bSYour Name bb_captured_reason : 3, // [28:26] 120*5113495bSYour Name bb_captured_channel : 1, // [25:25] 121*5113495bSYour Name follow_up_dialog_token : 8, // [24:17] 122*5113495bSYour Name dialog_token : 8, // [16:9] 123*5113495bSYour Name ftm_tm : 2, // [8:7] 124*5113495bSYour Name mpdu_delimiter_errors_seen : 1, // [6:6] 125*5113495bSYour Name coex_wlan_tx_after_start_of_rx : 1, // [5:5] 126*5113495bSYour Name coex_wlan_tx_from_start_of_rx : 1, // [4:4] 127*5113495bSYour Name coex_wan_tx_after_start_of_rx : 1, // [3:3] 128*5113495bSYour Name coex_wan_tx_from_start_of_rx : 1, // [2:2] 129*5113495bSYour Name coex_bt_tx_after_start_of_rx : 1, // [1:1] 130*5113495bSYour Name coex_bt_tx_from_start_of_rx : 1; // [0:0] 131*5113495bSYour Name uint32_t reserved_4 : 2, // [31:30] 132*5113495bSYour Name after_mpdu_count_passing_fcs : 10, // [29:20] 133*5113495bSYour Name before_mpdu_count_failing_fcs : 10, // [19:10] 134*5113495bSYour Name before_mpdu_count_passing_fcs : 10; // [9:0] 135*5113495bSYour Name uint32_t reserved_5 : 22, // [31:10] 136*5113495bSYour Name after_mpdu_count_failing_fcs : 10; // [9:0] 137*5113495bSYour Name uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] 138*5113495bSYour Name uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] 139*5113495bSYour Name uint32_t first_bt_broadcast_status_details : 12, // [31:20] 140*5113495bSYour Name reserved_8 : 3, // [19:17] 141*5113495bSYour Name bb_data : 1, // [16:16] 142*5113495bSYour Name bb_length : 16; // [15:0] 143*5113495bSYour Name uint32_t reserved_9 : 8, // [31:24] 144*5113495bSYour Name rx_ppdu_duration : 24; // [23:0] 145*5113495bSYour Name uint32_t second_bt_broadcast_status_details : 12, // [31:20] 146*5113495bSYour Name reserved_10 : 3, // [19:17] 147*5113495bSYour Name ast_index_valid : 1, // [16:16] 148*5113495bSYour Name ast_index : 16; // [15:0] 149*5113495bSYour Name struct phyrx_abort_request_info phyrx_abort_request_info_details; 150*5113495bSYour Name uint32_t reserved_12a : 4, // [31:28] 151*5113495bSYour Name pre_bt_broadcast_status_details : 12; // [27:16] 152*5113495bSYour Name struct macrx_abort_request_info macrx_abort_request_info_details; 153*5113495bSYour Name uint32_t non_qos_sn_lowest_retry_setting : 1, // [31:31] 154*5113495bSYour Name non_qos_sn_lowest : 12, // [30:19] 155*5113495bSYour Name non_qos_sn_highest_retry_setting : 1, // [18:18] 156*5113495bSYour Name non_qos_sn_highest : 12, // [17:6] 157*5113495bSYour Name reserved_13a : 5, // [5:1] 158*5113495bSYour Name non_qos_sn_info_valid : 1; // [0:0] 159*5113495bSYour Name uint32_t qos_sn_1_lowest_retry_setting : 1, // [31:31] 160*5113495bSYour Name qos_sn_1_lowest : 12, // [30:19] 161*5113495bSYour Name qos_sn_1_highest_retry_setting : 1, // [18:18] 162*5113495bSYour Name qos_sn_1_highest : 12, // [17:6] 163*5113495bSYour Name qos_sn_1_tid : 4, // [5:2] 164*5113495bSYour Name reserved_14a : 1, // [1:1] 165*5113495bSYour Name qos_sn_1_info_valid : 1; // [0:0] 166*5113495bSYour Name uint32_t qos_sn_2_lowest_retry_setting : 1, // [31:31] 167*5113495bSYour Name qos_sn_2_lowest : 12, // [30:19] 168*5113495bSYour Name qos_sn_2_highest_retry_setting : 1, // [18:18] 169*5113495bSYour Name qos_sn_2_highest : 12, // [17:6] 170*5113495bSYour Name qos_sn_2_tid : 4, // [5:2] 171*5113495bSYour Name reserved_15a : 1, // [1:1] 172*5113495bSYour Name qos_sn_2_info_valid : 1; // [0:0] 173*5113495bSYour Name struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 174*5113495bSYour Name uint32_t reserved_26a : 21, // [31:11] 175*5113495bSYour Name qos_sn_2_frag_num_state : 4, // [10:7] 176*5113495bSYour Name qos_sn_2_more_frag_state : 1, // [6:6] 177*5113495bSYour Name qos_sn_1_frag_num_state : 4, // [5:2] 178*5113495bSYour Name qos_sn_1_more_frag_state : 1, // [1:1] 179*5113495bSYour Name corrupted_due_to_fifo_delay : 1; // [0:0] 180*5113495bSYour Name uint32_t rx_ppdu_end_marker : 32; // [31:0] 181*5113495bSYour Name #endif 182*5113495bSYour Name }; 183*5113495bSYour Name 184*5113495bSYour Name 185*5113495bSYour Name /* Description WB_TIMESTAMP_LOWER_32 186*5113495bSYour Name 187*5113495bSYour Name WLAN/BT timestamp is a 1 usec resolution timestamp which 188*5113495bSYour Name does not get updated based on receive beacon like TSF. 189*5113495bSYour Name The same rules for capturing tsf_timestamp are used to 190*5113495bSYour Name capture the wb_timestamp. This field represents the lower 191*5113495bSYour Name 32 bits of the 64-bit timestamp 192*5113495bSYour Name */ 193*5113495bSYour Name 194*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 195*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 196*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 197*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff 198*5113495bSYour Name 199*5113495bSYour Name 200*5113495bSYour Name /* Description WB_TIMESTAMP_UPPER_32 201*5113495bSYour Name 202*5113495bSYour Name WLAN/BT timestamp is a 1 usec resolution timestamp which 203*5113495bSYour Name does not get updated based on receive beacon like TSF. 204*5113495bSYour Name The same rules for capturing tsf_timestamp are used to 205*5113495bSYour Name capture the wb_timestamp. This field represents the upper 206*5113495bSYour Name 32 bits of the 64-bit timestamp 207*5113495bSYour Name */ 208*5113495bSYour Name 209*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 210*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 211*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 212*5113495bSYour Name #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 213*5113495bSYour Name 214*5113495bSYour Name 215*5113495bSYour Name /* Description RX_ANTENNA 216*5113495bSYour Name 217*5113495bSYour Name Receive antenna value ??? 218*5113495bSYour Name */ 219*5113495bSYour Name 220*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 221*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 222*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 223*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff 224*5113495bSYour Name 225*5113495bSYour Name 226*5113495bSYour Name /* Description TX_HT_VHT_ACK 227*5113495bSYour Name 228*5113495bSYour Name Indicates that a HT or VHT Ack/BA frame was transmitted 229*5113495bSYour Name in response to this receive packet. 230*5113495bSYour Name */ 231*5113495bSYour Name 232*5113495bSYour Name #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 233*5113495bSYour Name #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 234*5113495bSYour Name #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 235*5113495bSYour Name #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 236*5113495bSYour Name 237*5113495bSYour Name 238*5113495bSYour Name 239*5113495bSYour Name #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 240*5113495bSYour Name #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 241*5113495bSYour Name #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 242*5113495bSYour Name #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 243*5113495bSYour Name 244*5113495bSYour Name 245*5113495bSYour Name /* Description OTP_TXBF_DISABLE 246*5113495bSYour Name 247*5113495bSYour Name Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 248*5113495bSYour Name set and if RXPU receives directed NDPA frame. Then, RXPCU 249*5113495bSYour Name should not send TX_EXPECT_NDP TLV to SW but set this bit 250*5113495bSYour Name to inform SW. 251*5113495bSYour Name */ 252*5113495bSYour Name 253*5113495bSYour Name #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 254*5113495bSYour Name #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 255*5113495bSYour Name #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 256*5113495bSYour Name #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 257*5113495bSYour Name 258*5113495bSYour Name 259*5113495bSYour Name /* Description PREVIOUS_TLV_CORRUPTED 260*5113495bSYour Name 261*5113495bSYour Name When set, the TLV preceding this RXPCU_END_INFO TLV within 262*5113495bSYour Name the RX_PPDU_END TLV, is corrupted. Not the entire TLV was 263*5113495bSYour Name received.... Likely due to an abort scenario... If abort 264*5113495bSYour Name is to blame, see the abort data datastructure for details. 265*5113495bSYour Name 266*5113495bSYour Name <legal all> 267*5113495bSYour Name */ 268*5113495bSYour Name 269*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 270*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 271*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 272*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 273*5113495bSYour Name 274*5113495bSYour Name 275*5113495bSYour Name /* Description PHYRX_ABORT_REQUEST_INFO_VALID 276*5113495bSYour Name 277*5113495bSYour Name When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to RXPCU. 278*5113495bSYour Name The abort fields embedded in this TLV contain valid info. 279*5113495bSYour Name 280*5113495bSYour Name <legal all> 281*5113495bSYour Name */ 282*5113495bSYour Name 283*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 284*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 285*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 286*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 287*5113495bSYour Name 288*5113495bSYour Name 289*5113495bSYour Name /* Description MACRX_ABORT_REQUEST_INFO_VALID 290*5113495bSYour Name 291*5113495bSYour Name When set, the MAC sent an MACRX_ABORT_REQUEST TLV to PHYRX. 292*5113495bSYour Name The abort fields embedded in this TLV contain valid info. 293*5113495bSYour Name 294*5113495bSYour Name <legal all> 295*5113495bSYour Name */ 296*5113495bSYour Name 297*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 298*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 299*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 300*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 301*5113495bSYour Name 302*5113495bSYour Name 303*5113495bSYour Name /* Description RESERVED 304*5113495bSYour Name 305*5113495bSYour Name <legal 0> 306*5113495bSYour Name */ 307*5113495bSYour Name 308*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 309*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 310*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 311*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 312*5113495bSYour Name 313*5113495bSYour Name 314*5113495bSYour Name /* Description COEX_BT_TX_FROM_START_OF_RX 315*5113495bSYour Name 316*5113495bSYour Name Set when BT TX was ongoing when WLAN RX started 317*5113495bSYour Name */ 318*5113495bSYour Name 319*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 320*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 321*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 322*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 323*5113495bSYour Name 324*5113495bSYour Name 325*5113495bSYour Name /* Description COEX_BT_TX_AFTER_START_OF_RX 326*5113495bSYour Name 327*5113495bSYour Name Set when BT TX started while WLAN RX was already ongoing 328*5113495bSYour Name 329*5113495bSYour Name */ 330*5113495bSYour Name 331*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 332*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 333*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 334*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 335*5113495bSYour Name 336*5113495bSYour Name 337*5113495bSYour Name /* Description COEX_WAN_TX_FROM_START_OF_RX 338*5113495bSYour Name 339*5113495bSYour Name Set when WAN TX was ongoing when WLAN RX started 340*5113495bSYour Name */ 341*5113495bSYour Name 342*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 343*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 344*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 345*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 346*5113495bSYour Name 347*5113495bSYour Name 348*5113495bSYour Name /* Description COEX_WAN_TX_AFTER_START_OF_RX 349*5113495bSYour Name 350*5113495bSYour Name Set when WAN TX started while WLAN RX was already ongoing 351*5113495bSYour Name 352*5113495bSYour Name */ 353*5113495bSYour Name 354*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 355*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 356*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 357*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 358*5113495bSYour Name 359*5113495bSYour Name 360*5113495bSYour Name /* Description COEX_WLAN_TX_FROM_START_OF_RX 361*5113495bSYour Name 362*5113495bSYour Name Set when other WLAN TX was ongoing when WLAN RX started 363*5113495bSYour Name */ 364*5113495bSYour Name 365*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 366*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 367*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 368*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 369*5113495bSYour Name 370*5113495bSYour Name 371*5113495bSYour Name /* Description COEX_WLAN_TX_AFTER_START_OF_RX 372*5113495bSYour Name 373*5113495bSYour Name Set when other WLAN TX started while WLAN RX was already 374*5113495bSYour Name ongoing 375*5113495bSYour Name */ 376*5113495bSYour Name 377*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 378*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 379*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 380*5113495bSYour Name #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 381*5113495bSYour Name 382*5113495bSYour Name 383*5113495bSYour Name /* Description MPDU_DELIMITER_ERRORS_SEEN 384*5113495bSYour Name 385*5113495bSYour Name When set, MPDU delimiter errors have been detected during 386*5113495bSYour Name this PPDU reception 387*5113495bSYour Name */ 388*5113495bSYour Name 389*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 390*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 391*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 392*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 393*5113495bSYour Name 394*5113495bSYour Name 395*5113495bSYour Name /* Description FTM_TM 396*5113495bSYour Name 397*5113495bSYour Name Indicate the timestamp is for the FTM or TM frame 398*5113495bSYour Name 399*5113495bSYour Name 0: non TM or FTM frame 400*5113495bSYour Name 1: FTM frame 401*5113495bSYour Name 2: TM frame 402*5113495bSYour Name 3: reserved 403*5113495bSYour Name <legal all> 404*5113495bSYour Name */ 405*5113495bSYour Name 406*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 407*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 408*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 409*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 410*5113495bSYour Name 411*5113495bSYour Name 412*5113495bSYour Name /* Description DIALOG_TOKEN 413*5113495bSYour Name 414*5113495bSYour Name The dialog token in the FTM or TM frame. Only valid when 415*5113495bSYour Name the FTM is set. Clear to 254 for a non-FTM frame 416*5113495bSYour Name <legal all> 417*5113495bSYour Name */ 418*5113495bSYour Name 419*5113495bSYour Name #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 420*5113495bSYour Name #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 421*5113495bSYour Name #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 422*5113495bSYour Name #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 423*5113495bSYour Name 424*5113495bSYour Name 425*5113495bSYour Name /* Description FOLLOW_UP_DIALOG_TOKEN 426*5113495bSYour Name 427*5113495bSYour Name The follow up dialog token in the FTM or TM frame. Only 428*5113495bSYour Name valid when the FTM is set. Clear to 0 for a non-FTM frame, 429*5113495bSYour Name The follow up dialog token in the FTM frame. Only valid 430*5113495bSYour Name when the FTM is set. Clear to 255 for a non-FTM frame<legal 431*5113495bSYour Name all> 432*5113495bSYour Name */ 433*5113495bSYour Name 434*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 435*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 436*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 437*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 438*5113495bSYour Name 439*5113495bSYour Name 440*5113495bSYour Name /* Description BB_CAPTURED_CHANNEL 441*5113495bSYour Name 442*5113495bSYour Name Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is sent 443*5113495bSYour Name to PHY, FW check it to correlate current PPDU TLVs with 444*5113495bSYour Name uploaded channel information. 445*5113495bSYour Name 446*5113495bSYour Name <legal all> 447*5113495bSYour Name */ 448*5113495bSYour Name 449*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 450*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 451*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 452*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 453*5113495bSYour Name 454*5113495bSYour Name 455*5113495bSYour Name /* Description BB_CAPTURED_REASON 456*5113495bSYour Name 457*5113495bSYour Name Copy "capture_reason" of MACRX_FREEZE_CAPTURE_CHANNEL TLV 458*5113495bSYour Name to here for FW usage. Valid when bb_captured_channel or 459*5113495bSYour Name bb_captured_timeout is set. 460*5113495bSYour Name 461*5113495bSYour Name This field indicates why the MAC asked to capture the channel 462*5113495bSYour Name 463*5113495bSYour Name <enum 0 freeze_reason_TM> 464*5113495bSYour Name <enum 1 freeze_reason_FTM> 465*5113495bSYour Name <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 466*5113495bSYour Name <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 467*5113495bSYour Name <enum 4 freeze_reason_NDPA_NDP> 468*5113495bSYour Name <enum 5 freeze_reason_ALL_PACKET> 469*5113495bSYour Name 470*5113495bSYour Name <legal 0-5> 471*5113495bSYour Name */ 472*5113495bSYour Name 473*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 474*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 475*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 476*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 477*5113495bSYour Name 478*5113495bSYour Name 479*5113495bSYour Name /* Description BB_CAPTURED_TIMEOUT 480*5113495bSYour Name 481*5113495bSYour Name Set by RxPCU to indicate channel capture condition is meet, 482*5113495bSYour Name but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due 483*5113495bSYour Name to AST long delay, which means the rx_frame_falling edge 484*5113495bSYour Name to FREEZE TLV ready time exceed the threshold time defined 485*5113495bSYour Name by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 486*5113495bSYour Name Bb_captured_reason is still valid in this case. 487*5113495bSYour Name 488*5113495bSYour Name <legal all> 489*5113495bSYour Name */ 490*5113495bSYour Name 491*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 492*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 493*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 494*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 495*5113495bSYour Name 496*5113495bSYour Name 497*5113495bSYour Name /* Description RESERVED_3 498*5113495bSYour Name 499*5113495bSYour Name <legal 0> 500*5113495bSYour Name */ 501*5113495bSYour Name 502*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 503*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 504*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 505*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 506*5113495bSYour Name 507*5113495bSYour Name 508*5113495bSYour Name /* Description BEFORE_MPDU_COUNT_PASSING_FCS 509*5113495bSYour Name 510*5113495bSYour Name Number of MPDUs received in this PPDU that passed the FCS 511*5113495bSYour Name check before the Coex TX started 512*5113495bSYour Name 513*5113495bSYour Name The counter saturates at 0x3FF. 514*5113495bSYour Name <legal all> 515*5113495bSYour Name */ 516*5113495bSYour Name 517*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 518*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 519*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 520*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff 521*5113495bSYour Name 522*5113495bSYour Name 523*5113495bSYour Name /* Description BEFORE_MPDU_COUNT_FAILING_FCS 524*5113495bSYour Name 525*5113495bSYour Name Number of MPDUs received in this PPDU that failed the FCS 526*5113495bSYour Name check before the Coex TX started 527*5113495bSYour Name 528*5113495bSYour Name The counter saturates at 0x3FF. 529*5113495bSYour Name <legal all> 530*5113495bSYour Name */ 531*5113495bSYour Name 532*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 533*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 534*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 535*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 536*5113495bSYour Name 537*5113495bSYour Name 538*5113495bSYour Name /* Description AFTER_MPDU_COUNT_PASSING_FCS 539*5113495bSYour Name 540*5113495bSYour Name Number of MPDUs received in this PPDU that passed the FCS 541*5113495bSYour Name check after the moment the Coex TX started 542*5113495bSYour Name 543*5113495bSYour Name (Note: The partially received MPDU when the COEX tx start 544*5113495bSYour Name event came in falls in the "after" category) 545*5113495bSYour Name 546*5113495bSYour Name The counter saturates at 0x3FF. 547*5113495bSYour Name <legal all> 548*5113495bSYour Name */ 549*5113495bSYour Name 550*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 551*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 552*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 553*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 554*5113495bSYour Name 555*5113495bSYour Name 556*5113495bSYour Name /* Description RESERVED_4 557*5113495bSYour Name 558*5113495bSYour Name <legal 0> 559*5113495bSYour Name */ 560*5113495bSYour Name 561*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 562*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 563*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 564*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 565*5113495bSYour Name 566*5113495bSYour Name 567*5113495bSYour Name /* Description AFTER_MPDU_COUNT_FAILING_FCS 568*5113495bSYour Name 569*5113495bSYour Name Number of MPDUs received in this PPDU that failed the FCS 570*5113495bSYour Name check after the moment the Coex TX started 571*5113495bSYour Name 572*5113495bSYour Name (Note: The partially received MPDU when the COEX tx start 573*5113495bSYour Name event came in falls in the "after" category) 574*5113495bSYour Name 575*5113495bSYour Name The counter saturates at 0x3FF. 576*5113495bSYour Name <legal all> 577*5113495bSYour Name */ 578*5113495bSYour Name 579*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 580*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 581*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 582*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 583*5113495bSYour Name 584*5113495bSYour Name 585*5113495bSYour Name /* Description RESERVED_5 586*5113495bSYour Name 587*5113495bSYour Name <legal 0> 588*5113495bSYour Name */ 589*5113495bSYour Name 590*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 591*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 592*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 593*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 594*5113495bSYour Name 595*5113495bSYour Name 596*5113495bSYour Name /* Description PHY_TIMESTAMP_TX_LOWER_32 597*5113495bSYour Name 598*5113495bSYour Name The PHY timestamp in the AMPI of the most recent rising 599*5113495bSYour Name edge (TODO: of what ???) after the TX_PHY_DESC. This field 600*5113495bSYour Name indicates the lower 32 bits of the timestamp 601*5113495bSYour Name */ 602*5113495bSYour Name 603*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 604*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 605*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 606*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff 607*5113495bSYour Name 608*5113495bSYour Name 609*5113495bSYour Name /* Description PHY_TIMESTAMP_TX_UPPER_32 610*5113495bSYour Name 611*5113495bSYour Name The PHY timestamp in the AMPI of the most recent rising 612*5113495bSYour Name edge (TODO: of what ???) after the TX_PHY_DESC. This field 613*5113495bSYour Name indicates the upper 32 bits of the timestamp 614*5113495bSYour Name */ 615*5113495bSYour Name 616*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 617*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 618*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 619*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 620*5113495bSYour Name 621*5113495bSYour Name 622*5113495bSYour Name /* Description BB_LENGTH 623*5113495bSYour Name 624*5113495bSYour Name Indicates the number of bytes of baseband information for 625*5113495bSYour Name PPDUs where the BB descriptor preamble type is 0x80 to 626*5113495bSYour Name 0xFF which indicates that this is not a normal PPDU but 627*5113495bSYour Name rather contains baseband debug information. 628*5113495bSYour Name TODO: Is this still needed ??? 629*5113495bSYour Name */ 630*5113495bSYour Name 631*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 632*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 633*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 634*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff 635*5113495bSYour Name 636*5113495bSYour Name 637*5113495bSYour Name 638*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 639*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 640*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 641*5113495bSYour Name #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 642*5113495bSYour Name 643*5113495bSYour Name 644*5113495bSYour Name /* Description RESERVED_8 645*5113495bSYour Name 646*5113495bSYour Name Reserved: HW should fill with 0, FW should ignore. 647*5113495bSYour Name */ 648*5113495bSYour Name 649*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 650*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 651*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 652*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 653*5113495bSYour Name 654*5113495bSYour Name 655*5113495bSYour Name /* Description FIRST_BT_BROADCAST_STATUS_DETAILS 656*5113495bSYour Name 657*5113495bSYour Name Same contents as field "bt_broadcast_status_details" for 658*5113495bSYour Name the first received COEX_STATUS_BROADCAST tlv during this 659*5113495bSYour Name PPDU reception. 660*5113495bSYour Name 661*5113495bSYour Name If no COEX_STATUS_BROADCAST tlv is received during this 662*5113495bSYour Name PPDU reception, this field will be set to 0 663*5113495bSYour Name 664*5113495bSYour Name <legal all> 665*5113495bSYour Name */ 666*5113495bSYour Name 667*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 668*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 669*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 670*5113495bSYour Name #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 671*5113495bSYour Name 672*5113495bSYour Name 673*5113495bSYour Name /* Description RX_PPDU_DURATION 674*5113495bSYour Name 675*5113495bSYour Name The length of this PPDU reception in us 676*5113495bSYour Name */ 677*5113495bSYour Name 678*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 679*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 680*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 681*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 682*5113495bSYour Name 683*5113495bSYour Name 684*5113495bSYour Name /* Description RESERVED_9 685*5113495bSYour Name 686*5113495bSYour Name <legal 0> 687*5113495bSYour Name */ 688*5113495bSYour Name 689*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 690*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 691*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 692*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 693*5113495bSYour Name 694*5113495bSYour Name 695*5113495bSYour Name /* Description AST_INDEX 696*5113495bSYour Name 697*5113495bSYour Name The AST index of the receive Ack/BA. This information is 698*5113495bSYour Name provided from the TXPCU to the RXPCU for receive Ack/BA 699*5113495bSYour Name for implicit beamforming. 700*5113495bSYour Name <legal all> 701*5113495bSYour Name */ 702*5113495bSYour Name 703*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 704*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 705*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 706*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff 707*5113495bSYour Name 708*5113495bSYour Name 709*5113495bSYour Name /* Description AST_INDEX_VALID 710*5113495bSYour Name 711*5113495bSYour Name Indicates that ast_index is valid. Should only be set for 712*5113495bSYour Name receive Ack/BA where single stream implicit sounding is 713*5113495bSYour Name captured. 714*5113495bSYour Name */ 715*5113495bSYour Name 716*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 717*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 718*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 719*5113495bSYour Name #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 720*5113495bSYour Name 721*5113495bSYour Name 722*5113495bSYour Name /* Description RESERVED_10 723*5113495bSYour Name 724*5113495bSYour Name <legal 0> 725*5113495bSYour Name */ 726*5113495bSYour Name 727*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 728*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 729*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 730*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 731*5113495bSYour Name 732*5113495bSYour Name 733*5113495bSYour Name /* Description SECOND_BT_BROADCAST_STATUS_DETAILS 734*5113495bSYour Name 735*5113495bSYour Name Same contents as field "bt_broadcast_status_details" for 736*5113495bSYour Name the second received COEX_STATUS_BROADCAST tlv during this 737*5113495bSYour Name PPDU reception. 738*5113495bSYour Name 739*5113495bSYour Name If no second COEX_STATUS_BROADCAST tlv is received during 740*5113495bSYour Name this PPDU reception, this field will be set to 0 741*5113495bSYour Name 742*5113495bSYour Name <legal all> 743*5113495bSYour Name */ 744*5113495bSYour Name 745*5113495bSYour Name #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 746*5113495bSYour Name #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 747*5113495bSYour Name #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 748*5113495bSYour Name #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 749*5113495bSYour Name 750*5113495bSYour Name 751*5113495bSYour Name /* Description PHYRX_ABORT_REQUEST_INFO_DETAILS 752*5113495bSYour Name 753*5113495bSYour Name Field only valid when Phyrx_abort_request_info_valid is 754*5113495bSYour Name set 755*5113495bSYour Name The reason why PHY generated an abort request 756*5113495bSYour Name */ 757*5113495bSYour Name 758*5113495bSYour Name 759*5113495bSYour Name /* Description PHYRX_ABORT_REASON 760*5113495bSYour Name 761*5113495bSYour Name <enum 0 phyrx_err_phy_off> Reception aborted due to receiving 762*5113495bSYour Name a PHY_OFF TLV 763*5113495bSYour Name <enum 1 phyrx_err_synth_off> 764*5113495bSYour Name <enum 2 phyrx_err_ofdma_timing> 765*5113495bSYour Name <enum 3 phyrx_err_ofdma_signal_parity> 766*5113495bSYour Name <enum 4 phyrx_err_ofdma_rate_illegal> 767*5113495bSYour Name <enum 5 phyrx_err_ofdma_length_illegal> 768*5113495bSYour Name <enum 6 phyrx_err_ofdma_restart> 769*5113495bSYour Name <enum 7 phyrx_err_ofdma_service> 770*5113495bSYour Name <enum 8 phyrx_err_ppdu_ofdma_power_drop> 771*5113495bSYour Name 772*5113495bSYour Name <enum 9 phyrx_err_cck_blokker> 773*5113495bSYour Name <enum 10 phyrx_err_cck_timing> 774*5113495bSYour Name <enum 11 phyrx_err_cck_header_crc> 775*5113495bSYour Name <enum 12 phyrx_err_cck_rate_illegal> 776*5113495bSYour Name <enum 13 phyrx_err_cck_length_illegal> 777*5113495bSYour Name <enum 14 phyrx_err_cck_restart> 778*5113495bSYour Name <enum 15 phyrx_err_cck_service> 779*5113495bSYour Name <enum 16 phyrx_err_cck_power_drop> 780*5113495bSYour Name 781*5113495bSYour Name <enum 17 phyrx_err_ht_crc_err> 782*5113495bSYour Name <enum 18 phyrx_err_ht_length_illegal> 783*5113495bSYour Name <enum 19 phyrx_err_ht_rate_illegal> 784*5113495bSYour Name <enum 20 phyrx_err_ht_zlf> 785*5113495bSYour Name <enum 21 phyrx_err_false_radar_ext> 786*5113495bSYour Name <enum 22 phyrx_err_green_field> 787*5113495bSYour Name <enum 60 phyrx_err_ht_nsym_lt_zero> 788*5113495bSYour Name 789*5113495bSYour Name <enum 23 phyrx_err_bw_gt_dyn_bw> 790*5113495bSYour Name <enum 24 phyrx_err_leg_ht_mismatch> 791*5113495bSYour Name <enum 25 phyrx_err_vht_crc_error> 792*5113495bSYour Name <enum 26 phyrx_err_vht_siga_unsupported> 793*5113495bSYour Name <enum 27 phyrx_err_vht_lsig_len_invalid> 794*5113495bSYour Name <enum 28 phyrx_err_vht_ndp_or_zlf> 795*5113495bSYour Name <enum 29 phyrx_err_vht_nsym_lt_zero> 796*5113495bSYour Name <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 797*5113495bSYour Name <enum 31 phyrx_err_vht_rx_skip_group_id0> 798*5113495bSYour Name <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 799*5113495bSYour Name <enum 33 phyrx_err_vht_rx_skip_group_id63> 800*5113495bSYour Name <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 801*5113495bSYour Name <enum 35 phyrx_err_defer_nap> 802*5113495bSYour Name 803*5113495bSYour Name <enum 61 phyrx_err_vht_lsig_rate_mismatch> 804*5113495bSYour Name <enum 62 phyrx_err_vht_paid_gid_mismatch> 805*5113495bSYour Name <enum 63 phyrx_err_vht_unsupported_bw> 806*5113495bSYour Name <enum 64 phyrx_err_vht_gi_disam_mismatch> 807*5113495bSYour Name 808*5113495bSYour Name <enum 36 phyrx_err_fdomain_timeout> 809*5113495bSYour Name <enum 37 phyrx_err_lsig_rel_check> 810*5113495bSYour Name <enum 38 phyrx_err_bt_collision> 811*5113495bSYour Name <enum 39 phyrx_err_unsupported_mu_feedback> 812*5113495bSYour Name <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 813*5113495bSYour Name <enum 41 phyrx_err_unsupported_cbf> 814*5113495bSYour Name 815*5113495bSYour Name <enum 42 phyrx_err_other> Should not really be used. If 816*5113495bSYour Name needed, ask for documentation update 817*5113495bSYour Name 818*5113495bSYour Name <enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error 819*5113495bSYour Name > <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported 820*5113495bSYour Name > <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 821*5113495bSYour Name > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 822*5113495bSYour Name phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported 823*5113495bSYour Name > 824*5113495bSYour Name <enum 54 phyrx_err_he_sigb_crc_error> 825*5113495bSYour Name <enum 55 phyrx_err_he_ext_su_unsupported> 826*5113495bSYour Name <enum 56 phyrx_err_he_trig_unsupported> 827*5113495bSYour Name <enum 57 phyrx_err_he_lsig_len_invalid> 828*5113495bSYour Name <enum 58 phyrx_err_he_lsig_rate_mismatch> 829*5113495bSYour Name <enum 59 phyrx_err_ofdma_signal_reliability> 830*5113495bSYour Name 831*5113495bSYour Name <enum 77 phyrx_err_wur_detection> 832*5113495bSYour Name 833*5113495bSYour Name <enum 72 phyrx_err_u_sig_crc_error> 834*5113495bSYour Name <enum 73 phyrx_err_u_sig_unsupported_mode> 835*5113495bSYour Name <enum 74 phyrx_err_u_sig_rsvd_err> 836*5113495bSYour Name <enum 75 phyrx_err_u_sig_mcs_error> 837*5113495bSYour Name <enum 76 phyrx_err_u_sig_bw_error> 838*5113495bSYour Name <enum 79 phyrx_err_u_sig_320_channel_mismatch> 839*5113495bSYour Name <enum 71 phyrx_err_eht_sig_crc_error> 840*5113495bSYour Name <enum 78 phyrx_err_eht_sig_unsupported_mode> 841*5113495bSYour Name 842*5113495bSYour Name <enum 80 phyrx_err_ehtplus_er_detection> 843*5113495bSYour Name 844*5113495bSYour Name <enum 52 phyrx_err_MU_UL_no_power_detected> 845*5113495bSYour Name <enum 53 phyrx_err_MU_UL_not_for_me> 846*5113495bSYour Name 847*5113495bSYour Name <enum 65 phyrx_err_rx_wdg_timeout> 848*5113495bSYour Name <enum 66 phyrx_err_sizing_evt_unexpected> 849*5113495bSYour Name <enum 67 phyrx_err_spectralscan> 850*5113495bSYour Name <enum 68 phyrx_err_radar_misdetected_as_ofdm> 851*5113495bSYour Name <enum 69 phyrx_err_rx_stuck> 852*5113495bSYour Name <enum 70 phyrx_err_invalid_11b_state> 853*5113495bSYour Name 854*5113495bSYour Name <legal 0 - 80> 855*5113495bSYour Name */ 856*5113495bSYour Name 857*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 858*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 859*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 860*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 861*5113495bSYour Name 862*5113495bSYour Name 863*5113495bSYour Name /* Description PHY_ENTERS_NAP_STATE 864*5113495bSYour Name 865*5113495bSYour Name When set, PHY enters PHY NAP state after sending this abort 866*5113495bSYour Name 867*5113495bSYour Name 868*5113495bSYour Name Note that nap and defer state are mutually exclusive. 869*5113495bSYour Name 870*5113495bSYour Name Field put pro-actively in place....usage still to be agreed 871*5113495bSYour Name upon. 872*5113495bSYour Name <legal all> 873*5113495bSYour Name */ 874*5113495bSYour Name 875*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 876*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 877*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 878*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 879*5113495bSYour Name 880*5113495bSYour Name 881*5113495bSYour Name /* Description PHY_ENTERS_DEFER_STATE 882*5113495bSYour Name 883*5113495bSYour Name When set, PHY enters PHY defer state after sending this 884*5113495bSYour Name abort 885*5113495bSYour Name 886*5113495bSYour Name Note that nap and defer state are mutually exclusive. 887*5113495bSYour Name 888*5113495bSYour Name Field put pro-actively in place....usage still to be agreed 889*5113495bSYour Name upon. 890*5113495bSYour Name <legal all> 891*5113495bSYour Name */ 892*5113495bSYour Name 893*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 894*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 895*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 896*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 897*5113495bSYour Name 898*5113495bSYour Name 899*5113495bSYour Name /* Description RESERVED_0 900*5113495bSYour Name 901*5113495bSYour Name <legal 0> 902*5113495bSYour Name */ 903*5113495bSYour Name 904*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 905*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 906*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 907*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 908*5113495bSYour Name 909*5113495bSYour Name 910*5113495bSYour Name /* Description RECEIVE_DURATION 911*5113495bSYour Name 912*5113495bSYour Name The remaining receive duration of this PPDU in the medium 913*5113495bSYour Name (in us). When PHY does not know this duration when this 914*5113495bSYour Name TLV is generated, the field will be set to 0. 915*5113495bSYour Name The timing reference point is the reception by the MAC of 916*5113495bSYour Name this TLV. The value shall be accurate to within 2us. 917*5113495bSYour Name 918*5113495bSYour Name In case Phy_enters_nap_state and/or Phy_enters_defer_state 919*5113495bSYour Name is set, there is a possibility that MAC PMM can also decide 920*5113495bSYour Name to go into a low(er) power state. 921*5113495bSYour Name <legal all> 922*5113495bSYour Name */ 923*5113495bSYour Name 924*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 925*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 926*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 927*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 928*5113495bSYour Name 929*5113495bSYour Name 930*5113495bSYour Name /* Description MACRX_ABORT_REQUEST_INFO_DETAILS 931*5113495bSYour Name 932*5113495bSYour Name Field only valid when macrx_abort_request_info_valid is 933*5113495bSYour Name set 934*5113495bSYour Name The reason why MACRX generated an abort request 935*5113495bSYour Name */ 936*5113495bSYour Name 937*5113495bSYour Name 938*5113495bSYour Name /* Description MACRX_ABORT_REASON 939*5113495bSYour Name 940*5113495bSYour Name <enum 0 macrx_abort_sw_initiated> 941*5113495bSYour Name <enum 1 macrx_abort_obss_reception> Upon receiving this 942*5113495bSYour Name abort reason, PHY should stop reception of the current frame 943*5113495bSYour Name and go back into a search mode 944*5113495bSYour Name <enum 2 macrx_abort_other> 945*5113495bSYour Name <enum 3 macrx_abort_sw_initiated_channel_switch> MAC FW 946*5113495bSYour Name issued an abort for channel switch reasons 947*5113495bSYour Name <enum 4 macrx_abort_sw_initiated_power_save> MAC FW issued 948*5113495bSYour Name an abort power save reasons 949*5113495bSYour Name <enum 5 macrx_abort_too_much_bad_data> RXPCU is terminating 950*5113495bSYour Name the current ongoing reception, as the data that MAC is 951*5113495bSYour Name receiving seems to be all garbage... The PER is too high, 952*5113495bSYour Name or in case of MU UL, Likely the trigger frame never got 953*5113495bSYour Name properly received by any of the targeted MU UL devices. 954*5113495bSYour Name After the abort, PHYRX can resume a normal search mode. 955*5113495bSYour Name <enum 6 macrx_abort_ul_mu_early_abort> RXPCU is terminating 956*5113495bSYour Name the current ongoing UL MU reception, because at the end 957*5113495bSYour Name of the "early_termination_window," the required number 958*5113495bSYour Name of users with at least one valid MPDU delimiter was not 959*5113495bSYour Name reached. Likely the trigger frame never got properly received 960*5113495bSYour Name by the required number of targeted devices. After the abort, 961*5113495bSYour Name PHYRX can resume a normal search mode. 962*5113495bSYour Name 963*5113495bSYour Name <legal 0-6> 964*5113495bSYour Name */ 965*5113495bSYour Name 966*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 967*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 968*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 969*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff 970*5113495bSYour Name 971*5113495bSYour Name 972*5113495bSYour Name /* Description RESERVED_0 973*5113495bSYour Name 974*5113495bSYour Name <legal 0> 975*5113495bSYour Name */ 976*5113495bSYour Name 977*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 978*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 979*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 980*5113495bSYour Name #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 981*5113495bSYour Name 982*5113495bSYour Name 983*5113495bSYour Name /* Description PRE_BT_BROADCAST_STATUS_DETAILS 984*5113495bSYour Name 985*5113495bSYour Name Same contents as field "bt_broadcast_status_details" of 986*5113495bSYour Name the last received COEX_STATUS_BROADCAST tlv before this 987*5113495bSYour Name PPDU reception. 988*5113495bSYour Name After power up, this field is all initialized to 0 989*5113495bSYour Name 990*5113495bSYour Name <legal all> 991*5113495bSYour Name */ 992*5113495bSYour Name 993*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 994*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 995*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 996*5113495bSYour Name #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 997*5113495bSYour Name 998*5113495bSYour Name 999*5113495bSYour Name /* Description RESERVED_12A 1000*5113495bSYour Name 1001*5113495bSYour Name Bits: [27:16] 1002*5113495bSYour Name Same contents as field "bt_broadcast_status_details" of 1003*5113495bSYour Name the last received COEX_STATUS_BROADCAST tlv before this 1004*5113495bSYour Name PPDU reception. 1005*5113495bSYour Name After power up, this field is all initialized to 0 1006*5113495bSYour Name 1007*5113495bSYour Name Bits: [31:28]: always 0 1008*5113495bSYour Name 1009*5113495bSYour Name 1010*5113495bSYour Name For detailed info see doc: TBD 1011*5113495bSYour Name <legal all> 1012*5113495bSYour Name */ 1013*5113495bSYour Name 1014*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 1015*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 1016*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 1017*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 1018*5113495bSYour Name 1019*5113495bSYour Name 1020*5113495bSYour Name /* Description NON_QOS_SN_INFO_VALID 1021*5113495bSYour Name 1022*5113495bSYour Name When set, the non_QoS_SN_... fields contain valid info. 1023*5113495bSYour Name 1024*5113495bSYour Name This field will ONLY be set upon the very first reception 1025*5113495bSYour Name of a non QoS frame. 1026*5113495bSYour Name 1027*5113495bSYour Name <legal all> 1028*5113495bSYour Name */ 1029*5113495bSYour Name 1030*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 1031*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 1032*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 1033*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 1034*5113495bSYour Name 1035*5113495bSYour Name 1036*5113495bSYour Name /* Description RESERVED_13A 1037*5113495bSYour Name 1038*5113495bSYour Name <legal 0> 1039*5113495bSYour Name */ 1040*5113495bSYour Name 1041*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 1042*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 1043*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 1044*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 1045*5113495bSYour Name 1046*5113495bSYour Name 1047*5113495bSYour Name /* Description NON_QOS_SN_HIGHEST 1048*5113495bSYour Name 1049*5113495bSYour Name Field only valid when non_QoS_SN_info_valid is set 1050*5113495bSYour Name 1051*5113495bSYour Name Lowest and highest are defined based on a 2K window. 1052*5113495bSYour Name When only 1 non-QoS frame is received, the 'highest' and 1053*5113495bSYour Name 'lowest' fields will have the same values. 1054*5113495bSYour Name 1055*5113495bSYour Name The highest MPDU sequence number for a non-QoS frame received 1056*5113495bSYour Name in this PPDU 1057*5113495bSYour Name <legal all> 1058*5113495bSYour Name */ 1059*5113495bSYour Name 1060*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 1061*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 1062*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 1063*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 1064*5113495bSYour Name 1065*5113495bSYour Name 1066*5113495bSYour Name /* Description NON_QOS_SN_HIGHEST_RETRY_SETTING 1067*5113495bSYour Name 1068*5113495bSYour Name Field only valid when non_QoS_SN_info_valid is set 1069*5113495bSYour Name 1070*5113495bSYour Name The 'retry' bit setting of the highest MPDU sequence number 1071*5113495bSYour Name non-QOS frame received in this PPDU 1072*5113495bSYour Name <legal all> 1073*5113495bSYour Name */ 1074*5113495bSYour Name 1075*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 1076*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 1077*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 1078*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 1079*5113495bSYour Name 1080*5113495bSYour Name 1081*5113495bSYour Name /* Description NON_QOS_SN_LOWEST 1082*5113495bSYour Name 1083*5113495bSYour Name Field only valid when non_QoS_SN_info_valid is set 1084*5113495bSYour Name 1085*5113495bSYour Name Lowest and highest are defined based on a 2K window. 1086*5113495bSYour Name When only 1 non-QoS frame is received, the 'highest' and 1087*5113495bSYour Name 'lowest' fields will have the same values. 1088*5113495bSYour Name 1089*5113495bSYour Name The lowest MPDU sequence number for a non-QoS frame received 1090*5113495bSYour Name in this PPDU 1091*5113495bSYour Name <legal all> 1092*5113495bSYour Name */ 1093*5113495bSYour Name 1094*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 1095*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 1096*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 1097*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 1098*5113495bSYour Name 1099*5113495bSYour Name 1100*5113495bSYour Name /* Description NON_QOS_SN_LOWEST_RETRY_SETTING 1101*5113495bSYour Name 1102*5113495bSYour Name Field only valid when non_QoS_SN_info_valid is set 1103*5113495bSYour Name 1104*5113495bSYour Name The 'retry' bit setting of the lowest MPDU sequence number 1105*5113495bSYour Name non-QoS frame received in this PPDU 1106*5113495bSYour Name <legal all> 1107*5113495bSYour Name */ 1108*5113495bSYour Name 1109*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 1110*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 1111*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 1112*5113495bSYour Name #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 1113*5113495bSYour Name 1114*5113495bSYour Name 1115*5113495bSYour Name /* Description QOS_SN_1_INFO_VALID 1116*5113495bSYour Name 1117*5113495bSYour Name When set, the QoS_SN_1_... fields contain valid info. 1118*5113495bSYour Name 1119*5113495bSYour Name This field will ONLY be set upon the very first reception 1120*5113495bSYour Name of a QoS frame. 1121*5113495bSYour Name 1122*5113495bSYour Name <legal all> 1123*5113495bSYour Name */ 1124*5113495bSYour Name 1125*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 1126*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 1127*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 1128*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 1129*5113495bSYour Name 1130*5113495bSYour Name 1131*5113495bSYour Name /* Description RESERVED_14A 1132*5113495bSYour Name 1133*5113495bSYour Name <legal 0> 1134*5113495bSYour Name */ 1135*5113495bSYour Name 1136*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 1137*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 1138*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 1139*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 1140*5113495bSYour Name 1141*5113495bSYour Name 1142*5113495bSYour Name /* Description QOS_SN_1_TID 1143*5113495bSYour Name 1144*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1145*5113495bSYour Name 1146*5113495bSYour Name The TID of the frames related to the QoS_SN_1_... fields 1147*5113495bSYour Name 1148*5113495bSYour Name <legal all> 1149*5113495bSYour Name */ 1150*5113495bSYour Name 1151*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 1152*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 1153*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 1154*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c 1155*5113495bSYour Name 1156*5113495bSYour Name 1157*5113495bSYour Name /* Description QOS_SN_1_HIGHEST 1158*5113495bSYour Name 1159*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1160*5113495bSYour Name 1161*5113495bSYour Name Lowest and highest are defined based on a 2K window. 1162*5113495bSYour Name When only 1 QoS frame of the relevant TID is received, the 1163*5113495bSYour Name 'highest' and 'lowest' fields will have the same values. 1164*5113495bSYour Name 1165*5113495bSYour Name 1166*5113495bSYour Name The highest MPDU sequence number for a QoS frame with TID 1167*5113495bSYour Name QoS_SN_1_TID received in this PPDU 1168*5113495bSYour Name <legal all> 1169*5113495bSYour Name */ 1170*5113495bSYour Name 1171*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 1172*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 1173*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 1174*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 1175*5113495bSYour Name 1176*5113495bSYour Name 1177*5113495bSYour Name /* Description QOS_SN_1_HIGHEST_RETRY_SETTING 1178*5113495bSYour Name 1179*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1180*5113495bSYour Name 1181*5113495bSYour Name The 'retry' bit setting of the highest MPDU sequence number 1182*5113495bSYour Name QoS frame with TID QoS_SN_1_TID received in this PPDU 1183*5113495bSYour Name <legal all> 1184*5113495bSYour Name */ 1185*5113495bSYour Name 1186*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 1187*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 1188*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 1189*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 1190*5113495bSYour Name 1191*5113495bSYour Name 1192*5113495bSYour Name /* Description QOS_SN_1_LOWEST 1193*5113495bSYour Name 1194*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1195*5113495bSYour Name 1196*5113495bSYour Name Lowest and highest are defined based on a 2K window. 1197*5113495bSYour Name When only 1 QoS frame of the relevant TID is received, the 1198*5113495bSYour Name 'highest' and 'lowest' fields will have the same values. 1199*5113495bSYour Name 1200*5113495bSYour Name 1201*5113495bSYour Name The lowest MPDU sequence number for a QoS frame with TID 1202*5113495bSYour Name QoS_SN_1_TID received in this PPDU 1203*5113495bSYour Name <legal all> 1204*5113495bSYour Name */ 1205*5113495bSYour Name 1206*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 1207*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 1208*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 1209*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 1210*5113495bSYour Name 1211*5113495bSYour Name 1212*5113495bSYour Name /* Description QOS_SN_1_LOWEST_RETRY_SETTING 1213*5113495bSYour Name 1214*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1215*5113495bSYour Name 1216*5113495bSYour Name The 'retry' bit setting of the lowest MPDU sequence number 1217*5113495bSYour Name QoS frame with TID QoS_SN_1_TID received in this PPDU 1218*5113495bSYour Name <legal all> 1219*5113495bSYour Name */ 1220*5113495bSYour Name 1221*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 1222*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 1223*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 1224*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 1225*5113495bSYour Name 1226*5113495bSYour Name 1227*5113495bSYour Name /* Description QOS_SN_2_INFO_VALID 1228*5113495bSYour Name 1229*5113495bSYour Name When set, the QoS_SN_2_... fields contain valid info. 1230*5113495bSYour Name 1231*5113495bSYour Name This field can ONLY be set in case of a multi-TID PPDU reception. 1232*5113495bSYour Name This field is set upon the very first reception of a QoS 1233*5113495bSYour Name frame belonging to the second TID in the PPDU. 1234*5113495bSYour Name 1235*5113495bSYour Name <legal all> 1236*5113495bSYour Name */ 1237*5113495bSYour Name 1238*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 1239*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 1240*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 1241*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 1242*5113495bSYour Name 1243*5113495bSYour Name 1244*5113495bSYour Name /* Description RESERVED_15A 1245*5113495bSYour Name 1246*5113495bSYour Name <legal 0> 1247*5113495bSYour Name */ 1248*5113495bSYour Name 1249*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 1250*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 1251*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 1252*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 1253*5113495bSYour Name 1254*5113495bSYour Name 1255*5113495bSYour Name /* Description QOS_SN_2_TID 1256*5113495bSYour Name 1257*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1258*5113495bSYour Name 1259*5113495bSYour Name The TID of the frames related to the QoS_SN_2_... fields 1260*5113495bSYour Name 1261*5113495bSYour Name <legal all> 1262*5113495bSYour Name */ 1263*5113495bSYour Name 1264*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 1265*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 1266*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 1267*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 1268*5113495bSYour Name 1269*5113495bSYour Name 1270*5113495bSYour Name /* Description QOS_SN_2_HIGHEST 1271*5113495bSYour Name 1272*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1273*5113495bSYour Name 1274*5113495bSYour Name Lowest and highest are defined based on a 2K window. 1275*5113495bSYour Name When only 1 QoS frame of the relevant TID is received, the 1276*5113495bSYour Name highest and lowest fields will have the same values. 1277*5113495bSYour Name 1278*5113495bSYour Name The highest MPDU sequence number for a QoS frame with TID 1279*5113495bSYour Name QoS_SN_2_TID received in this PPDU 1280*5113495bSYour Name <legal all> 1281*5113495bSYour Name */ 1282*5113495bSYour Name 1283*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 1284*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 1285*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 1286*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 1287*5113495bSYour Name 1288*5113495bSYour Name 1289*5113495bSYour Name /* Description QOS_SN_2_HIGHEST_RETRY_SETTING 1290*5113495bSYour Name 1291*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1292*5113495bSYour Name 1293*5113495bSYour Name The 'retry' bit setting of the highest MPDU sequence number 1294*5113495bSYour Name QoS frame with TID QoS_SN_2_TID received in this PPDU 1295*5113495bSYour Name <legal all> 1296*5113495bSYour Name */ 1297*5113495bSYour Name 1298*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 1299*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 1300*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 1301*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 1302*5113495bSYour Name 1303*5113495bSYour Name 1304*5113495bSYour Name /* Description QOS_SN_2_LOWEST 1305*5113495bSYour Name 1306*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1307*5113495bSYour Name 1308*5113495bSYour Name Lowest and highest are defined based on a 2K window. 1309*5113495bSYour Name When only 1 QoS frame of the relevant TID is received, the 1310*5113495bSYour Name highest and lowest fields will have the same values. 1311*5113495bSYour Name 1312*5113495bSYour Name The lowest MPDU sequence number for a QoS frame with TID 1313*5113495bSYour Name QoS_SN_2_TID received in this PPDU 1314*5113495bSYour Name <legal all> 1315*5113495bSYour Name */ 1316*5113495bSYour Name 1317*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 1318*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 1319*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 1320*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 1321*5113495bSYour Name 1322*5113495bSYour Name 1323*5113495bSYour Name /* Description QOS_SN_2_LOWEST_RETRY_SETTING 1324*5113495bSYour Name 1325*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1326*5113495bSYour Name 1327*5113495bSYour Name The 'retry' bit setting of the lowest MPDU sequence number 1328*5113495bSYour Name QoS frame with TID QoS_SN_2_TID received in this PPDU 1329*5113495bSYour Name <legal all> 1330*5113495bSYour Name */ 1331*5113495bSYour Name 1332*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 1333*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 1334*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 1335*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 1336*5113495bSYour Name 1337*5113495bSYour Name 1338*5113495bSYour Name /* Description RXPCU_PPDU_END_LAYOUT_DETAILS 1339*5113495bSYour Name 1340*5113495bSYour Name Structure containing the relative offsets of preamble TLVs 1341*5113495bSYour Name within 'RX_PPDU_END' documenting the layout within 'RX_PPDU_END' 1342*5113495bSYour Name 1343*5113495bSYour Name */ 1344*5113495bSYour Name 1345*5113495bSYour Name 1346*5113495bSYour Name /* Description RSSI_LEGACY_OFFSET 1347*5113495bSYour Name 1348*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within 1349*5113495bSYour Name 'RX_PPDU_END'<legal 1, 2> 1350*5113495bSYour Name */ 1351*5113495bSYour Name 1352*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 1353*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 1354*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 1355*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 1356*5113495bSYour Name 1357*5113495bSYour Name 1358*5113495bSYour Name /* Description L_SIG_A_OFFSET 1359*5113495bSYour Name 1360*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 1361*5113495bSYour Name Set to zero if the TLV is not included<legal 0, 44, 46> 1362*5113495bSYour Name */ 1363*5113495bSYour Name 1364*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 1365*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 1366*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 1367*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc 1368*5113495bSYour Name 1369*5113495bSYour Name 1370*5113495bSYour Name /* Description L_SIG_B_OFFSET 1371*5113495bSYour Name 1372*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 1373*5113495bSYour Name Set to zero if the TLV is not included<legal 0, 44, 46> 1374*5113495bSYour Name */ 1375*5113495bSYour Name 1376*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 1377*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 1378*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 1379*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 1380*5113495bSYour Name 1381*5113495bSYour Name 1382*5113495bSYour Name /* Description HT_SIG_OFFSET 1383*5113495bSYour Name 1384*5113495bSYour Name Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero 1385*5113495bSYour Name if the TLV is not included<legal 0, 46, 50> 1386*5113495bSYour Name */ 1387*5113495bSYour Name 1388*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 1389*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 1390*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 1391*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 1392*5113495bSYour Name 1393*5113495bSYour Name 1394*5113495bSYour Name /* Description VHT_SIG_A_OFFSET 1395*5113495bSYour Name 1396*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' 1397*5113495bSYour Name Set to zero if the TLV is not included<legal 0, 46, 50> 1398*5113495bSYour Name */ 1399*5113495bSYour Name 1400*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 1401*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 1402*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 1403*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 1404*5113495bSYour Name 1405*5113495bSYour Name 1406*5113495bSYour Name /* Description REPEAT_L_SIG_A_OFFSET 1407*5113495bSYour Name 1408*5113495bSYour Name Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in 1409*5113495bSYour Name HE and EHT cases) within 'RX_PPDU_END' 1410*5113495bSYour Name 1411*5113495bSYour Name Set to zero if the TLV is not included 1412*5113495bSYour Name <legal 0, 46, 50> 1413*5113495bSYour Name */ 1414*5113495bSYour Name 1415*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 1416*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 1417*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 1418*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 1419*5113495bSYour Name 1420*5113495bSYour Name 1421*5113495bSYour Name /* Description HE_SIG_A_SU_OFFSET 1422*5113495bSYour Name 1423*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within 1424*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1425*5113495bSYour Name 0, 48, 54> 1426*5113495bSYour Name */ 1427*5113495bSYour Name 1428*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 1429*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 1430*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 1431*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 1432*5113495bSYour Name 1433*5113495bSYour Name 1434*5113495bSYour Name /* Description HE_SIG_A_MU_DL_OFFSET 1435*5113495bSYour Name 1436*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within 1437*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1438*5113495bSYour Name 0, 48, 54> 1439*5113495bSYour Name */ 1440*5113495bSYour Name 1441*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 1442*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 1443*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 1444*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 1445*5113495bSYour Name 1446*5113495bSYour Name 1447*5113495bSYour Name /* Description HE_SIG_A_MU_UL_OFFSET 1448*5113495bSYour Name 1449*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within 1450*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1451*5113495bSYour Name 0, 48, 54> 1452*5113495bSYour Name */ 1453*5113495bSYour Name 1454*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 1455*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 1456*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 1457*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 1458*5113495bSYour Name 1459*5113495bSYour Name 1460*5113495bSYour Name /* Description GENERIC_U_SIG_OFFSET 1461*5113495bSYour Name 1462*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within 1463*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1464*5113495bSYour Name 0, 48, 54> 1465*5113495bSYour Name */ 1466*5113495bSYour Name 1467*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 1468*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 1469*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 1470*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 1471*5113495bSYour Name 1472*5113495bSYour Name 1473*5113495bSYour Name /* Description RSSI_HT_OFFSET 1474*5113495bSYour Name 1475*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' 1476*5113495bSYour Name Set to zero if the TLV is not included<legal 0, 49-127> 1477*5113495bSYour Name */ 1478*5113495bSYour Name 1479*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 1480*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 1481*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 1482*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 1483*5113495bSYour Name 1484*5113495bSYour Name 1485*5113495bSYour Name /* Description RESERVED_1A 1486*5113495bSYour Name 1487*5113495bSYour Name <legal 0> 1488*5113495bSYour Name */ 1489*5113495bSYour Name 1490*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 1491*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 1492*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 1493*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 1494*5113495bSYour Name 1495*5113495bSYour Name 1496*5113495bSYour Name /* Description VHT_SIG_B_SU20_OFFSET 1497*5113495bSYour Name 1498*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within 1499*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1500*5113495bSYour Name 0, 67, 74> 1501*5113495bSYour Name */ 1502*5113495bSYour Name 1503*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 1504*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 1505*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 1506*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f 1507*5113495bSYour Name 1508*5113495bSYour Name 1509*5113495bSYour Name /* Description VHT_SIG_B_SU40_OFFSET 1510*5113495bSYour Name 1511*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within 1512*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1513*5113495bSYour Name 0, 67, 74> 1514*5113495bSYour Name */ 1515*5113495bSYour Name 1516*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 1517*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 1518*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 1519*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 1520*5113495bSYour Name 1521*5113495bSYour Name 1522*5113495bSYour Name /* Description VHT_SIG_B_SU80_OFFSET 1523*5113495bSYour Name 1524*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within 1525*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1526*5113495bSYour Name 0, 67, 74> 1527*5113495bSYour Name */ 1528*5113495bSYour Name 1529*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 1530*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 1531*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 1532*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 1533*5113495bSYour Name 1534*5113495bSYour Name 1535*5113495bSYour Name /* Description VHT_SIG_B_SU160_OFFSET 1536*5113495bSYour Name 1537*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within 1538*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1539*5113495bSYour Name 0, 67, 74> 1540*5113495bSYour Name */ 1541*5113495bSYour Name 1542*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 1543*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 1544*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 1545*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 1546*5113495bSYour Name 1547*5113495bSYour Name 1548*5113495bSYour Name /* Description RESERVED_2A 1549*5113495bSYour Name 1550*5113495bSYour Name <legal 0> 1551*5113495bSYour Name */ 1552*5113495bSYour Name 1553*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 1554*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 1555*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 1556*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 1557*5113495bSYour Name 1558*5113495bSYour Name 1559*5113495bSYour Name /* Description VHT_SIG_B_MU20_OFFSET 1560*5113495bSYour Name 1561*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within 1562*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1563*5113495bSYour Name 0, 67, 74> 1564*5113495bSYour Name */ 1565*5113495bSYour Name 1566*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 1567*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 1568*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 1569*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 1570*5113495bSYour Name 1571*5113495bSYour Name 1572*5113495bSYour Name /* Description VHT_SIG_B_MU40_OFFSET 1573*5113495bSYour Name 1574*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within 1575*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1576*5113495bSYour Name 0, 67, 74> 1577*5113495bSYour Name */ 1578*5113495bSYour Name 1579*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 1580*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 1581*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 1582*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 1583*5113495bSYour Name 1584*5113495bSYour Name 1585*5113495bSYour Name /* Description VHT_SIG_B_MU80_OFFSET 1586*5113495bSYour Name 1587*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within 1588*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1589*5113495bSYour Name 0, 67, 74> 1590*5113495bSYour Name */ 1591*5113495bSYour Name 1592*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 1593*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 1594*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 1595*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 1596*5113495bSYour Name 1597*5113495bSYour Name 1598*5113495bSYour Name /* Description VHT_SIG_B_MU160_OFFSET 1599*5113495bSYour Name 1600*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within 1601*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1602*5113495bSYour Name 0, 67, 74> 1603*5113495bSYour Name */ 1604*5113495bSYour Name 1605*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 1606*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 1607*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 1608*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 1609*5113495bSYour Name 1610*5113495bSYour Name 1611*5113495bSYour Name /* Description RESERVED_3A 1612*5113495bSYour Name 1613*5113495bSYour Name <legal 0> 1614*5113495bSYour Name */ 1615*5113495bSYour Name 1616*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 1617*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 1618*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 1619*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 1620*5113495bSYour Name 1621*5113495bSYour Name 1622*5113495bSYour Name /* Description HE_SIG_B1_MU_OFFSET 1623*5113495bSYour Name 1624*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within 1625*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1626*5113495bSYour Name 0, 51, 58> 1627*5113495bSYour Name */ 1628*5113495bSYour Name 1629*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 1630*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 1631*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 1632*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f 1633*5113495bSYour Name 1634*5113495bSYour Name 1635*5113495bSYour Name /* Description HE_SIG_B2_MU_OFFSET 1636*5113495bSYour Name 1637*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within 1638*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1639*5113495bSYour Name 0, 51, 58> 1640*5113495bSYour Name */ 1641*5113495bSYour Name 1642*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 1643*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 1644*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 1645*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 1646*5113495bSYour Name 1647*5113495bSYour Name 1648*5113495bSYour Name /* Description HE_SIG_B2_OFDMA_OFFSET 1649*5113495bSYour Name 1650*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within 1651*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1652*5113495bSYour Name 0, 53, 62> 1653*5113495bSYour Name */ 1654*5113495bSYour Name 1655*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 1656*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 1657*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 1658*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 1659*5113495bSYour Name 1660*5113495bSYour Name 1661*5113495bSYour Name /* Description FIRST_GENERIC_EHT_SIG_OFFSET 1662*5113495bSYour Name 1663*5113495bSYour Name Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' 1664*5113495bSYour Name within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1665*5113495bSYour Name 0, 51, 58> 1666*5113495bSYour Name */ 1667*5113495bSYour Name 1668*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 1669*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 1670*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 1671*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 1672*5113495bSYour Name 1673*5113495bSYour Name 1674*5113495bSYour Name /* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED 1675*5113495bSYour Name 1676*5113495bSYour Name Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs 1677*5113495bSYour Name are included in 'RX_PPDU_END,' set to zero otherwise 1678*5113495bSYour Name <legal all> 1679*5113495bSYour Name */ 1680*5113495bSYour Name 1681*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 1682*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 1683*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 1684*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 1685*5113495bSYour Name 1686*5113495bSYour Name 1687*5113495bSYour Name /* Description RESERVED_4A 1688*5113495bSYour Name 1689*5113495bSYour Name <legal 0> 1690*5113495bSYour Name */ 1691*5113495bSYour Name 1692*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 1693*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 1694*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 1695*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 1696*5113495bSYour Name 1697*5113495bSYour Name 1698*5113495bSYour Name /* Description COMMON_USER_INFO_OFFSET 1699*5113495bSYour Name 1700*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within 1701*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1702*5113495bSYour Name 0, 46, 50, 67, 70-127> 1703*5113495bSYour Name */ 1704*5113495bSYour Name 1705*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 1706*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 1707*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 1708*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 1709*5113495bSYour Name 1710*5113495bSYour Name 1711*5113495bSYour Name /* Description FIRST_DEBUG_INFO_OFFSET 1712*5113495bSYour Name 1713*5113495bSYour Name Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' 1714*5113495bSYour Name within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1715*5113495bSYour Name all> 1716*5113495bSYour Name */ 1717*5113495bSYour Name 1718*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 1719*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 1720*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 1721*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 1722*5113495bSYour Name 1723*5113495bSYour Name 1724*5113495bSYour Name /* Description MULTIPLE_DEBUG_INFO_INCLUDED 1725*5113495bSYour Name 1726*5113495bSYour Name Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are 1727*5113495bSYour Name included in 'RX_PPDU_END,' set to zero otherwise<legal all> 1728*5113495bSYour Name 1729*5113495bSYour Name */ 1730*5113495bSYour Name 1731*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 1732*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 1733*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 1734*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 1735*5113495bSYour Name 1736*5113495bSYour Name 1737*5113495bSYour Name /* Description FIRST_OTHER_RECEIVE_INFO_OFFSET 1738*5113495bSYour Name 1739*5113495bSYour Name Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' 1740*5113495bSYour Name within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1741*5113495bSYour Name all> 1742*5113495bSYour Name */ 1743*5113495bSYour Name 1744*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 1745*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 1746*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 1747*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 1748*5113495bSYour Name 1749*5113495bSYour Name 1750*5113495bSYour Name /* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED 1751*5113495bSYour Name 1752*5113495bSYour Name Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs 1753*5113495bSYour Name are included in 'RX_PPDU_END,' set to zero otherwise<legal 1754*5113495bSYour Name all> 1755*5113495bSYour Name */ 1756*5113495bSYour Name 1757*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 1758*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 1759*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 1760*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 1761*5113495bSYour Name 1762*5113495bSYour Name 1763*5113495bSYour Name /* Description RESERVED_5A 1764*5113495bSYour Name 1765*5113495bSYour Name <legal 0> 1766*5113495bSYour Name */ 1767*5113495bSYour Name 1768*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 1769*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 1770*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 1771*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 1772*5113495bSYour Name 1773*5113495bSYour Name 1774*5113495bSYour Name /* Description DATA_DONE_OFFSET 1775*5113495bSYour Name 1776*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' 1777*5113495bSYour Name Set to zero if the TLV is not included<legal all> 1778*5113495bSYour Name */ 1779*5113495bSYour Name 1780*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 1781*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 1782*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 1783*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff 1784*5113495bSYour Name 1785*5113495bSYour Name 1786*5113495bSYour Name /* Description GENERATED_CBF_DETAILS_OFFSET 1787*5113495bSYour Name 1788*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' 1789*5113495bSYour Name within 'RX_PPDU_END'Set to zero if the TLV is not included<legal 1790*5113495bSYour Name 0, 70-127> 1791*5113495bSYour Name */ 1792*5113495bSYour Name 1793*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 1794*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 1795*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 1796*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 1797*5113495bSYour Name 1798*5113495bSYour Name 1799*5113495bSYour Name /* Description PKT_END_PART1_OFFSET 1800*5113495bSYour Name 1801*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within 1802*5113495bSYour Name 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1803*5113495bSYour Name all> 1804*5113495bSYour Name */ 1805*5113495bSYour Name 1806*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 1807*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 1808*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 1809*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 1810*5113495bSYour Name 1811*5113495bSYour Name 1812*5113495bSYour Name /* Description LOCATION_OFFSET 1813*5113495bSYour Name 1814*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' 1815*5113495bSYour Name Set to zero if the TLV is not included<legal all> 1816*5113495bSYour Name */ 1817*5113495bSYour Name 1818*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 1819*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 1820*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 1821*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 1822*5113495bSYour Name 1823*5113495bSYour Name 1824*5113495bSYour Name /* Description AZ_INTEGRITY_DATA_OFFSET 1825*5113495bSYour Name 1826*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' 1827*5113495bSYour Name within 'RX_PPDU_END' 1828*5113495bSYour Name 1829*5113495bSYour Name Set to zero if the TLV is not included 1830*5113495bSYour Name <legal all> 1831*5113495bSYour Name */ 1832*5113495bSYour Name 1833*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 1834*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 1835*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 1836*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 1837*5113495bSYour Name 1838*5113495bSYour Name 1839*5113495bSYour Name /* Description PKT_END_OFFSET 1840*5113495bSYour Name 1841*5113495bSYour Name Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' 1842*5113495bSYour Name Set to zero if the TLV is not included<legal all> 1843*5113495bSYour Name */ 1844*5113495bSYour Name 1845*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 1846*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 1847*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 1848*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 1849*5113495bSYour Name 1850*5113495bSYour Name 1851*5113495bSYour Name /* Description ABORT_REQUEST_ACK_OFFSET 1852*5113495bSYour Name 1853*5113495bSYour Name Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' 1854*5113495bSYour Name or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' 1855*5113495bSYour Name 1856*5113495bSYour Name Set to zero if the TLV is not included 1857*5113495bSYour Name <legal all> 1858*5113495bSYour Name */ 1859*5113495bSYour Name 1860*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 1861*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 1862*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 1863*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 1864*5113495bSYour Name 1865*5113495bSYour Name 1866*5113495bSYour Name /* Description RESERVED_7A 1867*5113495bSYour Name 1868*5113495bSYour Name Spare space in case the widths of the above offsets grow<legal 1869*5113495bSYour Name all> 1870*5113495bSYour Name */ 1871*5113495bSYour Name 1872*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 1873*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 1874*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 1875*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 1876*5113495bSYour Name 1877*5113495bSYour Name 1878*5113495bSYour Name /* Description RESERVED_8A 1879*5113495bSYour Name 1880*5113495bSYour Name Spare space in case the widths of the above offsets grow 1881*5113495bSYour Name 1882*5113495bSYour Name <legal all> 1883*5113495bSYour Name */ 1884*5113495bSYour Name 1885*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 1886*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 1887*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 1888*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff 1889*5113495bSYour Name 1890*5113495bSYour Name 1891*5113495bSYour Name /* Description RESERVED_9A 1892*5113495bSYour Name 1893*5113495bSYour Name Spare space in case the widths of the above offsets grow 1894*5113495bSYour Name 1895*5113495bSYour Name <legal all> 1896*5113495bSYour Name */ 1897*5113495bSYour Name 1898*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 1899*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 1900*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 1901*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 1902*5113495bSYour Name 1903*5113495bSYour Name 1904*5113495bSYour Name /* Description CORRUPTED_DUE_TO_FIFO_DELAY 1905*5113495bSYour Name 1906*5113495bSYour Name Set if Rx PCU avoided a hang due to SFM delays by writing 1907*5113495bSYour Name a corrupted 'RX_PPDU_END_USER_STATS' and/or 'RX_PPDU_END.' 1908*5113495bSYour Name 1909*5113495bSYour Name */ 1910*5113495bSYour Name 1911*5113495bSYour Name #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 1912*5113495bSYour Name #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 1913*5113495bSYour Name #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 1914*5113495bSYour Name #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 1915*5113495bSYour Name 1916*5113495bSYour Name 1917*5113495bSYour Name /* Description QOS_SN_1_MORE_FRAG_STATE 1918*5113495bSYour Name 1919*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1920*5113495bSYour Name 1921*5113495bSYour Name The 'more fragments' state of the QoS frames with TID QoS_SN_1_TID 1922*5113495bSYour Name at the end of this PPDU 1923*5113495bSYour Name <legal all> 1924*5113495bSYour Name */ 1925*5113495bSYour Name 1926*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1927*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 1928*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 1929*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 1930*5113495bSYour Name 1931*5113495bSYour Name 1932*5113495bSYour Name /* Description QOS_SN_1_FRAG_NUM_STATE 1933*5113495bSYour Name 1934*5113495bSYour Name Field only valid when QoS_SN_1_info_valid is set. 1935*5113495bSYour Name 1936*5113495bSYour Name The 'fragment number' state of the QoS frames with TID QoS_SN_1_TID 1937*5113495bSYour Name at the end of this PPDU 1938*5113495bSYour Name <legal all> 1939*5113495bSYour Name */ 1940*5113495bSYour Name 1941*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1942*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 1943*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 1944*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c 1945*5113495bSYour Name 1946*5113495bSYour Name 1947*5113495bSYour Name /* Description QOS_SN_2_MORE_FRAG_STATE 1948*5113495bSYour Name 1949*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1950*5113495bSYour Name 1951*5113495bSYour Name The 'more fragments' state of the QoS frames with TID QoS_SN_2_TID 1952*5113495bSYour Name at the end of this PPDU 1953*5113495bSYour Name <legal all> 1954*5113495bSYour Name */ 1955*5113495bSYour Name 1956*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1957*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 1958*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 1959*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 1960*5113495bSYour Name 1961*5113495bSYour Name 1962*5113495bSYour Name /* Description QOS_SN_2_FRAG_NUM_STATE 1963*5113495bSYour Name 1964*5113495bSYour Name Field only valid when QoS_SN_2_info_valid is set. 1965*5113495bSYour Name 1966*5113495bSYour Name The 'fragment number' state of the QoS frames with TID QoS_SN_2_TID 1967*5113495bSYour Name at the end of this PPDU 1968*5113495bSYour Name <legal all> 1969*5113495bSYour Name */ 1970*5113495bSYour Name 1971*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1972*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 1973*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 1974*5113495bSYour Name #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 1975*5113495bSYour Name 1976*5113495bSYour Name 1977*5113495bSYour Name /* Description RESERVED_26A 1978*5113495bSYour Name 1979*5113495bSYour Name <legal 0> 1980*5113495bSYour Name */ 1981*5113495bSYour Name 1982*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 1983*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 1984*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 1985*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 1986*5113495bSYour Name 1987*5113495bSYour Name 1988*5113495bSYour Name /* Description RX_PPDU_END_MARKER 1989*5113495bSYour Name 1990*5113495bSYour Name Field used by SW to double check that their structure alignment 1991*5113495bSYour Name is in sync with what HW has done. 1992*5113495bSYour Name <legal 0xAABBCCDD> 1993*5113495bSYour Name */ 1994*5113495bSYour Name 1995*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 1996*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 1997*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 1998*5113495bSYour Name #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 1999*5113495bSYour Name 2000*5113495bSYour Name 2001*5113495bSYour Name 2002*5113495bSYour Name #endif // RXPCU_PPDU_END_INFO 2003