1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RXPCU_PPDU_END_INFO_H_ 18 #define _RXPCU_PPDU_END_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phyrx_abort_request_info.h" 23 #include "macrx_abort_request_info.h" 24 #include "rxpcu_ppdu_end_layout_info.h" 25 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 26 27 #define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 28 29 30 struct rxpcu_ppdu_end_info { 31 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 32 uint32_t wb_timestamp_lower_32 : 32; // [31:0] 33 uint32_t wb_timestamp_upper_32 : 32; // [31:0] 34 uint32_t rx_antenna : 24, // [23:0] 35 tx_ht_vht_ack : 1, // [24:24] 36 unsupported_mu_nc : 1, // [25:25] 37 otp_txbf_disable : 1, // [26:26] 38 previous_tlv_corrupted : 1, // [27:27] 39 phyrx_abort_request_info_valid : 1, // [28:28] 40 macrx_abort_request_info_valid : 1, // [29:29] 41 reserved : 2; // [31:30] 42 uint32_t coex_bt_tx_from_start_of_rx : 1, // [0:0] 43 coex_bt_tx_after_start_of_rx : 1, // [1:1] 44 coex_wan_tx_from_start_of_rx : 1, // [2:2] 45 coex_wan_tx_after_start_of_rx : 1, // [3:3] 46 coex_wlan_tx_from_start_of_rx : 1, // [4:4] 47 coex_wlan_tx_after_start_of_rx : 1, // [5:5] 48 mpdu_delimiter_errors_seen : 1, // [6:6] 49 ftm_tm : 2, // [8:7] 50 dialog_token : 8, // [16:9] 51 follow_up_dialog_token : 8, // [24:17] 52 bb_captured_channel : 1, // [25:25] 53 bb_captured_reason : 3, // [28:26] 54 bb_captured_timeout : 1, // [29:29] 55 reserved_3 : 2; // [31:30] 56 uint32_t before_mpdu_count_passing_fcs : 10, // [9:0] 57 before_mpdu_count_failing_fcs : 10, // [19:10] 58 after_mpdu_count_passing_fcs : 10, // [29:20] 59 reserved_4 : 2; // [31:30] 60 uint32_t after_mpdu_count_failing_fcs : 10, // [9:0] 61 reserved_5 : 22; // [31:10] 62 uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] 63 uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] 64 uint32_t bb_length : 16, // [15:0] 65 bb_data : 1, // [16:16] 66 reserved_8 : 3, // [19:17] 67 first_bt_broadcast_status_details : 12; // [31:20] 68 uint32_t rx_ppdu_duration : 24, // [23:0] 69 reserved_9 : 8; // [31:24] 70 uint32_t ast_index : 16, // [15:0] 71 ast_index_valid : 1, // [16:16] 72 reserved_10 : 3, // [19:17] 73 second_bt_broadcast_status_details : 12; // [31:20] 74 struct phyrx_abort_request_info phyrx_abort_request_info_details; 75 struct macrx_abort_request_info macrx_abort_request_info_details; 76 uint16_t pre_bt_broadcast_status_details : 12, // [27:16] 77 reserved_12a : 4; // [31:28] 78 uint32_t non_qos_sn_info_valid : 1, // [0:0] 79 reserved_13a : 5, // [5:1] 80 non_qos_sn_highest : 12, // [17:6] 81 non_qos_sn_highest_retry_setting : 1, // [18:18] 82 non_qos_sn_lowest : 12, // [30:19] 83 non_qos_sn_lowest_retry_setting : 1; // [31:31] 84 uint32_t qos_sn_1_info_valid : 1, // [0:0] 85 reserved_14a : 1, // [1:1] 86 qos_sn_1_tid : 4, // [5:2] 87 qos_sn_1_highest : 12, // [17:6] 88 qos_sn_1_highest_retry_setting : 1, // [18:18] 89 qos_sn_1_lowest : 12, // [30:19] 90 qos_sn_1_lowest_retry_setting : 1; // [31:31] 91 uint32_t qos_sn_2_info_valid : 1, // [0:0] 92 reserved_15a : 1, // [1:1] 93 qos_sn_2_tid : 4, // [5:2] 94 qos_sn_2_highest : 12, // [17:6] 95 qos_sn_2_highest_retry_setting : 1, // [18:18] 96 qos_sn_2_lowest : 12, // [30:19] 97 qos_sn_2_lowest_retry_setting : 1; // [31:31] 98 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 99 uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] 100 qos_sn_1_more_frag_state : 1, // [1:1] 101 qos_sn_1_frag_num_state : 4, // [5:2] 102 qos_sn_2_more_frag_state : 1, // [6:6] 103 qos_sn_2_frag_num_state : 4, // [10:7] 104 reserved_26a : 21; // [31:11] 105 uint32_t rx_ppdu_end_marker : 32; // [31:0] 106 #else 107 uint32_t wb_timestamp_lower_32 : 32; // [31:0] 108 uint32_t wb_timestamp_upper_32 : 32; // [31:0] 109 uint32_t reserved : 2, // [31:30] 110 macrx_abort_request_info_valid : 1, // [29:29] 111 phyrx_abort_request_info_valid : 1, // [28:28] 112 previous_tlv_corrupted : 1, // [27:27] 113 otp_txbf_disable : 1, // [26:26] 114 unsupported_mu_nc : 1, // [25:25] 115 tx_ht_vht_ack : 1, // [24:24] 116 rx_antenna : 24; // [23:0] 117 uint32_t reserved_3 : 2, // [31:30] 118 bb_captured_timeout : 1, // [29:29] 119 bb_captured_reason : 3, // [28:26] 120 bb_captured_channel : 1, // [25:25] 121 follow_up_dialog_token : 8, // [24:17] 122 dialog_token : 8, // [16:9] 123 ftm_tm : 2, // [8:7] 124 mpdu_delimiter_errors_seen : 1, // [6:6] 125 coex_wlan_tx_after_start_of_rx : 1, // [5:5] 126 coex_wlan_tx_from_start_of_rx : 1, // [4:4] 127 coex_wan_tx_after_start_of_rx : 1, // [3:3] 128 coex_wan_tx_from_start_of_rx : 1, // [2:2] 129 coex_bt_tx_after_start_of_rx : 1, // [1:1] 130 coex_bt_tx_from_start_of_rx : 1; // [0:0] 131 uint32_t reserved_4 : 2, // [31:30] 132 after_mpdu_count_passing_fcs : 10, // [29:20] 133 before_mpdu_count_failing_fcs : 10, // [19:10] 134 before_mpdu_count_passing_fcs : 10; // [9:0] 135 uint32_t reserved_5 : 22, // [31:10] 136 after_mpdu_count_failing_fcs : 10; // [9:0] 137 uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] 138 uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] 139 uint32_t first_bt_broadcast_status_details : 12, // [31:20] 140 reserved_8 : 3, // [19:17] 141 bb_data : 1, // [16:16] 142 bb_length : 16; // [15:0] 143 uint32_t reserved_9 : 8, // [31:24] 144 rx_ppdu_duration : 24; // [23:0] 145 uint32_t second_bt_broadcast_status_details : 12, // [31:20] 146 reserved_10 : 3, // [19:17] 147 ast_index_valid : 1, // [16:16] 148 ast_index : 16; // [15:0] 149 struct phyrx_abort_request_info phyrx_abort_request_info_details; 150 uint32_t reserved_12a : 4, // [31:28] 151 pre_bt_broadcast_status_details : 12; // [27:16] 152 struct macrx_abort_request_info macrx_abort_request_info_details; 153 uint32_t non_qos_sn_lowest_retry_setting : 1, // [31:31] 154 non_qos_sn_lowest : 12, // [30:19] 155 non_qos_sn_highest_retry_setting : 1, // [18:18] 156 non_qos_sn_highest : 12, // [17:6] 157 reserved_13a : 5, // [5:1] 158 non_qos_sn_info_valid : 1; // [0:0] 159 uint32_t qos_sn_1_lowest_retry_setting : 1, // [31:31] 160 qos_sn_1_lowest : 12, // [30:19] 161 qos_sn_1_highest_retry_setting : 1, // [18:18] 162 qos_sn_1_highest : 12, // [17:6] 163 qos_sn_1_tid : 4, // [5:2] 164 reserved_14a : 1, // [1:1] 165 qos_sn_1_info_valid : 1; // [0:0] 166 uint32_t qos_sn_2_lowest_retry_setting : 1, // [31:31] 167 qos_sn_2_lowest : 12, // [30:19] 168 qos_sn_2_highest_retry_setting : 1, // [18:18] 169 qos_sn_2_highest : 12, // [17:6] 170 qos_sn_2_tid : 4, // [5:2] 171 reserved_15a : 1, // [1:1] 172 qos_sn_2_info_valid : 1; // [0:0] 173 struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; 174 uint32_t reserved_26a : 21, // [31:11] 175 qos_sn_2_frag_num_state : 4, // [10:7] 176 qos_sn_2_more_frag_state : 1, // [6:6] 177 qos_sn_1_frag_num_state : 4, // [5:2] 178 qos_sn_1_more_frag_state : 1, // [1:1] 179 corrupted_due_to_fifo_delay : 1; // [0:0] 180 uint32_t rx_ppdu_end_marker : 32; // [31:0] 181 #endif 182 }; 183 184 185 /* Description WB_TIMESTAMP_LOWER_32 186 187 WLAN/BT timestamp is a 1 usec resolution timestamp which 188 does not get updated based on receive beacon like TSF. 189 The same rules for capturing tsf_timestamp are used to 190 capture the wb_timestamp. This field represents the lower 191 32 bits of the 64-bit timestamp 192 */ 193 194 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 195 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 196 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 197 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff 198 199 200 /* Description WB_TIMESTAMP_UPPER_32 201 202 WLAN/BT timestamp is a 1 usec resolution timestamp which 203 does not get updated based on receive beacon like TSF. 204 The same rules for capturing tsf_timestamp are used to 205 capture the wb_timestamp. This field represents the upper 206 32 bits of the 64-bit timestamp 207 */ 208 209 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 210 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 211 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 212 #define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 213 214 215 /* Description RX_ANTENNA 216 217 Receive antenna value ??? 218 */ 219 220 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 221 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 222 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 223 #define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff 224 225 226 /* Description TX_HT_VHT_ACK 227 228 Indicates that a HT or VHT Ack/BA frame was transmitted 229 in response to this receive packet. 230 */ 231 232 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 233 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 234 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 235 #define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 236 237 238 239 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 240 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 241 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 242 #define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 243 244 245 /* Description OTP_TXBF_DISABLE 246 247 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 248 set and if RXPU receives directed NDPA frame. Then, RXPCU 249 should not send TX_EXPECT_NDP TLV to SW but set this bit 250 to inform SW. 251 */ 252 253 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 254 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 255 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 256 #define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 257 258 259 /* Description PREVIOUS_TLV_CORRUPTED 260 261 When set, the TLV preceding this RXPCU_END_INFO TLV within 262 the RX_PPDU_END TLV, is corrupted. Not the entire TLV was 263 received.... Likely due to an abort scenario... If abort 264 is to blame, see the abort data datastructure for details. 265 266 <legal all> 267 */ 268 269 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 270 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 271 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 272 #define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 273 274 275 /* Description PHYRX_ABORT_REQUEST_INFO_VALID 276 277 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to RXPCU. 278 The abort fields embedded in this TLV contain valid info. 279 280 <legal all> 281 */ 282 283 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 284 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 285 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 286 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 287 288 289 /* Description MACRX_ABORT_REQUEST_INFO_VALID 290 291 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to PHYRX. 292 The abort fields embedded in this TLV contain valid info. 293 294 <legal all> 295 */ 296 297 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 298 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 299 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 300 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 301 302 303 /* Description RESERVED 304 305 <legal 0> 306 */ 307 308 #define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 309 #define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 310 #define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 311 #define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 312 313 314 /* Description COEX_BT_TX_FROM_START_OF_RX 315 316 Set when BT TX was ongoing when WLAN RX started 317 */ 318 319 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 320 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 321 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 322 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 323 324 325 /* Description COEX_BT_TX_AFTER_START_OF_RX 326 327 Set when BT TX started while WLAN RX was already ongoing 328 329 */ 330 331 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 332 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 333 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 334 #define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 335 336 337 /* Description COEX_WAN_TX_FROM_START_OF_RX 338 339 Set when WAN TX was ongoing when WLAN RX started 340 */ 341 342 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 343 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 344 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 345 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 346 347 348 /* Description COEX_WAN_TX_AFTER_START_OF_RX 349 350 Set when WAN TX started while WLAN RX was already ongoing 351 352 */ 353 354 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 355 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 356 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 357 #define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 358 359 360 /* Description COEX_WLAN_TX_FROM_START_OF_RX 361 362 Set when other WLAN TX was ongoing when WLAN RX started 363 */ 364 365 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 366 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 367 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 368 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 369 370 371 /* Description COEX_WLAN_TX_AFTER_START_OF_RX 372 373 Set when other WLAN TX started while WLAN RX was already 374 ongoing 375 */ 376 377 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 378 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 379 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 380 #define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 381 382 383 /* Description MPDU_DELIMITER_ERRORS_SEEN 384 385 When set, MPDU delimiter errors have been detected during 386 this PPDU reception 387 */ 388 389 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 390 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 391 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 392 #define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 393 394 395 /* Description FTM_TM 396 397 Indicate the timestamp is for the FTM or TM frame 398 399 0: non TM or FTM frame 400 1: FTM frame 401 2: TM frame 402 3: reserved 403 <legal all> 404 */ 405 406 #define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 407 #define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 408 #define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 409 #define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 410 411 412 /* Description DIALOG_TOKEN 413 414 The dialog token in the FTM or TM frame. Only valid when 415 the FTM is set. Clear to 254 for a non-FTM frame 416 <legal all> 417 */ 418 419 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 420 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 421 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 422 #define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 423 424 425 /* Description FOLLOW_UP_DIALOG_TOKEN 426 427 The follow up dialog token in the FTM or TM frame. Only 428 valid when the FTM is set. Clear to 0 for a non-FTM frame, 429 The follow up dialog token in the FTM frame. Only valid 430 when the FTM is set. Clear to 255 for a non-FTM frame<legal 431 all> 432 */ 433 434 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 435 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 436 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 437 #define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 438 439 440 /* Description BB_CAPTURED_CHANNEL 441 442 Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is sent 443 to PHY, FW check it to correlate current PPDU TLVs with 444 uploaded channel information. 445 446 <legal all> 447 */ 448 449 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 450 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 451 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 452 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 453 454 455 /* Description BB_CAPTURED_REASON 456 457 Copy "capture_reason" of MACRX_FREEZE_CAPTURE_CHANNEL TLV 458 to here for FW usage. Valid when bb_captured_channel or 459 bb_captured_timeout is set. 460 461 This field indicates why the MAC asked to capture the channel 462 463 <enum 0 freeze_reason_TM> 464 <enum 1 freeze_reason_FTM> 465 <enum 2 freeze_reason_ACK_resp_to_TM_FTM> 466 <enum 3 freeze_reason_TA_RA_TYPE_FILTER> 467 <enum 4 freeze_reason_NDPA_NDP> 468 <enum 5 freeze_reason_ALL_PACKET> 469 470 <legal 0-5> 471 */ 472 473 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 474 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 475 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 476 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 477 478 479 /* Description BB_CAPTURED_TIMEOUT 480 481 Set by RxPCU to indicate channel capture condition is meet, 482 but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due 483 to AST long delay, which means the rx_frame_falling edge 484 to FREEZE TLV ready time exceed the threshold time defined 485 by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. 486 Bb_captured_reason is still valid in this case. 487 488 <legal all> 489 */ 490 491 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 492 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 493 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 494 #define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 495 496 497 /* Description RESERVED_3 498 499 <legal 0> 500 */ 501 502 #define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 503 #define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 504 #define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 505 #define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 506 507 508 /* Description BEFORE_MPDU_COUNT_PASSING_FCS 509 510 Number of MPDUs received in this PPDU that passed the FCS 511 check before the Coex TX started 512 513 The counter saturates at 0x3FF. 514 <legal all> 515 */ 516 517 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 518 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 519 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 520 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff 521 522 523 /* Description BEFORE_MPDU_COUNT_FAILING_FCS 524 525 Number of MPDUs received in this PPDU that failed the FCS 526 check before the Coex TX started 527 528 The counter saturates at 0x3FF. 529 <legal all> 530 */ 531 532 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 533 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 534 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 535 #define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 536 537 538 /* Description AFTER_MPDU_COUNT_PASSING_FCS 539 540 Number of MPDUs received in this PPDU that passed the FCS 541 check after the moment the Coex TX started 542 543 (Note: The partially received MPDU when the COEX tx start 544 event came in falls in the "after" category) 545 546 The counter saturates at 0x3FF. 547 <legal all> 548 */ 549 550 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 551 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 552 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 553 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 554 555 556 /* Description RESERVED_4 557 558 <legal 0> 559 */ 560 561 #define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 562 #define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 563 #define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 564 #define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 565 566 567 /* Description AFTER_MPDU_COUNT_FAILING_FCS 568 569 Number of MPDUs received in this PPDU that failed the FCS 570 check after the moment the Coex TX started 571 572 (Note: The partially received MPDU when the COEX tx start 573 event came in falls in the "after" category) 574 575 The counter saturates at 0x3FF. 576 <legal all> 577 */ 578 579 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 580 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 581 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 582 #define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 583 584 585 /* Description RESERVED_5 586 587 <legal 0> 588 */ 589 590 #define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 591 #define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 592 #define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 593 #define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 594 595 596 /* Description PHY_TIMESTAMP_TX_LOWER_32 597 598 The PHY timestamp in the AMPI of the most recent rising 599 edge (TODO: of what ???) after the TX_PHY_DESC. This field 600 indicates the lower 32 bits of the timestamp 601 */ 602 603 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 604 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 605 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 606 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff 607 608 609 /* Description PHY_TIMESTAMP_TX_UPPER_32 610 611 The PHY timestamp in the AMPI of the most recent rising 612 edge (TODO: of what ???) after the TX_PHY_DESC. This field 613 indicates the upper 32 bits of the timestamp 614 */ 615 616 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 617 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 618 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 619 #define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 620 621 622 /* Description BB_LENGTH 623 624 Indicates the number of bytes of baseband information for 625 PPDUs where the BB descriptor preamble type is 0x80 to 626 0xFF which indicates that this is not a normal PPDU but 627 rather contains baseband debug information. 628 TODO: Is this still needed ??? 629 */ 630 631 #define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 632 #define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 633 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 634 #define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff 635 636 637 638 #define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 639 #define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 640 #define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 641 #define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 642 643 644 /* Description RESERVED_8 645 646 Reserved: HW should fill with 0, FW should ignore. 647 */ 648 649 #define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 650 #define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 651 #define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 652 #define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 653 654 655 /* Description FIRST_BT_BROADCAST_STATUS_DETAILS 656 657 Same contents as field "bt_broadcast_status_details" for 658 the first received COEX_STATUS_BROADCAST tlv during this 659 PPDU reception. 660 661 If no COEX_STATUS_BROADCAST tlv is received during this 662 PPDU reception, this field will be set to 0 663 664 <legal all> 665 */ 666 667 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 668 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 669 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 670 #define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 671 672 673 /* Description RX_PPDU_DURATION 674 675 The length of this PPDU reception in us 676 */ 677 678 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 679 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 680 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 681 #define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 682 683 684 /* Description RESERVED_9 685 686 <legal 0> 687 */ 688 689 #define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 690 #define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 691 #define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 692 #define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 693 694 695 /* Description AST_INDEX 696 697 The AST index of the receive Ack/BA. This information is 698 provided from the TXPCU to the RXPCU for receive Ack/BA 699 for implicit beamforming. 700 <legal all> 701 */ 702 703 #define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 704 #define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 705 #define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 706 #define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff 707 708 709 /* Description AST_INDEX_VALID 710 711 Indicates that ast_index is valid. Should only be set for 712 receive Ack/BA where single stream implicit sounding is 713 captured. 714 */ 715 716 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 717 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 718 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 719 #define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 720 721 722 /* Description RESERVED_10 723 724 <legal 0> 725 */ 726 727 #define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 728 #define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 729 #define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 730 #define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 731 732 733 /* Description SECOND_BT_BROADCAST_STATUS_DETAILS 734 735 Same contents as field "bt_broadcast_status_details" for 736 the second received COEX_STATUS_BROADCAST tlv during this 737 PPDU reception. 738 739 If no second COEX_STATUS_BROADCAST tlv is received during 740 this PPDU reception, this field will be set to 0 741 742 <legal all> 743 */ 744 745 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 746 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 747 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 748 #define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 749 750 751 /* Description PHYRX_ABORT_REQUEST_INFO_DETAILS 752 753 Field only valid when Phyrx_abort_request_info_valid is 754 set 755 The reason why PHY generated an abort request 756 */ 757 758 759 /* Description PHYRX_ABORT_REASON 760 761 <enum 0 phyrx_err_phy_off> Reception aborted due to receiving 762 a PHY_OFF TLV 763 <enum 1 phyrx_err_synth_off> 764 <enum 2 phyrx_err_ofdma_timing> 765 <enum 3 phyrx_err_ofdma_signal_parity> 766 <enum 4 phyrx_err_ofdma_rate_illegal> 767 <enum 5 phyrx_err_ofdma_length_illegal> 768 <enum 6 phyrx_err_ofdma_restart> 769 <enum 7 phyrx_err_ofdma_service> 770 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 771 772 <enum 9 phyrx_err_cck_blokker> 773 <enum 10 phyrx_err_cck_timing> 774 <enum 11 phyrx_err_cck_header_crc> 775 <enum 12 phyrx_err_cck_rate_illegal> 776 <enum 13 phyrx_err_cck_length_illegal> 777 <enum 14 phyrx_err_cck_restart> 778 <enum 15 phyrx_err_cck_service> 779 <enum 16 phyrx_err_cck_power_drop> 780 781 <enum 17 phyrx_err_ht_crc_err> 782 <enum 18 phyrx_err_ht_length_illegal> 783 <enum 19 phyrx_err_ht_rate_illegal> 784 <enum 20 phyrx_err_ht_zlf> 785 <enum 21 phyrx_err_false_radar_ext> 786 <enum 22 phyrx_err_green_field> 787 <enum 60 phyrx_err_ht_nsym_lt_zero> 788 789 <enum 23 phyrx_err_bw_gt_dyn_bw> 790 <enum 24 phyrx_err_leg_ht_mismatch> 791 <enum 25 phyrx_err_vht_crc_error> 792 <enum 26 phyrx_err_vht_siga_unsupported> 793 <enum 27 phyrx_err_vht_lsig_len_invalid> 794 <enum 28 phyrx_err_vht_ndp_or_zlf> 795 <enum 29 phyrx_err_vht_nsym_lt_zero> 796 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 797 <enum 31 phyrx_err_vht_rx_skip_group_id0> 798 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 799 <enum 33 phyrx_err_vht_rx_skip_group_id63> 800 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 801 <enum 35 phyrx_err_defer_nap> 802 803 <enum 61 phyrx_err_vht_lsig_rate_mismatch> 804 <enum 62 phyrx_err_vht_paid_gid_mismatch> 805 <enum 63 phyrx_err_vht_unsupported_bw> 806 <enum 64 phyrx_err_vht_gi_disam_mismatch> 807 808 <enum 36 phyrx_err_fdomain_timeout> 809 <enum 37 phyrx_err_lsig_rel_check> 810 <enum 38 phyrx_err_bt_collision> 811 <enum 39 phyrx_err_unsupported_mu_feedback> 812 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 813 <enum 41 phyrx_err_unsupported_cbf> 814 815 <enum 42 phyrx_err_other> Should not really be used. If 816 needed, ask for documentation update 817 818 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error 819 > <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported 820 > <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 821 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 822 phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported 823 > 824 <enum 54 phyrx_err_he_sigb_crc_error> 825 <enum 55 phyrx_err_he_ext_su_unsupported> 826 <enum 56 phyrx_err_he_trig_unsupported> 827 <enum 57 phyrx_err_he_lsig_len_invalid> 828 <enum 58 phyrx_err_he_lsig_rate_mismatch> 829 <enum 59 phyrx_err_ofdma_signal_reliability> 830 831 <enum 77 phyrx_err_wur_detection> 832 833 <enum 72 phyrx_err_u_sig_crc_error> 834 <enum 73 phyrx_err_u_sig_unsupported_mode> 835 <enum 74 phyrx_err_u_sig_rsvd_err> 836 <enum 75 phyrx_err_u_sig_mcs_error> 837 <enum 76 phyrx_err_u_sig_bw_error> 838 <enum 79 phyrx_err_u_sig_320_channel_mismatch> 839 <enum 71 phyrx_err_eht_sig_crc_error> 840 <enum 78 phyrx_err_eht_sig_unsupported_mode> 841 842 <enum 80 phyrx_err_ehtplus_er_detection> 843 844 <enum 52 phyrx_err_MU_UL_no_power_detected> 845 <enum 53 phyrx_err_MU_UL_not_for_me> 846 847 <enum 65 phyrx_err_rx_wdg_timeout> 848 <enum 66 phyrx_err_sizing_evt_unexpected> 849 <enum 67 phyrx_err_spectralscan> 850 <enum 68 phyrx_err_radar_misdetected_as_ofdm> 851 <enum 69 phyrx_err_rx_stuck> 852 <enum 70 phyrx_err_invalid_11b_state> 853 854 <legal 0 - 80> 855 */ 856 857 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 858 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 859 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 860 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 861 862 863 /* Description PHY_ENTERS_NAP_STATE 864 865 When set, PHY enters PHY NAP state after sending this abort 866 867 868 Note that nap and defer state are mutually exclusive. 869 870 Field put pro-actively in place....usage still to be agreed 871 upon. 872 <legal all> 873 */ 874 875 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 876 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 877 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 878 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 879 880 881 /* Description PHY_ENTERS_DEFER_STATE 882 883 When set, PHY enters PHY defer state after sending this 884 abort 885 886 Note that nap and defer state are mutually exclusive. 887 888 Field put pro-actively in place....usage still to be agreed 889 upon. 890 <legal all> 891 */ 892 893 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 894 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 895 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 896 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 897 898 899 /* Description RESERVED_0 900 901 <legal 0> 902 */ 903 904 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 905 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 906 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 907 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 908 909 910 /* Description RECEIVE_DURATION 911 912 The remaining receive duration of this PPDU in the medium 913 (in us). When PHY does not know this duration when this 914 TLV is generated, the field will be set to 0. 915 The timing reference point is the reception by the MAC of 916 this TLV. The value shall be accurate to within 2us. 917 918 In case Phy_enters_nap_state and/or Phy_enters_defer_state 919 is set, there is a possibility that MAC PMM can also decide 920 to go into a low(er) power state. 921 <legal all> 922 */ 923 924 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 925 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 926 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 927 #define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 928 929 930 /* Description MACRX_ABORT_REQUEST_INFO_DETAILS 931 932 Field only valid when macrx_abort_request_info_valid is 933 set 934 The reason why MACRX generated an abort request 935 */ 936 937 938 /* Description MACRX_ABORT_REASON 939 940 <enum 0 macrx_abort_sw_initiated> 941 <enum 1 macrx_abort_obss_reception> Upon receiving this 942 abort reason, PHY should stop reception of the current frame 943 and go back into a search mode 944 <enum 2 macrx_abort_other> 945 <enum 3 macrx_abort_sw_initiated_channel_switch> MAC FW 946 issued an abort for channel switch reasons 947 <enum 4 macrx_abort_sw_initiated_power_save> MAC FW issued 948 an abort power save reasons 949 <enum 5 macrx_abort_too_much_bad_data> RXPCU is terminating 950 the current ongoing reception, as the data that MAC is 951 receiving seems to be all garbage... The PER is too high, 952 or in case of MU UL, Likely the trigger frame never got 953 properly received by any of the targeted MU UL devices. 954 After the abort, PHYRX can resume a normal search mode. 955 <enum 6 macrx_abort_ul_mu_early_abort> RXPCU is terminating 956 the current ongoing UL MU reception, because at the end 957 of the "early_termination_window," the required number 958 of users with at least one valid MPDU delimiter was not 959 reached. Likely the trigger frame never got properly received 960 by the required number of targeted devices. After the abort, 961 PHYRX can resume a normal search mode. 962 963 <legal 0-6> 964 */ 965 966 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 967 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 968 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 969 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff 970 971 972 /* Description RESERVED_0 973 974 <legal 0> 975 */ 976 977 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 978 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 979 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 980 #define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 981 982 983 /* Description PRE_BT_BROADCAST_STATUS_DETAILS 984 985 Same contents as field "bt_broadcast_status_details" of 986 the last received COEX_STATUS_BROADCAST tlv before this 987 PPDU reception. 988 After power up, this field is all initialized to 0 989 990 <legal all> 991 */ 992 993 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 994 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 995 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 996 #define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 997 998 999 /* Description RESERVED_12A 1000 1001 Bits: [27:16] 1002 Same contents as field "bt_broadcast_status_details" of 1003 the last received COEX_STATUS_BROADCAST tlv before this 1004 PPDU reception. 1005 After power up, this field is all initialized to 0 1006 1007 Bits: [31:28]: always 0 1008 1009 1010 For detailed info see doc: TBD 1011 <legal all> 1012 */ 1013 1014 #define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 1015 #define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 1016 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 1017 #define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 1018 1019 1020 /* Description NON_QOS_SN_INFO_VALID 1021 1022 When set, the non_QoS_SN_... fields contain valid info. 1023 1024 This field will ONLY be set upon the very first reception 1025 of a non QoS frame. 1026 1027 <legal all> 1028 */ 1029 1030 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 1031 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 1032 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 1033 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 1034 1035 1036 /* Description RESERVED_13A 1037 1038 <legal 0> 1039 */ 1040 1041 #define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 1042 #define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 1043 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 1044 #define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 1045 1046 1047 /* Description NON_QOS_SN_HIGHEST 1048 1049 Field only valid when non_QoS_SN_info_valid is set 1050 1051 Lowest and highest are defined based on a 2K window. 1052 When only 1 non-QoS frame is received, the 'highest' and 1053 'lowest' fields will have the same values. 1054 1055 The highest MPDU sequence number for a non-QoS frame received 1056 in this PPDU 1057 <legal all> 1058 */ 1059 1060 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 1061 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 1062 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 1063 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 1064 1065 1066 /* Description NON_QOS_SN_HIGHEST_RETRY_SETTING 1067 1068 Field only valid when non_QoS_SN_info_valid is set 1069 1070 The 'retry' bit setting of the highest MPDU sequence number 1071 non-QOS frame received in this PPDU 1072 <legal all> 1073 */ 1074 1075 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 1076 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 1077 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 1078 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 1079 1080 1081 /* Description NON_QOS_SN_LOWEST 1082 1083 Field only valid when non_QoS_SN_info_valid is set 1084 1085 Lowest and highest are defined based on a 2K window. 1086 When only 1 non-QoS frame is received, the 'highest' and 1087 'lowest' fields will have the same values. 1088 1089 The lowest MPDU sequence number for a non-QoS frame received 1090 in this PPDU 1091 <legal all> 1092 */ 1093 1094 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 1095 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 1096 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 1097 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 1098 1099 1100 /* Description NON_QOS_SN_LOWEST_RETRY_SETTING 1101 1102 Field only valid when non_QoS_SN_info_valid is set 1103 1104 The 'retry' bit setting of the lowest MPDU sequence number 1105 non-QoS frame received in this PPDU 1106 <legal all> 1107 */ 1108 1109 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 1110 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 1111 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 1112 #define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 1113 1114 1115 /* Description QOS_SN_1_INFO_VALID 1116 1117 When set, the QoS_SN_1_... fields contain valid info. 1118 1119 This field will ONLY be set upon the very first reception 1120 of a QoS frame. 1121 1122 <legal all> 1123 */ 1124 1125 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 1126 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 1127 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 1128 #define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 1129 1130 1131 /* Description RESERVED_14A 1132 1133 <legal 0> 1134 */ 1135 1136 #define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 1137 #define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 1138 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 1139 #define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 1140 1141 1142 /* Description QOS_SN_1_TID 1143 1144 Field only valid when QoS_SN_1_info_valid is set. 1145 1146 The TID of the frames related to the QoS_SN_1_... fields 1147 1148 <legal all> 1149 */ 1150 1151 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 1152 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 1153 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 1154 #define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c 1155 1156 1157 /* Description QOS_SN_1_HIGHEST 1158 1159 Field only valid when QoS_SN_1_info_valid is set. 1160 1161 Lowest and highest are defined based on a 2K window. 1162 When only 1 QoS frame of the relevant TID is received, the 1163 'highest' and 'lowest' fields will have the same values. 1164 1165 1166 The highest MPDU sequence number for a QoS frame with TID 1167 QoS_SN_1_TID received in this PPDU 1168 <legal all> 1169 */ 1170 1171 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 1172 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 1173 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 1174 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 1175 1176 1177 /* Description QOS_SN_1_HIGHEST_RETRY_SETTING 1178 1179 Field only valid when QoS_SN_1_info_valid is set. 1180 1181 The 'retry' bit setting of the highest MPDU sequence number 1182 QoS frame with TID QoS_SN_1_TID received in this PPDU 1183 <legal all> 1184 */ 1185 1186 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 1187 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 1188 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 1189 #define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 1190 1191 1192 /* Description QOS_SN_1_LOWEST 1193 1194 Field only valid when QoS_SN_1_info_valid is set. 1195 1196 Lowest and highest are defined based on a 2K window. 1197 When only 1 QoS frame of the relevant TID is received, the 1198 'highest' and 'lowest' fields will have the same values. 1199 1200 1201 The lowest MPDU sequence number for a QoS frame with TID 1202 QoS_SN_1_TID received in this PPDU 1203 <legal all> 1204 */ 1205 1206 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 1207 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 1208 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 1209 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 1210 1211 1212 /* Description QOS_SN_1_LOWEST_RETRY_SETTING 1213 1214 Field only valid when QoS_SN_1_info_valid is set. 1215 1216 The 'retry' bit setting of the lowest MPDU sequence number 1217 QoS frame with TID QoS_SN_1_TID received in this PPDU 1218 <legal all> 1219 */ 1220 1221 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 1222 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 1223 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 1224 #define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 1225 1226 1227 /* Description QOS_SN_2_INFO_VALID 1228 1229 When set, the QoS_SN_2_... fields contain valid info. 1230 1231 This field can ONLY be set in case of a multi-TID PPDU reception. 1232 This field is set upon the very first reception of a QoS 1233 frame belonging to the second TID in the PPDU. 1234 1235 <legal all> 1236 */ 1237 1238 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 1239 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 1240 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 1241 #define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 1242 1243 1244 /* Description RESERVED_15A 1245 1246 <legal 0> 1247 */ 1248 1249 #define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 1250 #define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 1251 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 1252 #define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 1253 1254 1255 /* Description QOS_SN_2_TID 1256 1257 Field only valid when QoS_SN_2_info_valid is set. 1258 1259 The TID of the frames related to the QoS_SN_2_... fields 1260 1261 <legal all> 1262 */ 1263 1264 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 1265 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 1266 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 1267 #define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 1268 1269 1270 /* Description QOS_SN_2_HIGHEST 1271 1272 Field only valid when QoS_SN_2_info_valid is set. 1273 1274 Lowest and highest are defined based on a 2K window. 1275 When only 1 QoS frame of the relevant TID is received, the 1276 highest and lowest fields will have the same values. 1277 1278 The highest MPDU sequence number for a QoS frame with TID 1279 QoS_SN_2_TID received in this PPDU 1280 <legal all> 1281 */ 1282 1283 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 1284 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 1285 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 1286 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 1287 1288 1289 /* Description QOS_SN_2_HIGHEST_RETRY_SETTING 1290 1291 Field only valid when QoS_SN_2_info_valid is set. 1292 1293 The 'retry' bit setting of the highest MPDU sequence number 1294 QoS frame with TID QoS_SN_2_TID received in this PPDU 1295 <legal all> 1296 */ 1297 1298 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 1299 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 1300 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 1301 #define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 1302 1303 1304 /* Description QOS_SN_2_LOWEST 1305 1306 Field only valid when QoS_SN_2_info_valid is set. 1307 1308 Lowest and highest are defined based on a 2K window. 1309 When only 1 QoS frame of the relevant TID is received, the 1310 highest and lowest fields will have the same values. 1311 1312 The lowest MPDU sequence number for a QoS frame with TID 1313 QoS_SN_2_TID received in this PPDU 1314 <legal all> 1315 */ 1316 1317 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 1318 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 1319 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 1320 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 1321 1322 1323 /* Description QOS_SN_2_LOWEST_RETRY_SETTING 1324 1325 Field only valid when QoS_SN_2_info_valid is set. 1326 1327 The 'retry' bit setting of the lowest MPDU sequence number 1328 QoS frame with TID QoS_SN_2_TID received in this PPDU 1329 <legal all> 1330 */ 1331 1332 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 1333 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 1334 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 1335 #define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 1336 1337 1338 /* Description RXPCU_PPDU_END_LAYOUT_DETAILS 1339 1340 Structure containing the relative offsets of preamble TLVs 1341 within 'RX_PPDU_END' documenting the layout within 'RX_PPDU_END' 1342 1343 */ 1344 1345 1346 /* Description RSSI_LEGACY_OFFSET 1347 1348 Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within 1349 'RX_PPDU_END'<legal 1, 2> 1350 */ 1351 1352 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 1353 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 1354 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 1355 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 1356 1357 1358 /* Description L_SIG_A_OFFSET 1359 1360 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 1361 Set to zero if the TLV is not included<legal 0, 44, 46> 1362 */ 1363 1364 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 1365 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 1366 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 1367 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc 1368 1369 1370 /* Description L_SIG_B_OFFSET 1371 1372 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 1373 Set to zero if the TLV is not included<legal 0, 44, 46> 1374 */ 1375 1376 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 1377 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 1378 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 1379 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 1380 1381 1382 /* Description HT_SIG_OFFSET 1383 1384 Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero 1385 if the TLV is not included<legal 0, 46, 50> 1386 */ 1387 1388 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 1389 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 1390 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 1391 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 1392 1393 1394 /* Description VHT_SIG_A_OFFSET 1395 1396 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' 1397 Set to zero if the TLV is not included<legal 0, 46, 50> 1398 */ 1399 1400 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 1401 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 1402 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 1403 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 1404 1405 1406 /* Description REPEAT_L_SIG_A_OFFSET 1407 1408 Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in 1409 HE and EHT cases) within 'RX_PPDU_END' 1410 1411 Set to zero if the TLV is not included 1412 <legal 0, 46, 50> 1413 */ 1414 1415 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 1416 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 1417 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 1418 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 1419 1420 1421 /* Description HE_SIG_A_SU_OFFSET 1422 1423 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within 1424 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1425 0, 48, 54> 1426 */ 1427 1428 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 1429 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 1430 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 1431 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 1432 1433 1434 /* Description HE_SIG_A_MU_DL_OFFSET 1435 1436 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within 1437 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1438 0, 48, 54> 1439 */ 1440 1441 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 1442 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 1443 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 1444 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 1445 1446 1447 /* Description HE_SIG_A_MU_UL_OFFSET 1448 1449 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within 1450 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1451 0, 48, 54> 1452 */ 1453 1454 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 1455 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 1456 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 1457 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 1458 1459 1460 /* Description GENERIC_U_SIG_OFFSET 1461 1462 Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within 1463 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1464 0, 48, 54> 1465 */ 1466 1467 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 1468 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 1469 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 1470 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 1471 1472 1473 /* Description RSSI_HT_OFFSET 1474 1475 Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' 1476 Set to zero if the TLV is not included<legal 0, 49-127> 1477 */ 1478 1479 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 1480 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 1481 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 1482 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 1483 1484 1485 /* Description RESERVED_1A 1486 1487 <legal 0> 1488 */ 1489 1490 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 1491 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 1492 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 1493 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 1494 1495 1496 /* Description VHT_SIG_B_SU20_OFFSET 1497 1498 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within 1499 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1500 0, 67, 74> 1501 */ 1502 1503 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 1504 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 1505 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 1506 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f 1507 1508 1509 /* Description VHT_SIG_B_SU40_OFFSET 1510 1511 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within 1512 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1513 0, 67, 74> 1514 */ 1515 1516 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 1517 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 1518 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 1519 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 1520 1521 1522 /* Description VHT_SIG_B_SU80_OFFSET 1523 1524 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within 1525 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1526 0, 67, 74> 1527 */ 1528 1529 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 1530 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 1531 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 1532 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 1533 1534 1535 /* Description VHT_SIG_B_SU160_OFFSET 1536 1537 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within 1538 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1539 0, 67, 74> 1540 */ 1541 1542 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 1543 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 1544 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 1545 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 1546 1547 1548 /* Description RESERVED_2A 1549 1550 <legal 0> 1551 */ 1552 1553 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 1554 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 1555 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 1556 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 1557 1558 1559 /* Description VHT_SIG_B_MU20_OFFSET 1560 1561 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within 1562 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1563 0, 67, 74> 1564 */ 1565 1566 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 1567 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 1568 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 1569 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 1570 1571 1572 /* Description VHT_SIG_B_MU40_OFFSET 1573 1574 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within 1575 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1576 0, 67, 74> 1577 */ 1578 1579 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 1580 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 1581 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 1582 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 1583 1584 1585 /* Description VHT_SIG_B_MU80_OFFSET 1586 1587 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within 1588 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1589 0, 67, 74> 1590 */ 1591 1592 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 1593 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 1594 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 1595 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 1596 1597 1598 /* Description VHT_SIG_B_MU160_OFFSET 1599 1600 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within 1601 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1602 0, 67, 74> 1603 */ 1604 1605 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 1606 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 1607 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 1608 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 1609 1610 1611 /* Description RESERVED_3A 1612 1613 <legal 0> 1614 */ 1615 1616 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 1617 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 1618 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 1619 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 1620 1621 1622 /* Description HE_SIG_B1_MU_OFFSET 1623 1624 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within 1625 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1626 0, 51, 58> 1627 */ 1628 1629 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 1630 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 1631 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 1632 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f 1633 1634 1635 /* Description HE_SIG_B2_MU_OFFSET 1636 1637 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within 1638 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1639 0, 51, 58> 1640 */ 1641 1642 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 1643 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 1644 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 1645 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 1646 1647 1648 /* Description HE_SIG_B2_OFDMA_OFFSET 1649 1650 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within 1651 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1652 0, 53, 62> 1653 */ 1654 1655 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 1656 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 1657 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 1658 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 1659 1660 1661 /* Description FIRST_GENERIC_EHT_SIG_OFFSET 1662 1663 Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' 1664 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1665 0, 51, 58> 1666 */ 1667 1668 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 1669 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 1670 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 1671 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 1672 1673 1674 /* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED 1675 1676 Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs 1677 are included in 'RX_PPDU_END,' set to zero otherwise 1678 <legal all> 1679 */ 1680 1681 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 1682 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 1683 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 1684 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 1685 1686 1687 /* Description RESERVED_4A 1688 1689 <legal 0> 1690 */ 1691 1692 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 1693 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 1694 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 1695 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 1696 1697 1698 /* Description COMMON_USER_INFO_OFFSET 1699 1700 Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within 1701 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1702 0, 46, 50, 67, 70-127> 1703 */ 1704 1705 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 1706 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 1707 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 1708 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 1709 1710 1711 /* Description FIRST_DEBUG_INFO_OFFSET 1712 1713 Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' 1714 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1715 all> 1716 */ 1717 1718 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 1719 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 1720 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 1721 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 1722 1723 1724 /* Description MULTIPLE_DEBUG_INFO_INCLUDED 1725 1726 Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are 1727 included in 'RX_PPDU_END,' set to zero otherwise<legal all> 1728 1729 */ 1730 1731 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 1732 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 1733 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 1734 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 1735 1736 1737 /* Description FIRST_OTHER_RECEIVE_INFO_OFFSET 1738 1739 Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' 1740 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1741 all> 1742 */ 1743 1744 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 1745 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 1746 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 1747 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 1748 1749 1750 /* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED 1751 1752 Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs 1753 are included in 'RX_PPDU_END,' set to zero otherwise<legal 1754 all> 1755 */ 1756 1757 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 1758 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 1759 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 1760 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 1761 1762 1763 /* Description RESERVED_5A 1764 1765 <legal 0> 1766 */ 1767 1768 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 1769 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 1770 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 1771 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 1772 1773 1774 /* Description DATA_DONE_OFFSET 1775 1776 Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' 1777 Set to zero if the TLV is not included<legal all> 1778 */ 1779 1780 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 1781 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 1782 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 1783 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff 1784 1785 1786 /* Description GENERATED_CBF_DETAILS_OFFSET 1787 1788 Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' 1789 within 'RX_PPDU_END'Set to zero if the TLV is not included<legal 1790 0, 70-127> 1791 */ 1792 1793 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 1794 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 1795 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 1796 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 1797 1798 1799 /* Description PKT_END_PART1_OFFSET 1800 1801 Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within 1802 'RX_PPDU_END' Set to zero if the TLV is not included<legal 1803 all> 1804 */ 1805 1806 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 1807 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 1808 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 1809 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 1810 1811 1812 /* Description LOCATION_OFFSET 1813 1814 Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' 1815 Set to zero if the TLV is not included<legal all> 1816 */ 1817 1818 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 1819 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 1820 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 1821 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 1822 1823 1824 /* Description AZ_INTEGRITY_DATA_OFFSET 1825 1826 Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' 1827 within 'RX_PPDU_END' 1828 1829 Set to zero if the TLV is not included 1830 <legal all> 1831 */ 1832 1833 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 1834 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 1835 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 1836 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 1837 1838 1839 /* Description PKT_END_OFFSET 1840 1841 Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' 1842 Set to zero if the TLV is not included<legal all> 1843 */ 1844 1845 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 1846 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 1847 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 1848 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 1849 1850 1851 /* Description ABORT_REQUEST_ACK_OFFSET 1852 1853 Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' 1854 or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' 1855 1856 Set to zero if the TLV is not included 1857 <legal all> 1858 */ 1859 1860 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 1861 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 1862 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 1863 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 1864 1865 1866 /* Description RESERVED_7A 1867 1868 Spare space in case the widths of the above offsets grow<legal 1869 all> 1870 */ 1871 1872 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 1873 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 1874 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 1875 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 1876 1877 1878 /* Description RESERVED_8A 1879 1880 Spare space in case the widths of the above offsets grow 1881 1882 <legal all> 1883 */ 1884 1885 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 1886 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 1887 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 1888 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff 1889 1890 1891 /* Description RESERVED_9A 1892 1893 Spare space in case the widths of the above offsets grow 1894 1895 <legal all> 1896 */ 1897 1898 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 1899 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 1900 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 1901 #define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 1902 1903 1904 /* Description CORRUPTED_DUE_TO_FIFO_DELAY 1905 1906 Set if Rx PCU avoided a hang due to SFM delays by writing 1907 a corrupted 'RX_PPDU_END_USER_STATS' and/or 'RX_PPDU_END.' 1908 1909 */ 1910 1911 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 1912 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 1913 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 1914 #define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 1915 1916 1917 /* Description QOS_SN_1_MORE_FRAG_STATE 1918 1919 Field only valid when QoS_SN_1_info_valid is set. 1920 1921 The 'more fragments' state of the QoS frames with TID QoS_SN_1_TID 1922 at the end of this PPDU 1923 <legal all> 1924 */ 1925 1926 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1927 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 1928 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 1929 #define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 1930 1931 1932 /* Description QOS_SN_1_FRAG_NUM_STATE 1933 1934 Field only valid when QoS_SN_1_info_valid is set. 1935 1936 The 'fragment number' state of the QoS frames with TID QoS_SN_1_TID 1937 at the end of this PPDU 1938 <legal all> 1939 */ 1940 1941 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1942 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 1943 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 1944 #define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c 1945 1946 1947 /* Description QOS_SN_2_MORE_FRAG_STATE 1948 1949 Field only valid when QoS_SN_2_info_valid is set. 1950 1951 The 'more fragments' state of the QoS frames with TID QoS_SN_2_TID 1952 at the end of this PPDU 1953 <legal all> 1954 */ 1955 1956 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 1957 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 1958 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 1959 #define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 1960 1961 1962 /* Description QOS_SN_2_FRAG_NUM_STATE 1963 1964 Field only valid when QoS_SN_2_info_valid is set. 1965 1966 The 'fragment number' state of the QoS frames with TID QoS_SN_2_TID 1967 at the end of this PPDU 1968 <legal all> 1969 */ 1970 1971 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 1972 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 1973 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 1974 #define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 1975 1976 1977 /* Description RESERVED_26A 1978 1979 <legal 0> 1980 */ 1981 1982 #define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 1983 #define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 1984 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 1985 #define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 1986 1987 1988 /* Description RX_PPDU_END_MARKER 1989 1990 Field used by SW to double check that their structure alignment 1991 is in sync with what HW has done. 1992 <legal 0xAABBCCDD> 1993 */ 1994 1995 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 1996 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 1997 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 1998 #define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 1999 2000 2001 2002 #endif // RXPCU_PPDU_END_INFO 2003