1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ 18 #define _RXPCU_PPDU_END_LAYOUT_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 23 24 25 struct rxpcu_ppdu_end_layout_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t rssi_legacy_offset : 2, // [1:0] 28 l_sig_a_offset : 6, // [7:2] 29 l_sig_b_offset : 6, // [13:8] 30 ht_sig_offset : 6, // [19:14] 31 vht_sig_a_offset : 6, // [25:20] 32 repeat_l_sig_a_offset : 6; // [31:26] 33 uint32_t he_sig_a_su_offset : 6, // [5:0] 34 he_sig_a_mu_dl_offset : 6, // [11:6] 35 he_sig_a_mu_ul_offset : 6, // [17:12] 36 generic_u_sig_offset : 6, // [23:18] 37 rssi_ht_offset : 7, // [30:24] 38 reserved_1a : 1; // [31:31] 39 uint32_t vht_sig_b_su20_offset : 7, // [6:0] 40 vht_sig_b_su40_offset : 7, // [13:7] 41 vht_sig_b_su80_offset : 7, // [20:14] 42 vht_sig_b_su160_offset : 7, // [27:21] 43 reserved_2a : 4; // [31:28] 44 uint32_t vht_sig_b_mu20_offset : 7, // [6:0] 45 vht_sig_b_mu40_offset : 7, // [13:7] 46 vht_sig_b_mu80_offset : 7, // [20:14] 47 vht_sig_b_mu160_offset : 7, // [27:21] 48 reserved_3a : 4; // [31:28] 49 uint32_t he_sig_b1_mu_offset : 7, // [6:0] 50 he_sig_b2_mu_offset : 7, // [13:7] 51 he_sig_b2_ofdma_offset : 7, // [20:14] 52 first_generic_eht_sig_offset : 7, // [27:21] 53 multiple_generic_eht_sig_included : 1, // [28:28] 54 reserved_4a : 3; // [31:29] 55 uint32_t common_user_info_offset : 7, // [6:0] 56 first_debug_info_offset : 8, // [14:7] 57 multiple_debug_info_included : 1, // [15:15] 58 first_other_receive_info_offset : 8, // [23:16] 59 multiple_other_receive_info_included : 1, // [24:24] 60 reserved_5a : 7; // [31:25] 61 uint32_t data_done_offset : 8, // [7:0] 62 generated_cbf_details_offset : 8, // [15:8] 63 pkt_end_part1_offset : 8, // [23:16] 64 location_offset : 8; // [31:24] 65 uint32_t az_integrity_data_offset : 8, // [7:0] 66 pkt_end_offset : 8, // [15:8] 67 abort_request_ack_offset : 8, // [23:16] 68 reserved_7a : 8; // [31:24] 69 uint32_t reserved_8a : 32; // [31:0] 70 uint32_t reserved_9a : 32; // [31:0] 71 #else 72 uint32_t repeat_l_sig_a_offset : 6, // [31:26] 73 vht_sig_a_offset : 6, // [25:20] 74 ht_sig_offset : 6, // [19:14] 75 l_sig_b_offset : 6, // [13:8] 76 l_sig_a_offset : 6, // [7:2] 77 rssi_legacy_offset : 2; // [1:0] 78 uint32_t reserved_1a : 1, // [31:31] 79 rssi_ht_offset : 7, // [30:24] 80 generic_u_sig_offset : 6, // [23:18] 81 he_sig_a_mu_ul_offset : 6, // [17:12] 82 he_sig_a_mu_dl_offset : 6, // [11:6] 83 he_sig_a_su_offset : 6; // [5:0] 84 uint32_t reserved_2a : 4, // [31:28] 85 vht_sig_b_su160_offset : 7, // [27:21] 86 vht_sig_b_su80_offset : 7, // [20:14] 87 vht_sig_b_su40_offset : 7, // [13:7] 88 vht_sig_b_su20_offset : 7; // [6:0] 89 uint32_t reserved_3a : 4, // [31:28] 90 vht_sig_b_mu160_offset : 7, // [27:21] 91 vht_sig_b_mu80_offset : 7, // [20:14] 92 vht_sig_b_mu40_offset : 7, // [13:7] 93 vht_sig_b_mu20_offset : 7; // [6:0] 94 uint32_t reserved_4a : 3, // [31:29] 95 multiple_generic_eht_sig_included : 1, // [28:28] 96 first_generic_eht_sig_offset : 7, // [27:21] 97 he_sig_b2_ofdma_offset : 7, // [20:14] 98 he_sig_b2_mu_offset : 7, // [13:7] 99 he_sig_b1_mu_offset : 7; // [6:0] 100 uint32_t reserved_5a : 7, // [31:25] 101 multiple_other_receive_info_included : 1, // [24:24] 102 first_other_receive_info_offset : 8, // [23:16] 103 multiple_debug_info_included : 1, // [15:15] 104 first_debug_info_offset : 8, // [14:7] 105 common_user_info_offset : 7; // [6:0] 106 uint32_t location_offset : 8, // [31:24] 107 pkt_end_part1_offset : 8, // [23:16] 108 generated_cbf_details_offset : 8, // [15:8] 109 data_done_offset : 8; // [7:0] 110 uint32_t reserved_7a : 8, // [31:24] 111 abort_request_ack_offset : 8, // [23:16] 112 pkt_end_offset : 8, // [15:8] 113 az_integrity_data_offset : 8; // [7:0] 114 uint32_t reserved_8a : 32; // [31:0] 115 uint32_t reserved_9a : 32; // [31:0] 116 #endif 117 }; 118 119 120 /* Description RSSI_LEGACY_OFFSET 121 122 Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within 123 'RX_PPDU_END'<legal 1, 2> 124 */ 125 126 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 127 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 128 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 129 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 130 131 132 /* Description L_SIG_A_OFFSET 133 134 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 135 Set to zero if the TLV is not included<legal 0, 44, 46> 136 */ 137 138 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 139 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 140 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 141 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc 142 143 144 /* Description L_SIG_B_OFFSET 145 146 Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' 147 Set to zero if the TLV is not included<legal 0, 44, 46> 148 */ 149 150 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 151 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 152 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 153 #define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 154 155 156 /* Description HT_SIG_OFFSET 157 158 Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero 159 if the TLV is not included<legal 0, 46, 50> 160 */ 161 162 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 163 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 164 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 165 #define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 166 167 168 /* Description VHT_SIG_A_OFFSET 169 170 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' 171 Set to zero if the TLV is not included<legal 0, 46, 50> 172 */ 173 174 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 175 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 176 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 177 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 178 179 180 /* Description REPEAT_L_SIG_A_OFFSET 181 182 Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in 183 HE and EHT cases) within 'RX_PPDU_END' 184 185 Set to zero if the TLV is not included 186 <legal 0, 46, 50> 187 */ 188 189 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 190 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 191 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 192 #define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 193 194 195 /* Description HE_SIG_A_SU_OFFSET 196 197 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within 198 'RX_PPDU_END' Set to zero if the TLV is not included<legal 199 0, 48, 54> 200 */ 201 202 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 203 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 204 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 205 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f 206 207 208 /* Description HE_SIG_A_MU_DL_OFFSET 209 210 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within 211 'RX_PPDU_END' Set to zero if the TLV is not included<legal 212 0, 48, 54> 213 */ 214 215 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 216 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 217 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 218 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 219 220 221 /* Description HE_SIG_A_MU_UL_OFFSET 222 223 Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within 224 'RX_PPDU_END' Set to zero if the TLV is not included<legal 225 0, 48, 54> 226 */ 227 228 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 229 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 230 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 231 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 232 233 234 /* Description GENERIC_U_SIG_OFFSET 235 236 Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within 237 'RX_PPDU_END' Set to zero if the TLV is not included<legal 238 0, 48, 54> 239 */ 240 241 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 242 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 243 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 244 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 245 246 247 /* Description RSSI_HT_OFFSET 248 249 Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' 250 Set to zero if the TLV is not included<legal 0, 49-127> 251 */ 252 253 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 254 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 255 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 256 #define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 257 258 259 /* Description RESERVED_1A 260 261 <legal 0> 262 */ 263 264 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 265 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 266 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 267 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 268 269 270 /* Description VHT_SIG_B_SU20_OFFSET 271 272 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within 273 'RX_PPDU_END' Set to zero if the TLV is not included<legal 274 0, 67, 74> 275 */ 276 277 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 278 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 279 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 280 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f 281 282 283 /* Description VHT_SIG_B_SU40_OFFSET 284 285 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within 286 'RX_PPDU_END' Set to zero if the TLV is not included<legal 287 0, 67, 74> 288 */ 289 290 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 291 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 292 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 293 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 294 295 296 /* Description VHT_SIG_B_SU80_OFFSET 297 298 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within 299 'RX_PPDU_END' Set to zero if the TLV is not included<legal 300 0, 67, 74> 301 */ 302 303 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 304 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 305 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 306 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 307 308 309 /* Description VHT_SIG_B_SU160_OFFSET 310 311 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within 312 'RX_PPDU_END' Set to zero if the TLV is not included<legal 313 0, 67, 74> 314 */ 315 316 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 317 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 318 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 319 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 320 321 322 /* Description RESERVED_2A 323 324 <legal 0> 325 */ 326 327 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 328 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 329 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 330 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 331 332 333 /* Description VHT_SIG_B_MU20_OFFSET 334 335 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within 336 'RX_PPDU_END' Set to zero if the TLV is not included<legal 337 0, 67, 74> 338 */ 339 340 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c 341 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 342 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 343 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f 344 345 346 /* Description VHT_SIG_B_MU40_OFFSET 347 348 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within 349 'RX_PPDU_END' Set to zero if the TLV is not included<legal 350 0, 67, 74> 351 */ 352 353 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c 354 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 355 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 356 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 357 358 359 /* Description VHT_SIG_B_MU80_OFFSET 360 361 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within 362 'RX_PPDU_END' Set to zero if the TLV is not included<legal 363 0, 67, 74> 364 */ 365 366 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c 367 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 368 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 369 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 370 371 372 /* Description VHT_SIG_B_MU160_OFFSET 373 374 Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within 375 'RX_PPDU_END' Set to zero if the TLV is not included<legal 376 0, 67, 74> 377 */ 378 379 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c 380 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 381 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 382 #define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 383 384 385 /* Description RESERVED_3A 386 387 <legal 0> 388 */ 389 390 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c 391 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 392 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 393 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 394 395 396 /* Description HE_SIG_B1_MU_OFFSET 397 398 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within 399 'RX_PPDU_END' Set to zero if the TLV is not included<legal 400 0, 51, 58> 401 */ 402 403 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 404 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 405 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 406 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f 407 408 409 /* Description HE_SIG_B2_MU_OFFSET 410 411 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within 412 'RX_PPDU_END' Set to zero if the TLV is not included<legal 413 0, 51, 58> 414 */ 415 416 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 417 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 418 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 419 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 420 421 422 /* Description HE_SIG_B2_OFDMA_OFFSET 423 424 Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within 425 'RX_PPDU_END' Set to zero if the TLV is not included<legal 426 0, 53, 62> 427 */ 428 429 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 430 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 431 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 432 #define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 433 434 435 /* Description FIRST_GENERIC_EHT_SIG_OFFSET 436 437 Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' 438 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 439 0, 51, 58> 440 */ 441 442 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 443 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 444 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 445 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 446 447 448 /* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED 449 450 Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs 451 are included in 'RX_PPDU_END,' set to zero otherwise 452 <legal all> 453 */ 454 455 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 456 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 457 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 458 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 459 460 461 /* Description RESERVED_4A 462 463 <legal 0> 464 */ 465 466 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 467 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 468 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 469 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 470 471 472 /* Description COMMON_USER_INFO_OFFSET 473 474 Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within 475 'RX_PPDU_END' Set to zero if the TLV is not included<legal 476 0, 46, 50, 67, 70-127> 477 */ 478 479 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 480 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 481 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 482 #define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f 483 484 485 /* Description FIRST_DEBUG_INFO_OFFSET 486 487 Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' 488 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 489 all> 490 */ 491 492 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 493 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 494 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 495 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 496 497 498 /* Description MULTIPLE_DEBUG_INFO_INCLUDED 499 500 Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are 501 included in 'RX_PPDU_END,' set to zero otherwise<legal all> 502 503 */ 504 505 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 506 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 507 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 508 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 509 510 511 /* Description FIRST_OTHER_RECEIVE_INFO_OFFSET 512 513 Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' 514 within 'RX_PPDU_END' Set to zero if the TLV is not included<legal 515 all> 516 */ 517 518 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 519 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 520 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 521 #define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 522 523 524 /* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED 525 526 Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs 527 are included in 'RX_PPDU_END,' set to zero otherwise<legal 528 all> 529 */ 530 531 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 532 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 533 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 534 #define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 535 536 537 /* Description RESERVED_5A 538 539 <legal 0> 540 */ 541 542 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 543 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 544 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 545 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 546 547 548 /* Description DATA_DONE_OFFSET 549 550 Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' 551 Set to zero if the TLV is not included<legal all> 552 */ 553 554 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 555 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 556 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 557 #define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff 558 559 560 /* Description GENERATED_CBF_DETAILS_OFFSET 561 562 Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' 563 within 'RX_PPDU_END'Set to zero if the TLV is not included<legal 564 0, 70-127> 565 */ 566 567 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 568 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 569 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 570 #define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 571 572 573 /* Description PKT_END_PART1_OFFSET 574 575 Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within 576 'RX_PPDU_END' Set to zero if the TLV is not included<legal 577 all> 578 */ 579 580 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 581 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 582 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 583 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 584 585 586 /* Description LOCATION_OFFSET 587 588 Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' 589 Set to zero if the TLV is not included<legal all> 590 */ 591 592 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 593 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 594 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 595 #define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 596 597 598 /* Description AZ_INTEGRITY_DATA_OFFSET 599 600 Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' 601 within 'RX_PPDU_END' 602 603 Set to zero if the TLV is not included 604 <legal all> 605 */ 606 607 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c 608 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0 609 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7 610 #define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff 611 612 613 /* Description PKT_END_OFFSET 614 615 Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' 616 Set to zero if the TLV is not included<legal all> 617 */ 618 619 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c 620 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 621 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 622 #define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 623 624 625 /* Description ABORT_REQUEST_ACK_OFFSET 626 627 Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' 628 or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' 629 630 Set to zero if the TLV is not included 631 <legal all> 632 */ 633 634 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c 635 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 636 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 637 #define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 638 639 640 /* Description RESERVED_7A 641 642 Spare space in case the widths of the above offsets grow<legal 643 all> 644 */ 645 646 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c 647 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 648 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 649 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 650 651 652 /* Description RESERVED_8A 653 654 Spare space in case the widths of the above offsets grow 655 656 <legal all> 657 */ 658 659 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 660 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 661 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 662 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff 663 664 665 /* Description RESERVED_9A 666 667 Spare space in case the widths of the above offsets grow 668 669 <legal all> 670 */ 671 672 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 673 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 674 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 675 #define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff 676 677 678 679 #endif // RXPCU_PPDU_END_LAYOUT_INFO 680