1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SW_MONITOR_RING_H_ 18 #define _SW_MONITOR_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_mpdu_details.h" 24 #define NUM_OF_DWORDS_SW_MONITOR_RING 8 25 26 27 struct sw_monitor_ring { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 struct rx_mpdu_details reo_level_mpdu_frame_info; 30 struct buffer_addr_info status_buff_addr_info; 31 uint32_t rxdma_push_reason : 2, // [1:0] 32 rxdma_error_code : 5, // [6:2] 33 mpdu_fragment_number : 4, // [10:7] 34 frameless_bar : 1, // [11:11] 35 status_buf_count : 4, // [15:12] 36 end_of_ppdu : 1, // [16:16] 37 reserved_6a : 15; // [31:17] 38 uint32_t phy_ppdu_id : 16, // [15:0] 39 reserved_7a : 4, // [19:16] 40 ring_id : 8, // [27:20] 41 looping_count : 4; // [31:28] 42 #else 43 struct rx_mpdu_details reo_level_mpdu_frame_info; 44 struct buffer_addr_info status_buff_addr_info; 45 uint32_t reserved_6a : 15, // [31:17] 46 end_of_ppdu : 1, // [16:16] 47 status_buf_count : 4, // [15:12] 48 frameless_bar : 1, // [11:11] 49 mpdu_fragment_number : 4, // [10:7] 50 rxdma_error_code : 5, // [6:2] 51 rxdma_push_reason : 2; // [1:0] 52 uint32_t looping_count : 4, // [31:28] 53 ring_id : 8, // [27:20] 54 reserved_7a : 4, // [19:16] 55 phy_ppdu_id : 16; // [15:0] 56 #endif 57 }; 58 59 60 /* Description REO_LEVEL_MPDU_FRAME_INFO 61 62 Consumer: SW 63 Producer: RXDMA 64 65 Details related to the MPDU being pushed to SW, valid only 66 if end_of_ppdu is set to 0 67 */ 68 69 70 /* Description MSDU_LINK_DESC_ADDR_INFO 71 72 Consumer: REO/SW/FW 73 Producer: RXDMA 74 75 Details of the physical address of the MSDU link descriptor 76 that contains pointers to MSDUs related to this MPDU 77 */ 78 79 80 /* Description BUFFER_ADDR_31_0 81 82 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 83 descriptor OR Link Descriptor 84 85 In case of 'NULL' pointer, this field is set to 0 86 <legal all> 87 */ 88 89 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 90 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 91 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 92 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 93 94 95 /* Description BUFFER_ADDR_39_32 96 97 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 98 descriptor OR Link Descriptor 99 100 In case of 'NULL' pointer, this field is set to 0 101 <legal all> 102 */ 103 104 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 105 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 106 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 107 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 108 109 110 /* Description RETURN_BUFFER_MANAGER 111 112 Consumer: WBM 113 Producer: SW/FW 114 115 In case of 'NULL' pointer, this field is set to 0 116 117 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 118 descriptor OR link descriptor that is being pointed to 119 shall be returned after the frame has been processed. It 120 is used by WBM for routing purposes. 121 122 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 123 to the WMB buffer idle list 124 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 125 to the WBM idle link descriptor idle list, where the chip 126 0 WBM is chosen in case of a multi-chip config 127 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 128 to the chip 1 WBM idle link descriptor idle list 129 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 130 to the chip 2 WBM idle link descriptor idle list 131 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 132 returned to chip 3 WBM idle link descriptor idle list 133 <enum 4 FW_BM> This buffer shall be returned to the FW 134 <enum 5 SW0_BM> This buffer shall be returned to the SW, 135 ring 0 136 <enum 6 SW1_BM> This buffer shall be returned to the SW, 137 ring 1 138 <enum 7 SW2_BM> This buffer shall be returned to the SW, 139 ring 2 140 <enum 8 SW3_BM> This buffer shall be returned to the SW, 141 ring 3 142 <enum 9 SW4_BM> This buffer shall be returned to the SW, 143 ring 4 144 <enum 10 SW5_BM> This buffer shall be returned to the SW, 145 ring 5 146 <enum 11 SW6_BM> This buffer shall be returned to the SW, 147 ring 6 148 149 <legal 0-12> 150 */ 151 152 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 153 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 154 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 155 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 156 157 158 /* Description SW_BUFFER_COOKIE 159 160 Cookie field exclusively used by SW. 161 162 In case of 'NULL' pointer, this field is set to 0 163 164 HW ignores the contents, accept that it passes the programmed 165 value on to other descriptors together with the physical 166 address 167 168 Field can be used by SW to for example associate the buffers 169 physical address with the virtual address 170 The bit definitions as used by SW are within SW HLD specification 171 172 173 NOTE1: 174 The three most significant bits can have a special meaning 175 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 176 and field transmit_bw_restriction is set 177 178 In case of NON punctured transmission: 179 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 180 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 181 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 182 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 183 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 184 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 185 Sw_buffer_cookie[19:18] = 2'b11: reserved 186 187 In case of punctured transmission: 188 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 189 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 190 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 191 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 192 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 193 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 194 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 195 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 196 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 197 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 198 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 199 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 200 Sw_buffer_cookie[19:18] = 2'b11: reserved 201 202 Note: a punctured transmission is indicated by the presence 203 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 204 205 <legal all> 206 */ 207 208 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 209 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 210 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 211 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 212 213 214 /* Description RX_MPDU_DESC_INFO_DETAILS 215 216 Consumer: REO/SW/FW 217 Producer: RXDMA 218 219 General information related to the MPDU that should be passed 220 on from REO entrance ring to the REO destination ring 221 */ 222 223 224 /* Description MSDU_COUNT 225 226 Consumer: REO/SW/FW 227 Producer: RXDMA 228 229 The number of MSDUs within the MPDU 230 <legal all> 231 */ 232 233 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 234 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 235 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 236 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 237 238 239 /* Description FRAGMENT_FLAG 240 241 Consumer: REO/SW/FW 242 Producer: RXDMA 243 244 When set, this MPDU is a fragment and REO should forward 245 this fragment MPDU to the REO destination ring without 246 any reorder checks, pn checks or bitmap update. This implies 247 that REO is forwarding the pointer to the MSDU link descriptor. 248 The destination ring is coming from a programmable register 249 setting in REO 250 251 <legal all> 252 */ 253 254 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 255 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 256 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 257 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 258 259 260 /* Description MPDU_RETRY_BIT 261 262 Consumer: REO/SW/FW 263 Producer: RXDMA 264 265 The retry bit setting from the MPDU header of the received 266 frame 267 <legal all> 268 */ 269 270 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 271 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 272 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 273 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 274 275 276 /* Description AMPDU_FLAG 277 278 Consumer: REO/SW/FW 279 Producer: RXDMA 280 281 When set, the MPDU was received as part of an A-MPDU. 282 <legal all> 283 */ 284 285 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 286 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 287 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 288 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 289 290 291 /* Description BAR_FRAME 292 293 Consumer: REO/SW/FW 294 Producer: RXDMA 295 296 When set, the received frame is a BAR frame. After processing, 297 this frame shall be pushed to SW or deleted. 298 <legal all> 299 */ 300 301 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 302 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 303 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 304 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 305 306 307 /* Description PN_FIELDS_CONTAIN_VALID_INFO 308 309 Consumer: REO/SW/FW 310 Producer: RXDMA 311 312 Copied here by RXDMA from RX_MPDU_END 313 When not set, REO will Not perform a PN sequence number 314 check 315 */ 316 317 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 318 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 319 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 320 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 321 322 323 /* Description RAW_MPDU 324 325 Field only valid when first_msdu_in_mpdu_flag is set. 326 327 When set, the contents in the MSDU buffer contains a 'RAW' 328 MPDU. This 'RAW' MPDU might be spread out over multiple 329 MSDU buffers. 330 <legal all> 331 */ 332 333 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 334 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 335 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 336 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 337 338 339 /* Description MORE_FRAGMENT_FLAG 340 341 The More Fragment bit setting from the MPDU header of the 342 received frame 343 344 <legal all> 345 */ 346 347 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 348 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 349 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 350 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 351 352 353 354 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 355 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 356 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 357 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 358 359 360 /* Description MPDU_QOS_CONTROL_VALID 361 362 When set, the MPDU has a QoS control field. 363 364 In case of ndp or phy_err, this field will never be set. 365 366 <legal all> 367 */ 368 369 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 370 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 371 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 372 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 373 374 375 /* Description TID 376 377 Field only valid when mpdu_qos_control_valid is set 378 379 The TID field in the QoS control field 380 <legal all> 381 */ 382 383 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 384 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 385 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 386 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 387 388 389 /* Description PEER_META_DATA 390 391 Meta data that SW has programmed in the Peer table entry 392 of the transmitting STA. 393 <legal all> 394 */ 395 396 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 397 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 398 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 399 #define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 400 401 402 /* Description STATUS_BUFF_ADDR_INFO 403 404 Consumer: SW 405 Producer: RXDMA 406 407 Details of the physical address of the first status buffer 408 used for the PPDU (either the PPDU that included the MPDU 409 being pushed to SW if end_of_ppdu = 0, or the PPDU whose 410 end is indicated through end_of_ppdu = 1) 411 */ 412 413 414 /* Description BUFFER_ADDR_31_0 415 416 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 417 descriptor OR Link Descriptor 418 419 In case of 'NULL' pointer, this field is set to 0 420 <legal all> 421 */ 422 423 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 424 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 425 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 426 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 427 428 429 /* Description BUFFER_ADDR_39_32 430 431 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 432 descriptor OR Link Descriptor 433 434 In case of 'NULL' pointer, this field is set to 0 435 <legal all> 436 */ 437 438 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 439 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 440 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 441 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 442 443 444 /* Description RETURN_BUFFER_MANAGER 445 446 Consumer: WBM 447 Producer: SW/FW 448 449 In case of 'NULL' pointer, this field is set to 0 450 451 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 452 descriptor OR link descriptor that is being pointed to 453 shall be returned after the frame has been processed. It 454 is used by WBM for routing purposes. 455 456 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 457 to the WMB buffer idle list 458 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 459 to the WBM idle link descriptor idle list, where the chip 460 0 WBM is chosen in case of a multi-chip config 461 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 462 to the chip 1 WBM idle link descriptor idle list 463 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 464 to the chip 2 WBM idle link descriptor idle list 465 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 466 returned to chip 3 WBM idle link descriptor idle list 467 <enum 4 FW_BM> This buffer shall be returned to the FW 468 <enum 5 SW0_BM> This buffer shall be returned to the SW, 469 ring 0 470 <enum 6 SW1_BM> This buffer shall be returned to the SW, 471 ring 1 472 <enum 7 SW2_BM> This buffer shall be returned to the SW, 473 ring 2 474 <enum 8 SW3_BM> This buffer shall be returned to the SW, 475 ring 3 476 <enum 9 SW4_BM> This buffer shall be returned to the SW, 477 ring 4 478 <enum 10 SW5_BM> This buffer shall be returned to the SW, 479 ring 5 480 <enum 11 SW6_BM> This buffer shall be returned to the SW, 481 ring 6 482 483 <legal 0-12> 484 */ 485 486 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 487 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 488 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 489 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 490 491 492 /* Description SW_BUFFER_COOKIE 493 494 Cookie field exclusively used by SW. 495 496 In case of 'NULL' pointer, this field is set to 0 497 498 HW ignores the contents, accept that it passes the programmed 499 value on to other descriptors together with the physical 500 address 501 502 Field can be used by SW to for example associate the buffers 503 physical address with the virtual address 504 The bit definitions as used by SW are within SW HLD specification 505 506 507 NOTE1: 508 The three most significant bits can have a special meaning 509 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 510 and field transmit_bw_restriction is set 511 512 In case of NON punctured transmission: 513 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 514 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 515 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 516 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 517 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 518 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 519 Sw_buffer_cookie[19:18] = 2'b11: reserved 520 521 In case of punctured transmission: 522 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 523 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 524 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 525 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 526 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 527 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 528 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 529 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 530 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 531 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 532 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 533 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 534 Sw_buffer_cookie[19:18] = 2'b11: reserved 535 536 Note: a punctured transmission is indicated by the presence 537 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 538 539 <legal all> 540 */ 541 542 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 543 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 544 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 545 #define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 546 547 548 /* Description RXDMA_PUSH_REASON 549 550 Indicates why RXDMA pushed the frame to this ring 551 552 <enum 0 rxdma_error_detected> RXDMA detected an error an 553 pushed this frame to this queue 554 <enum 1 rxdma_routing_instruction> RXDMA pushed the frame 555 to this queue per received routing instructions. No error 556 within RXDMA was detected 557 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 558 result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" 559 set, but instead WBM might just see a NULL pointer in the 560 MSDU link descriptor. This is to be considered a normal 561 condition for this scenario. 562 563 <legal 0 - 2> 564 */ 565 566 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 567 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_LSB 0 568 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_MSB 1 569 #define SW_MONITOR_RING_RXDMA_PUSH_REASON_MASK 0x00000003 570 571 572 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_LSB 2 573 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_MSB 6 574 #define SW_MONITOR_RING_RXDMA_ERROR_CODE_MASK 0x0000007c 575 576 577 /* Description MPDU_FRAGMENT_NUMBER 578 579 Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag 580 is set and end_of_ppdu is set to 0. 581 582 The fragment number from the 802.11 header. 583 584 Note that the sequence number is embedded in the field: 585 Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number 586 587 588 <legal all> 589 */ 590 591 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 592 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_LSB 7 593 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MSB 10 594 #define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 595 596 597 /* Description FRAMELESS_BAR 598 599 When set, this SW monitor ring struct contains BAR info 600 from a multi TID BAR frame. The original multi TID BAR frame 601 itself contained all the REO info for the first TID, but 602 all the subsequent TID info and their linkage to the REO 603 descriptors is passed down as 'frameless' BAR info. 604 605 The only fields valid in this descriptor when this bit is 606 within the 607 Reo_level_mpdu_frame_info: 608 Within Rx_mpdu_desc_info_details: 609 Mpdu_Sequence_number 610 BAR_frame 611 Peer_meta_data 612 All other fields shall be set to 0. 613 614 <legal all> 615 */ 616 617 #define SW_MONITOR_RING_FRAMELESS_BAR_OFFSET 0x00000018 618 #define SW_MONITOR_RING_FRAMELESS_BAR_LSB 11 619 #define SW_MONITOR_RING_FRAMELESS_BAR_MSB 11 620 #define SW_MONITOR_RING_FRAMELESS_BAR_MASK 0x00000800 621 622 623 /* Description STATUS_BUF_COUNT 624 625 A count of status buffers used so far for the PPDU (either 626 the PPDU that included the MPDU being pushed to SW if end_of_ppdu 627 = 0, or the PPDU whose end is indicated through end_of_ppdu 628 = 1) 629 */ 630 631 #define SW_MONITOR_RING_STATUS_BUF_COUNT_OFFSET 0x00000018 632 #define SW_MONITOR_RING_STATUS_BUF_COUNT_LSB 12 633 #define SW_MONITOR_RING_STATUS_BUF_COUNT_MSB 15 634 #define SW_MONITOR_RING_STATUS_BUF_COUNT_MASK 0x0000f000 635 636 637 /* Description END_OF_PPDU 638 639 RXDMA can be configured to generate a separate 'SW_MONITOR_RING' 640 descriptor at the end of a PPDU (either through an 'RX_PPDU_END' 641 TLV or through an 'RX_FLUSH') to demarcate PPDUs. 642 643 For such a descriptor, this bit is set to 1 and fields Reo_level_mpdu_frame_info, 644 mpdu_fragment_number and Frameless_bar are all set to 0. 645 646 647 Otherwise this bit is set to 0. 648 */ 649 650 #define SW_MONITOR_RING_END_OF_PPDU_OFFSET 0x00000018 651 #define SW_MONITOR_RING_END_OF_PPDU_LSB 16 652 #define SW_MONITOR_RING_END_OF_PPDU_MSB 16 653 #define SW_MONITOR_RING_END_OF_PPDU_MASK 0x00010000 654 655 656 /* Description RESERVED_6A 657 658 <legal 0> 659 */ 660 661 #define SW_MONITOR_RING_RESERVED_6A_OFFSET 0x00000018 662 #define SW_MONITOR_RING_RESERVED_6A_LSB 17 663 #define SW_MONITOR_RING_RESERVED_6A_MSB 31 664 #define SW_MONITOR_RING_RESERVED_6A_MASK 0xfffe0000 665 666 667 /* Description PHY_PPDU_ID 668 669 A PPDU counter value that PHY increments for every PPDU 670 received 671 The counter value wraps around. RXDMA can be configured 672 to copy this from the RX_PPDU_START TLV for every output 673 descriptor. 674 675 <legal all> 676 */ 677 678 #define SW_MONITOR_RING_PHY_PPDU_ID_OFFSET 0x0000001c 679 #define SW_MONITOR_RING_PHY_PPDU_ID_LSB 0 680 #define SW_MONITOR_RING_PHY_PPDU_ID_MSB 15 681 #define SW_MONITOR_RING_PHY_PPDU_ID_MASK 0x0000ffff 682 683 684 /* Description RESERVED_7A 685 686 <legal 0> 687 */ 688 689 #define SW_MONITOR_RING_RESERVED_7A_OFFSET 0x0000001c 690 #define SW_MONITOR_RING_RESERVED_7A_LSB 16 691 #define SW_MONITOR_RING_RESERVED_7A_MSB 19 692 #define SW_MONITOR_RING_RESERVED_7A_MASK 0x000f0000 693 694 695 /* Description RING_ID 696 697 Consumer: SW/REO/DEBUG 698 Producer: SRNG (of RXDMA) 699 700 For debugging. 701 This field is filled in by the SRNG module. 702 It help to identify the ring that is being looked <legal 703 all> 704 */ 705 706 #define SW_MONITOR_RING_RING_ID_OFFSET 0x0000001c 707 #define SW_MONITOR_RING_RING_ID_LSB 20 708 #define SW_MONITOR_RING_RING_ID_MSB 27 709 #define SW_MONITOR_RING_RING_ID_MASK 0x0ff00000 710 711 712 /* Description LOOPING_COUNT 713 714 Consumer: SW/REO/DEBUG 715 Producer: SRNG (of RXDMA) 716 717 For debugging. 718 This field is filled in by the SRNG module. 719 720 A count value that indicates the number of times the producer 721 of entries into this Ring has looped around the ring. 722 At initialization time, this value is set to 0. On the first 723 loop, this value is set to 1. After the max value is reached 724 allowed by the number of bits for this field, the count 725 value continues with 0 again. 726 727 In case SW is the consumer of the ring entries, it can use 728 this field to figure out up to where the producer of entries 729 has created new entries. This eliminates the need to check 730 where the "head pointer' of the ring is located once the 731 SW starts processing an interrupt indicating that new entries 732 have been put into this ring... 733 734 Also note that SW if it wants only needs to look at the 735 LSB bit of this count value. 736 <legal all> 737 */ 738 739 #define SW_MONITOR_RING_LOOPING_COUNT_OFFSET 0x0000001c 740 #define SW_MONITOR_RING_LOOPING_COUNT_LSB 28 741 #define SW_MONITOR_RING_LOOPING_COUNT_MSB 31 742 #define SW_MONITOR_RING_LOOPING_COUNT_MASK 0xf0000000 743 744 745 746 #endif // SW_MONITOR_RING 747