1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TCL_STATUS_RING_H_ 18 #define _TCL_STATUS_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 23 24 25 struct tcl_status_ring { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t gse_ctrl : 4, // [3:0] 28 ase_fse_sel : 1, // [4:4] 29 cache_op_res : 2, // [6:5] 30 index_search_en : 1, // [7:7] 31 msdu_cnt_n : 24; // [31:8] 32 uint32_t msdu_byte_cnt_n : 32; // [31:0] 33 uint32_t msdu_timestmp_n : 32; // [31:0] 34 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 35 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 36 uint32_t hash_indx_val : 20, // [19:0] 37 cache_set_num : 4, // [23:20] 38 reserved_5a : 8; // [31:24] 39 uint32_t reserved_6a : 32; // [31:0] 40 uint32_t reserved_7a : 20, // [19:0] 41 ring_id : 8, // [27:20] 42 looping_count : 4; // [31:28] 43 #else 44 uint32_t msdu_cnt_n : 24, // [31:8] 45 index_search_en : 1, // [7:7] 46 cache_op_res : 2, // [6:5] 47 ase_fse_sel : 1, // [4:4] 48 gse_ctrl : 4; // [3:0] 49 uint32_t msdu_byte_cnt_n : 32; // [31:0] 50 uint32_t msdu_timestmp_n : 32; // [31:0] 51 uint32_t cmd_meta_data_31_0 : 32; // [31:0] 52 uint32_t cmd_meta_data_63_32 : 32; // [31:0] 53 uint32_t reserved_5a : 8, // [31:24] 54 cache_set_num : 4, // [23:20] 55 hash_indx_val : 20; // [19:0] 56 uint32_t reserved_6a : 32; // [31:0] 57 uint32_t looping_count : 4, // [31:28] 58 ring_id : 8, // [27:20] 59 reserved_7a : 20; // [19:0] 60 #endif 61 }; 62 63 64 /* Description GSE_CTRL 65 66 GSE control operations. This includes cache operations and 67 table entry statistics read/clear operation. 68 <enum 0 rd_stat> Report or Read statistics 69 <enum 1 srch_dis> Search disable. Report only Hash 70 <enum 2 Wr_bk_single> Write Back single entry 71 <enum 3 wr_bk_all> Write Back entire cache entry 72 <enum 4 inval_single> Invalidate single cache entry 73 <enum 5 inval_all> Invalidate entire cache 74 <enum 6 wr_bk_inval_single> Write back and Invalidate single 75 entry in cache 76 <enum 7 wr_bk_inval_all> write back and invalidate entire 77 cache 78 <enum 8 clr_stat_single> Clear statistics for single entry 79 80 <legal 0-8> 81 Rest of the values reserved. 82 For all single entry control operations (write back, Invalidate 83 or both)Statistics will be reported 84 */ 85 86 #define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 87 #define TCL_STATUS_RING_GSE_CTRL_LSB 0 88 #define TCL_STATUS_RING_GSE_CTRL_MSB 3 89 #define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f 90 91 92 /* Description ASE_FSE_SEL 93 94 Search Engine for which operation is done. 95 1'b0: Address Search Engine Result 96 1'b1: Flow Search Engine result 97 */ 98 99 #define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 100 #define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 101 #define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 102 #define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 103 104 105 /* Description CACHE_OP_RES 106 107 Cache operation result. Following are results of cache operation. 108 109 <enum 0 op_done> Operation successful 110 <enum 1 not_fnd> Entry not found in Table 111 <enum 2 timeout_er> Timeout Error 112 <legal 0-2> 113 */ 114 115 #define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 116 #define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 117 #define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 118 #define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 119 120 121 /* Description INDEX_SEARCH_EN 122 123 When this bit is set to 1 control_buffer_addr[19:0] will 124 be considered as index of the AST or Flow table and GSE 125 commands will be executed accordingly on the entry pointed 126 by the index. 127 This feature is disabled by setting this bit to 0. 128 <enum 0 index_based_cmd_disable> 129 <enum 1 index_based_cmd_enable> 130 131 <legal all> 132 */ 133 134 #define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 135 #define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 136 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 137 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 138 139 140 /* Description MSDU_CNT_N 141 142 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 143 4'b1000 144 */ 145 146 #define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 147 #define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 148 #define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 149 #define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 150 151 152 /* Description MSDU_BYTE_CNT_N 153 154 MSDU byte count for entry 1. Valid when GSE_CTRL is 4'b0111 155 and 4'b1000 156 */ 157 158 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 159 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 160 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 161 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff 162 163 164 /* Description MSDU_TIMESTMP_N 165 166 MSDU timestamp for entry 1. Valid when GSE_CTRL is 4'b0111 167 and 4'b1000 168 */ 169 170 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 171 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 172 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 173 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff 174 175 176 /* Description CMD_META_DATA_31_0 177 178 Meta data from input ring 179 <legal all> 180 */ 181 182 #define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c 183 #define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 184 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 185 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff 186 187 188 /* Description CMD_META_DATA_63_32 189 190 Meta data from input ring 191 <legal all> 192 */ 193 194 #define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 195 #define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 196 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 197 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff 198 199 200 /* Description HASH_INDX_VAL 201 202 Index of entry in the table in case of search pass (or) 203 204 Hash value of the entry in table in case of search failed 205 or search disable. 206 <legal all> 207 */ 208 209 #define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 210 #define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 211 #define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 212 #define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff 213 214 215 /* Description CACHE_SET_NUM 216 217 Cache set number copied from TCL_GSE_CMD 218 */ 219 220 #define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 221 #define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 222 #define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 223 #define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 224 225 226 /* Description RESERVED_5A 227 228 <legal 0> 229 */ 230 231 #define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 232 #define TCL_STATUS_RING_RESERVED_5A_LSB 24 233 #define TCL_STATUS_RING_RESERVED_5A_MSB 31 234 #define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 235 236 237 /* Description RESERVED_6A 238 239 <legal 0> 240 */ 241 242 #define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 243 #define TCL_STATUS_RING_RESERVED_6A_LSB 0 244 #define TCL_STATUS_RING_RESERVED_6A_MSB 31 245 #define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff 246 247 248 /* Description RESERVED_7A 249 250 <legal 0> 251 */ 252 253 #define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c 254 #define TCL_STATUS_RING_RESERVED_7A_LSB 0 255 #define TCL_STATUS_RING_RESERVED_7A_MSB 19 256 #define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff 257 258 259 /* Description RING_ID 260 261 The buffer pointer ring ID. 262 263 Helps with debugging when dumping ring contents. 264 <legal all> 265 */ 266 267 #define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c 268 #define TCL_STATUS_RING_RING_ID_LSB 20 269 #define TCL_STATUS_RING_RING_ID_MSB 27 270 #define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 271 272 273 /* Description LOOPING_COUNT 274 275 A count value that indicates the number of times the producer 276 of entries into the Ring has looped around the ring. 277 At initialization time, this value is set to 0. On the first 278 loop, this value is set to 1. After the max value is reached 279 allowed by the number of bits for this field, the count 280 value continues with 0 again. 281 282 In case SW is the consumer of the ring entries, it can use 283 this field to figure out up to where the producer of entries 284 has created new entries. This eliminates the need to check 285 where the "head pointer' of the ring is located once the 286 SW starts processing an interrupt indicating that new entries 287 have been put into this ring... 288 289 Also note that SW if it wants only needs to look at the 290 LSB bit of this count value. 291 <legal all> 292 */ 293 294 #define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c 295 #define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 296 #define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 297 #define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 298 299 300 301 #endif // TCL_STATUS_RING 302