1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TX_FES_STATUS_1K_BA_H_ 18 #define _TX_FES_STATUS_1K_BA_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 23 24 #define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 25 26 27 struct tx_fes_status_1k_ba { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t ack_ba_status_type : 1, // [0:0] 30 ba_type : 1, // [1:1] 31 ba_tid : 4, // [5:2] 32 unexpected_ack_or_ba : 1, // [6:6] 33 response_timeout : 1, // [7:7] 34 ack_frame_rssi : 8, // [15:8] 35 ssn : 12, // [27:16] 36 reserved_0b : 4; // [31:28] 37 uint32_t sw_peer_id : 16, // [15:0] 38 reserved_1a : 16; // [31:16] 39 uint32_t ba_bitmap_31_0 : 32; // [31:0] 40 uint32_t ba_bitmap_63_32 : 32; // [31:0] 41 uint32_t ba_bitmap_95_64 : 32; // [31:0] 42 uint32_t ba_bitmap_127_96 : 32; // [31:0] 43 uint32_t ba_bitmap_159_128 : 32; // [31:0] 44 uint32_t ba_bitmap_191_160 : 32; // [31:0] 45 uint32_t ba_bitmap_223_192 : 32; // [31:0] 46 uint32_t ba_bitmap_255_224 : 32; // [31:0] 47 uint32_t ba_bitmap_287_256 : 32; // [31:0] 48 uint32_t ba_bitmap_319_288 : 32; // [31:0] 49 uint32_t ba_bitmap_351_320 : 32; // [31:0] 50 uint32_t ba_bitmap_383_352 : 32; // [31:0] 51 uint32_t ba_bitmap_415_384 : 32; // [31:0] 52 uint32_t ba_bitmap_447_416 : 32; // [31:0] 53 uint32_t ba_bitmap_479_448 : 32; // [31:0] 54 uint32_t ba_bitmap_511_480 : 32; // [31:0] 55 uint32_t ba_bitmap_543_512 : 32; // [31:0] 56 uint32_t ba_bitmap_575_544 : 32; // [31:0] 57 uint32_t ba_bitmap_607_576 : 32; // [31:0] 58 uint32_t ba_bitmap_639_608 : 32; // [31:0] 59 uint32_t ba_bitmap_671_640 : 32; // [31:0] 60 uint32_t ba_bitmap_703_672 : 32; // [31:0] 61 uint32_t ba_bitmap_735_704 : 32; // [31:0] 62 uint32_t ba_bitmap_767_736 : 32; // [31:0] 63 uint32_t ba_bitmap_799_768 : 32; // [31:0] 64 uint32_t ba_bitmap_831_800 : 32; // [31:0] 65 uint32_t ba_bitmap_863_832 : 32; // [31:0] 66 uint32_t ba_bitmap_895_864 : 32; // [31:0] 67 uint32_t ba_bitmap_927_896 : 32; // [31:0] 68 uint32_t ba_bitmap_959_928 : 32; // [31:0] 69 uint32_t ba_bitmap_991_960 : 32; // [31:0] 70 uint32_t ba_bitmap_1023_992 : 32; // [31:0] 71 #else 72 uint32_t reserved_0b : 4, // [31:28] 73 ssn : 12, // [27:16] 74 ack_frame_rssi : 8, // [15:8] 75 response_timeout : 1, // [7:7] 76 unexpected_ack_or_ba : 1, // [6:6] 77 ba_tid : 4, // [5:2] 78 ba_type : 1, // [1:1] 79 ack_ba_status_type : 1; // [0:0] 80 uint32_t reserved_1a : 16, // [31:16] 81 sw_peer_id : 16; // [15:0] 82 uint32_t ba_bitmap_31_0 : 32; // [31:0] 83 uint32_t ba_bitmap_63_32 : 32; // [31:0] 84 uint32_t ba_bitmap_95_64 : 32; // [31:0] 85 uint32_t ba_bitmap_127_96 : 32; // [31:0] 86 uint32_t ba_bitmap_159_128 : 32; // [31:0] 87 uint32_t ba_bitmap_191_160 : 32; // [31:0] 88 uint32_t ba_bitmap_223_192 : 32; // [31:0] 89 uint32_t ba_bitmap_255_224 : 32; // [31:0] 90 uint32_t ba_bitmap_287_256 : 32; // [31:0] 91 uint32_t ba_bitmap_319_288 : 32; // [31:0] 92 uint32_t ba_bitmap_351_320 : 32; // [31:0] 93 uint32_t ba_bitmap_383_352 : 32; // [31:0] 94 uint32_t ba_bitmap_415_384 : 32; // [31:0] 95 uint32_t ba_bitmap_447_416 : 32; // [31:0] 96 uint32_t ba_bitmap_479_448 : 32; // [31:0] 97 uint32_t ba_bitmap_511_480 : 32; // [31:0] 98 uint32_t ba_bitmap_543_512 : 32; // [31:0] 99 uint32_t ba_bitmap_575_544 : 32; // [31:0] 100 uint32_t ba_bitmap_607_576 : 32; // [31:0] 101 uint32_t ba_bitmap_639_608 : 32; // [31:0] 102 uint32_t ba_bitmap_671_640 : 32; // [31:0] 103 uint32_t ba_bitmap_703_672 : 32; // [31:0] 104 uint32_t ba_bitmap_735_704 : 32; // [31:0] 105 uint32_t ba_bitmap_767_736 : 32; // [31:0] 106 uint32_t ba_bitmap_799_768 : 32; // [31:0] 107 uint32_t ba_bitmap_831_800 : 32; // [31:0] 108 uint32_t ba_bitmap_863_832 : 32; // [31:0] 109 uint32_t ba_bitmap_895_864 : 32; // [31:0] 110 uint32_t ba_bitmap_927_896 : 32; // [31:0] 111 uint32_t ba_bitmap_959_928 : 32; // [31:0] 112 uint32_t ba_bitmap_991_960 : 32; // [31:0] 113 uint32_t ba_bitmap_1023_992 : 32; // [31:0] 114 #endif 115 }; 116 117 118 /* Description ACK_BA_STATUS_TYPE 119 120 Consumer: SW 121 Producer: RXPCU 122 123 <enum 1 1K_BA_type> This TLV represents an BA reception. 124 125 <legal 1> 126 */ 127 128 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 129 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 130 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 131 #define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 132 133 134 /* Description BA_TYPE 135 136 <enum 1 1K_BA_TYPE_bitmap> 137 <legal 1> 138 */ 139 140 #define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 141 #define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 142 #define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 143 #define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 144 145 146 /* Description BA_TID 147 148 The TID field copied from the BA frame 149 <legal all> 150 */ 151 152 #define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 153 #define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 154 #define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 155 #define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c 156 157 158 /* Description UNEXPECTED_ACK_OR_BA 159 160 Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT 161 TLV' received. 162 This can happen when a BA for unexpected TID is received. 163 164 165 This message enables SW to still pass this BA information 166 on to the right TQM queue. 167 <legal all> 168 */ 169 170 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 171 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 172 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 173 #define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 174 175 176 /* Description RESPONSE_TIMEOUT 177 178 When set, there was delay in RXPCU (likely due to AST fetch 179 delay) that resulted in TXPCU not being able to send the 180 RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout 181 from the falling edge of the frame. This status TLV is still 182 generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED 183 TLV. 184 <legal all> 185 */ 186 187 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 188 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 189 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 190 #define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 191 192 193 /* Description ACK_FRAME_RSSI 194 195 RSSI of the received ACK, BA or M-BA frame. 196 197 <legal all> 198 */ 199 200 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 201 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 202 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 203 #define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 204 205 206 /* Description SSN 207 208 Consumer: TQM/FW 209 Producer: SW/RXPCU 210 211 Field only valid in case of the Ack_ba_status_type indicating: 212 BA_type 213 214 The starting Sequence number of the (B)ACK bitmap <legal 215 all> 216 */ 217 218 #define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 219 #define TX_FES_STATUS_1K_BA_SSN_LSB 16 220 #define TX_FES_STATUS_1K_BA_SSN_MSB 27 221 #define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 222 223 224 /* Description RESERVED_0B 225 226 <legal 0> 227 */ 228 229 #define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 230 #define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 231 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 232 #define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 233 234 235 /* Description SW_PEER_ID 236 237 The sw_peer_id for which the bitmap is requested. 238 239 SW could use this info to link this TLV back to the right 240 TQM queue (if needed) 241 <legal all> 242 */ 243 244 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 245 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 246 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 247 #define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 248 249 250 /* Description RESERVED_1A 251 252 <legal 0> 253 */ 254 255 #define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 256 #define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 257 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 258 #define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 259 260 261 /* Description BA_BITMAP_31_0 262 263 Consumer: TQM/FW 264 Producer: SW/RXPCU 265 266 Ba_bitmap_31_0 267 <legal all> 268 */ 269 270 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 271 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 272 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 273 #define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff 274 275 276 /* Description BA_BITMAP_63_32 277 278 Consumer: TQM/FW 279 Producer: SW/RXPCU 280 281 Ba_bitmap_63_32 282 <legal all> 283 */ 284 285 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 286 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 287 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 288 #define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 289 290 291 /* Description BA_BITMAP_95_64 292 293 Consumer: TQM/FW 294 Producer: SW/RXPCU 295 296 Ba_bitmap_95_64 297 <legal all> 298 */ 299 300 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 301 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 302 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 303 #define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff 304 305 306 /* Description BA_BITMAP_127_96 307 308 Consumer: TQM/FW 309 Producer: SW/RXPCU 310 311 Ba_bitmap_127_96 312 <legal all> 313 */ 314 315 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 316 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 317 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 318 #define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 319 320 321 /* Description BA_BITMAP_159_128 322 323 Consumer: TQM/FW 324 Producer: SW/RXPCU 325 326 Ba_bitmap_159_128 327 <legal all> 328 */ 329 330 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 331 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 332 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 333 #define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff 334 335 336 /* Description BA_BITMAP_191_160 337 338 Consumer: TQM/FW 339 Producer: SW/RXPCU 340 341 Ba_bitmap_191_160 342 <legal all> 343 */ 344 345 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 346 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 347 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 348 #define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 349 350 351 /* Description BA_BITMAP_223_192 352 353 Consumer: TQM/FW 354 Producer: SW/RXPCU 355 356 Ba_bitmap_223_192 357 <legal all> 358 */ 359 360 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 361 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 362 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 363 #define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff 364 365 366 /* Description BA_BITMAP_255_224 367 368 Consumer: TQM/FW 369 Producer: SW/RXPCU 370 371 Ba_bitmap_255_224 372 <legal all> 373 */ 374 375 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 376 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 377 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 378 #define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 379 380 381 /* Description BA_BITMAP_287_256 382 383 Ba_bitmap_287_256 384 <legal all> 385 */ 386 387 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 388 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 389 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 390 #define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff 391 392 393 /* Description BA_BITMAP_319_288 394 395 Ba_bitmap_319_288 396 <legal all> 397 */ 398 399 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 400 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 401 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 402 #define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 403 404 405 /* Description BA_BITMAP_351_320 406 407 Ba_bitmap_351_320 408 <legal all> 409 */ 410 411 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 412 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 413 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 414 #define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff 415 416 417 /* Description BA_BITMAP_383_352 418 419 Ba_bitmap_383_352 420 <legal all> 421 */ 422 423 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 424 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 425 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 426 #define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 427 428 429 /* Description BA_BITMAP_415_384 430 431 Ba_bitmap_415_384 432 <legal all> 433 */ 434 435 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 436 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 437 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 438 #define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff 439 440 441 /* Description BA_BITMAP_447_416 442 443 Ba_bitmap_447_416 444 <legal all> 445 */ 446 447 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 448 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 449 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 450 #define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 451 452 453 /* Description BA_BITMAP_479_448 454 455 Ba_bitmap_479_448 456 <legal all> 457 */ 458 459 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 460 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 461 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 462 #define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff 463 464 465 /* Description BA_BITMAP_511_480 466 467 Ba_bitmap_511_480 468 <legal all> 469 */ 470 471 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 472 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 473 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 474 #define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 475 476 477 /* Description BA_BITMAP_543_512 478 479 Ba_bitmap_543_512 480 <legal all> 481 */ 482 483 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 484 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 485 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 486 #define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff 487 488 489 /* Description BA_BITMAP_575_544 490 491 Ba_bitmap_575_544 492 <legal all> 493 */ 494 495 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 496 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 497 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 498 #define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 499 500 501 /* Description BA_BITMAP_607_576 502 503 Ba_bitmap_607_576 504 <legal all> 505 */ 506 507 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 508 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 509 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 510 #define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff 511 512 513 /* Description BA_BITMAP_639_608 514 515 Ba_bitmap_639_608 516 <legal all> 517 */ 518 519 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 520 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 521 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 522 #define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 523 524 525 /* Description BA_BITMAP_671_640 526 527 Ba_bitmap_671_640 528 <legal all> 529 */ 530 531 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 532 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 533 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 534 #define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff 535 536 537 /* Description BA_BITMAP_703_672 538 539 Ba_bitmap_703_672 540 <legal all> 541 */ 542 543 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 544 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 545 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 546 #define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 547 548 549 /* Description BA_BITMAP_735_704 550 551 Ba_bitmap_735_704 552 <legal all> 553 */ 554 555 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 556 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 557 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 558 #define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff 559 560 561 /* Description BA_BITMAP_767_736 562 563 Ba_bitmap_767_736 564 <legal all> 565 */ 566 567 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 568 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 569 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 570 #define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 571 572 573 /* Description BA_BITMAP_799_768 574 575 Ba_bitmap_799_768 576 <legal all> 577 */ 578 579 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 580 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 581 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 582 #define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff 583 584 585 /* Description BA_BITMAP_831_800 586 587 Ba_bitmap_831_800 588 <legal all> 589 */ 590 591 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 592 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 593 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 594 #define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 595 596 597 /* Description BA_BITMAP_863_832 598 599 Ba_bitmap_863_832 600 <legal all> 601 */ 602 603 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 604 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 605 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 606 #define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff 607 608 609 /* Description BA_BITMAP_895_864 610 611 Ba_bitmap_895_864 612 <legal all> 613 */ 614 615 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 616 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 617 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 618 #define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 619 620 621 /* Description BA_BITMAP_927_896 622 623 Ba_bitmap_927_896 624 <legal all> 625 */ 626 627 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 628 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 629 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 630 #define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff 631 632 633 /* Description BA_BITMAP_959_928 634 635 Ba_bitmap_959_928 636 <legal all> 637 */ 638 639 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 640 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 641 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 642 #define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 643 644 645 /* Description BA_BITMAP_991_960 646 647 Ba_bitmap_991_960 648 <legal all> 649 */ 650 651 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 652 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 653 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 654 #define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff 655 656 657 /* Description BA_BITMAP_1023_992 658 659 Ba_bitmap_1023_992 660 <legal all> 661 */ 662 663 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 664 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 665 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 666 #define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 667 668 669 670 #endif // TX_FES_STATUS_1K_BA 671