1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TX_FES_STATUS_PROT_H_ 18 #define _TX_FES_STATUS_PROT_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "phytx_abort_request_info.h" 23 #define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 24 25 #define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 26 27 28 struct tx_fes_status_prot { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 uint32_t success : 1, // [0:0] 31 phytx_pkt_end_info_valid : 1, // [1:1] 32 phytx_abort_request_info_valid : 1, // [2:2] 33 reserved_0 : 20, // [22:3] 34 pkt_type : 4, // [26:23] 35 dot11ax_su_extended : 1, // [27:27] 36 rate_mcs : 4; // [31:28] 37 uint32_t frame_type : 2, // [1:0] 38 frame_subtype : 4, // [5:2] 39 rx_pwr_mgmt : 1, // [6:6] 40 status : 1, // [7:7] 41 duration_field : 16, // [23:8] 42 reserved_1a : 2, // [25:24] 43 agc_cbw : 3, // [28:26] 44 service_cbw : 3; // [31:29] 45 uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] 46 start_of_frame_timestamp_31_16 : 16; // [31:16] 47 uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] 48 end_of_frame_timestamp_31_16 : 16; // [31:16] 49 uint32_t tx_group_delay : 12, // [11:0] 50 timing_status : 2, // [13:12] 51 dpdtrain_done : 1, // [14:14] 52 reserved_4 : 1, // [15:15] 53 transmit_delay : 16; // [31:16] 54 uint32_t tpc_dbg_info_cmn_15_0 : 16, // [15:0] 55 tpc_dbg_info_cmn_31_16 : 16; // [31:16] 56 uint32_t tpc_dbg_info_cmn_47_32 : 16, // [15:0] 57 tpc_dbg_info_chn1_15_0 : 16; // [31:16] 58 uint32_t tpc_dbg_info_chn1_31_16 : 16, // [15:0] 59 tpc_dbg_info_chn1_47_32 : 16; // [31:16] 60 uint32_t tpc_dbg_info_chn1_63_48 : 16, // [15:0] 61 tpc_dbg_info_chn1_79_64 : 16; // [31:16] 62 uint32_t tpc_dbg_info_chn2_15_0 : 16, // [15:0] 63 tpc_dbg_info_chn2_31_16 : 16; // [31:16] 64 uint32_t tpc_dbg_info_chn2_47_32 : 16, // [15:0] 65 tpc_dbg_info_chn2_63_48 : 16; // [31:16] 66 uint32_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] 67 struct phytx_abort_request_info phytx_abort_request_info_details; 68 uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] 69 phytx_tx_end_sw_info_31_16 : 16; // [31:16] 70 uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] 71 phytx_tx_end_sw_info_63_48 : 16; // [31:16] 72 #else 73 uint32_t rate_mcs : 4, // [31:28] 74 dot11ax_su_extended : 1, // [27:27] 75 pkt_type : 4, // [26:23] 76 reserved_0 : 20, // [22:3] 77 phytx_abort_request_info_valid : 1, // [2:2] 78 phytx_pkt_end_info_valid : 1, // [1:1] 79 success : 1; // [0:0] 80 uint32_t service_cbw : 3, // [31:29] 81 agc_cbw : 3, // [28:26] 82 reserved_1a : 2, // [25:24] 83 duration_field : 16, // [23:8] 84 status : 1, // [7:7] 85 rx_pwr_mgmt : 1, // [6:6] 86 frame_subtype : 4, // [5:2] 87 frame_type : 2; // [1:0] 88 uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] 89 start_of_frame_timestamp_15_0 : 16; // [15:0] 90 uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] 91 end_of_frame_timestamp_15_0 : 16; // [15:0] 92 uint32_t transmit_delay : 16, // [31:16] 93 reserved_4 : 1, // [15:15] 94 dpdtrain_done : 1, // [14:14] 95 timing_status : 2, // [13:12] 96 tx_group_delay : 12; // [11:0] 97 uint32_t tpc_dbg_info_cmn_31_16 : 16, // [31:16] 98 tpc_dbg_info_cmn_15_0 : 16; // [15:0] 99 uint32_t tpc_dbg_info_chn1_15_0 : 16, // [31:16] 100 tpc_dbg_info_cmn_47_32 : 16; // [15:0] 101 uint32_t tpc_dbg_info_chn1_47_32 : 16, // [31:16] 102 tpc_dbg_info_chn1_31_16 : 16; // [15:0] 103 uint32_t tpc_dbg_info_chn1_79_64 : 16, // [31:16] 104 tpc_dbg_info_chn1_63_48 : 16; // [15:0] 105 uint32_t tpc_dbg_info_chn2_31_16 : 16, // [31:16] 106 tpc_dbg_info_chn2_15_0 : 16; // [15:0] 107 uint32_t tpc_dbg_info_chn2_63_48 : 16, // [31:16] 108 tpc_dbg_info_chn2_47_32 : 16; // [15:0] 109 struct phytx_abort_request_info phytx_abort_request_info_details; 110 uint16_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] 111 uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] 112 phytx_tx_end_sw_info_15_0 : 16; // [15:0] 113 uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] 114 phytx_tx_end_sw_info_47_32 : 16; // [15:0] 115 #endif 116 }; 117 118 119 /* Description SUCCESS 120 121 When set, protection response has been received 122 */ 123 124 #define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 125 #define TX_FES_STATUS_PROT_SUCCESS_LSB 0 126 #define TX_FES_STATUS_PROT_SUCCESS_MSB 0 127 #define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 128 129 130 /* Description PHYTX_PKT_END_INFO_VALID 131 132 All the fields originating from PHYTX_PKT_END TLV contain 133 valid info 134 */ 135 136 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 137 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 138 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 139 #define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 140 141 142 /* Description PHYTX_ABORT_REQUEST_INFO_VALID 143 144 Field Phytx_abort_request_info_details contains valid info 145 146 */ 147 148 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 149 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 150 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 151 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 152 153 154 /* Description RESERVED_0 155 156 <legal 0> 157 */ 158 159 #define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 160 #define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 161 #define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 162 #define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 163 164 165 /* Description PKT_TYPE 166 167 Field only valid when success is set 168 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 169 TLV. 170 171 Packet type: 172 <enum 0 dot11a>802.11a PPDU type 173 <enum 1 dot11b>802.11b PPDU type 174 <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type 175 <enum 3 dot11ac>802.11ac PPDU type 176 <enum 4 dot11ax>802.11ax PPDU type 177 <enum 5 dot11ba>802.11ba (WUR) PPDU type 178 <enum 6 dot11be>802.11be PPDU type 179 <enum 7 dot11az>802.11az (ranging) PPDU type 180 <enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported 181 & aborted) 182 */ 183 184 #define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 185 #define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 186 #define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 187 #define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 188 189 190 /* Description DOT11AX_SU_EXTENDED 191 192 Field only valid when success is set and pkt_type == 11ax 193 OR pkt_type == 11be 194 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 195 TLV. 196 197 When set, the 11ax or 11be reception was an extended range 198 SU 199 */ 200 201 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 202 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 203 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 204 #define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 205 206 207 /* Description RATE_MCS 208 209 Field only valid when success is set 210 Source of the info here is the 'RECEIVED_RESPONSE_INFO' 211 TLV. 212 213 For details, refer to MCS_TYPE description 214 Note: This is "rate" in case of 11a/11b 215 216 <legal all> 217 */ 218 219 #define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 220 #define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 221 #define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 222 #define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 223 224 225 /* Description FRAME_TYPE 226 227 Field only valid when 'success' is set. 228 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 229 230 231 802.11 frame type field 232 This field applies for 11ah as well. 233 */ 234 235 #define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 236 #define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 237 #define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 238 #define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 239 240 241 /* Description FRAME_SUBTYPE 242 243 Field only valid when 'success' is set. 244 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 245 246 247 802.11 frame subtype field 248 This field applies for 11ah as well. 249 */ 250 251 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 252 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 253 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 254 #define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 255 256 257 /* Description RX_PWR_MGMT 258 259 Field only valid when 'success' is set. 260 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 261 262 263 Power Management bit extracted from the header of the received 264 frame. 265 */ 266 267 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 268 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 269 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 270 #define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 271 272 273 /* Description STATUS 274 275 Field only valid when 'success' is set. 276 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 277 278 279 If set indicates that receive packet passed FCS check. 280 */ 281 282 #define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 283 #define TX_FES_STATUS_PROT_STATUS_LSB 39 284 #define TX_FES_STATUS_PROT_STATUS_MSB 39 285 #define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 286 287 288 /* Description DURATION_FIELD 289 290 Field only valid when 'success' is set. 291 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 292 293 294 The contents of the duration field of the received frame. 295 296 <legal all> 297 */ 298 299 #define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 300 #define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 301 #define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 302 #define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 303 304 305 /* Description RESERVED_1A 306 307 <legal 0> 308 */ 309 310 #define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 311 #define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 312 #define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 313 #define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 314 315 316 /* Description AGC_CBW 317 318 Field only valid when 'success' is set. 319 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 320 321 322 BW as detected by the AGC 323 324 <enum 0 20_mhz>20 Mhz BW 325 <enum 1 40_mhz>40 Mhz BW 326 <enum 2 80_mhz>80 Mhz BW 327 <enum 3 160_mhz>160 Mhz BW 328 <enum 4 320_mhz>320 Mhz BW 329 <enum 5 240_mhz>240 Mhz BW 330 */ 331 332 #define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 333 #define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 334 #define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 335 #define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 336 337 338 /* Description SERVICE_CBW 339 340 Field only valid when 'success' is set. 341 342 Source of the info here is the RECEIVED_RESPONSE_INFO TLV 343 344 345 This field reflects the BW extracted from the Serivce Field 346 for 11ac mode of operation . 347 348 This field is used in the context of Dynamic/Static BW evaluation 349 purposes in TxPCU 350 CBW field extracted from Service field 351 352 <enum 0 20_mhz>20 Mhz BW 353 <enum 1 40_mhz>40 Mhz BW 354 <enum 2 80_mhz>80 Mhz BW 355 <enum 3 160_mhz>160 Mhz BW 356 <enum 4 320_mhz>320 Mhz BW 357 <enum 5 240_mhz>240 Mhz BW 358 */ 359 360 #define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 361 #define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 362 #define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 363 #define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 364 365 366 /* Description START_OF_FRAME_TIMESTAMP_15_0 367 368 PHYTX_PKT_END info 369 370 Field only valid when PHYTX_PKT_END_info_valid is set 371 372 bits 15:0 of a 64 bit time stamp 373 Start of frame in the medium @960 MHz 374 <legal all> 375 */ 376 377 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 378 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 379 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 380 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 381 382 383 /* Description START_OF_FRAME_TIMESTAMP_31_16 384 385 PHYTX_PKT_END info 386 387 Field only valid when PHYTX_PKT_END_info_valid is set 388 389 bits 31:16 of a 64 bit time stamp 390 Start of frame in the medium @960 MHz 391 <legal all> 392 */ 393 394 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 395 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 396 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 397 #define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 398 399 400 /* Description END_OF_FRAME_TIMESTAMP_15_0 401 402 PHYTX_PKT_END info 403 404 Field only valid when PHYTX_PKT_END_info_valid is set 405 406 bits 15:0 of a 64 bit time stamp 407 End of frame in the medium @960 MHz 408 <legal all> 409 */ 410 411 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 412 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 413 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 414 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 415 416 417 /* Description END_OF_FRAME_TIMESTAMP_31_16 418 419 PHYTX_PKT_END info 420 421 Field only valid when PHYTX_PKT_END_info_valid is set 422 423 bits 31:16 of a 64 bit time stamp 424 End of frame in the medium @960 MHz 425 <legal all> 426 */ 427 428 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 429 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 430 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 431 #define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 432 433 434 /* Description TX_GROUP_DELAY 435 436 PHYTX_PKT_END info 437 438 Field only valid when PHYTX_PKT_END_info_valid is set 439 440 Group delay on TxTD+PHYRF path for this PPDU (packet BW 441 dependent), useful for RTT 442 443 Unit is 960MHz cycles. 444 <legal all> 445 */ 446 447 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 448 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 449 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 450 #define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff 451 452 453 /* Description TIMING_STATUS 454 455 PHYTX_PKT_END info 456 457 Field only valid when PHYTX_PKT_END_info_valid is set 458 459 <enum 0 No_tx_timing_request> The MAC did not request for 460 the transmission to start at a particular time 461 <enum 1 successful_tx_timing > MAC did request for transmission 462 to start at a particular time and PHY was able to do so. 463 464 <enum 2 tx_timing_not_honoured> PHY was not able to honour 465 the requested transmit time by the MAC. The transmission 466 started later, and field transmit_delay indicates how much 467 later. 468 <legal 0-2> 469 */ 470 471 #define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 472 #define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 473 #define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 474 #define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 475 476 477 /* Description DPDTRAIN_DONE 478 479 Field only valid when PHYTX_PKT_END_info_valid is set 480 481 For DPD Training packets, this bit is set to indicate that 482 DPD Training was successfully run to completion. Also 483 reused by Implicit BF Calibration Packets. This bit is intended 484 for debug purposes. 485 <legal all> 486 */ 487 488 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 489 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 490 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 491 #define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 492 493 494 /* Description RESERVED_4 495 496 PHYTX_PKT_END info 497 498 <legal 0> 499 */ 500 501 #define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 502 #define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 503 #define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 504 #define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 505 506 507 /* Description TRANSMIT_DELAY 508 509 PHYTX_PKT_END info 510 511 The number of 480 MHz clock cycles that the transmission 512 started after the actual requested transmit start time. 513 514 Value saturates at 0xFFFF 515 <legal all> 516 */ 517 518 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 519 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 520 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 521 #define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 522 523 524 /* Description TPC_DBG_INFO_CMN_15_0 525 526 PHYTX_PKT_END info 527 528 Field only valid when PHYTX_PKT_END_info_valid is set 529 530 Some TPC debug info that PHY can pass back to MAC FW 531 <legal all> 532 */ 533 534 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 535 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 536 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 537 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 538 539 540 /* Description TPC_DBG_INFO_CMN_31_16 541 542 PHYTX_PKT_END info 543 544 Field only valid when PHYTX_PKT_END_info_valid is set 545 546 Some TPC debug info that PHY can pass back to MAC FW 547 <legal all> 548 */ 549 550 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 551 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 552 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 553 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 554 555 556 /* Description TPC_DBG_INFO_CMN_47_32 557 558 PHYTX_PKT_END info 559 560 Field only valid when PHYTX_PKT_END_info_valid is set 561 562 Some TPC debug info that PHY can pass back to MAC FW 563 <legal all> 564 */ 565 566 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 567 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 568 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 569 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff 570 571 572 /* Description TPC_DBG_INFO_CHN1_15_0 573 574 PHYTX_PKT_END info 575 576 Field only valid when PHYTX_PKT_END_info_valid is set 577 578 Some per-chain TPC debug info for the first selected chain 579 that PHY can pass back to MAC FW 580 <legal all> 581 */ 582 583 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 584 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 585 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 586 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 587 588 589 /* Description TPC_DBG_INFO_CHN1_31_16 590 591 PHYTX_PKT_END info 592 593 Field only valid when PHYTX_PKT_END_info_valid is set 594 595 Some per-chain TPC debug info for the first selected chain 596 that PHY can pass back to MAC FW 597 <legal all> 598 */ 599 600 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 601 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 602 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 603 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 604 605 606 /* Description TPC_DBG_INFO_CHN1_47_32 607 608 PHYTX_PKT_END info 609 610 Field only valid when PHYTX_PKT_END_info_valid is set 611 612 Some per-chain TPC debug info for the first selected chain 613 that PHY can pass back to MAC FW 614 <legal all> 615 */ 616 617 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 618 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 619 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 620 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 621 622 623 /* Description TPC_DBG_INFO_CHN1_63_48 624 625 PHYTX_PKT_END info 626 627 Field only valid when PHYTX_PKT_END_info_valid is set 628 629 Some per-chain TPC debug info for the first selected chain 630 that PHY can pass back to MAC FW 631 <legal all> 632 */ 633 634 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 635 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 636 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 637 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff 638 639 640 /* Description TPC_DBG_INFO_CHN1_79_64 641 642 PHYTX_PKT_END info 643 644 Field only valid when PHYTX_PKT_END_info_valid is set 645 646 Some per-chain TPC debug info for the first selected chain 647 that PHY can pass back to MAC FW 648 <legal all> 649 */ 650 651 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 652 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 653 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 654 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 655 656 657 /* Description TPC_DBG_INFO_CHN2_15_0 658 659 PHYTX_PKT_END info 660 661 Field only valid when PHYTX_PKT_END_info_valid is set 662 663 Some per-chain TPC debug info for the second selected chain 664 that PHY can pass back to MAC FW 665 <legal all> 666 */ 667 668 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 669 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 670 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 671 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 672 673 674 /* Description TPC_DBG_INFO_CHN2_31_16 675 676 PHYTX_PKT_END info 677 678 Field only valid when PHYTX_PKT_END_info_valid is set 679 680 Some per-chain TPC debug info for the second selected chain 681 that PHY can pass back to MAC FW 682 <legal all> 683 */ 684 685 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 686 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 687 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 688 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 689 690 691 /* Description TPC_DBG_INFO_CHN2_47_32 692 693 PHYTX_PKT_END info 694 695 Field only valid when PHYTX_PKT_END_info_valid is set 696 697 Some per-chain TPC debug info for the second selected chain 698 that PHY can pass back to MAC FW 699 <legal all> 700 */ 701 702 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 703 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 704 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 705 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff 706 707 708 /* Description TPC_DBG_INFO_CHN2_63_48 709 710 PHYTX_PKT_END info 711 712 Field only valid when PHYTX_PKT_END_info_valid is set 713 714 Some per-chain TPC debug info for the second selected chain 715 that PHY can pass back to MAC FW 716 <legal all> 717 */ 718 719 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 720 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 721 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 722 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 723 724 725 /* Description TPC_DBG_INFO_CHN2_79_64 726 727 PHYTX_PKT_END info 728 729 Field only valid when PHYTX_PKT_END_info_valid is set 730 731 Some per-chain TPC debug info for the second selected chain 732 that PHY can pass back to MAC FW 733 <legal all> 734 */ 735 736 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 737 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 738 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 739 #define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 740 741 742 /* Description PHYTX_ABORT_REQUEST_INFO_DETAILS 743 744 Field only valid when PHYTX_ABORT_REQUEST_info_valid is 745 set 746 747 The reason why PHYTX is requested an abort 748 */ 749 750 751 /* Description PHYTX_ABORT_REASON 752 753 Reason for early termination of TX packet by the PHY 754 755 <enum_type PHYTX_ABORT_ENUM> 756 */ 757 758 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 759 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 760 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 761 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 762 763 764 /* Description USER_NUMBER 765 766 For some errors, the user for which this error was detected 767 can be indicated in this field. 768 <legal 0-36> 769 */ 770 771 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 772 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 773 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 774 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 775 776 777 /* Description RESERVED 778 779 <legal 0> 780 */ 781 782 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 783 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 784 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 785 #define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 786 787 788 /* Description PHYTX_TX_END_SW_INFO_15_0 789 790 PHYTX_PKT_END info 791 792 Field only valid when PHYTX_PKT_END_info_valid is set 793 794 Some PHY status data that PHY microcode can pass back to 795 MAC FW, for any future requests, e.g. any DMA download 796 time 797 <legal all> 798 */ 799 800 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 801 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 802 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 803 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 804 805 806 /* Description PHYTX_TX_END_SW_INFO_31_16 807 808 PHYTX_PKT_END info 809 810 Field only valid when PHYTX_PKT_END_info_valid is set 811 812 Some PHY status data that PHY microcode can pass back to 813 MAC FW, for any future requests, e.g. any DMA download 814 time 815 <legal all> 816 */ 817 818 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 819 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 820 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 821 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 822 823 824 /* Description PHYTX_TX_END_SW_INFO_47_32 825 826 PHYTX_PKT_END info 827 828 Field only valid when PHYTX_PKT_END_info_valid is set 829 830 Some PHY status data that PHY microcode can pass back to 831 MAC FW, for any future requests, e.g. any DMA download 832 time 833 <legal all> 834 */ 835 836 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 837 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 838 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 839 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 840 841 842 /* Description PHYTX_TX_END_SW_INFO_63_48 843 844 PHYTX_PKT_END info 845 846 Field only valid when PHYTX_PKT_END_info_valid is set 847 848 Some PHY status data that PHY microcode can pass back to 849 MAC FW, for any future requests, e.g. any DMA download 850 time 851 <legal all> 852 */ 853 854 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 855 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 856 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 857 #define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 858 859 860 861 #endif // TX_FES_STATUS_PROT 862