1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TX_MPDU_START_H_ 18 #define _TX_MPDU_START_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TX_MPDU_START 10 23 24 #define NUM_OF_QWORDS_TX_MPDU_START 5 25 26 27 struct tx_mpdu_start { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t mpdu_length : 14, // [13:0] 30 frame_not_from_tqm : 1, // [14:14] 31 vht_control_present : 1, // [15:15] 32 mpdu_header_length : 8, // [23:16] 33 retry_count : 7, // [30:24] 34 wds : 1; // [31:31] 35 uint32_t pn_31_0 : 32; // [31:0] 36 uint32_t pn_47_32 : 16, // [15:0] 37 mpdu_sequence_number : 12, // [27:16] 38 raw_already_encrypted : 1, // [28:28] 39 frame_type : 2, // [30:29] 40 txdma_dropped_mpdu_warning : 1; // [31:31] 41 uint32_t iv_byte_0 : 8, // [7:0] 42 iv_byte_1 : 8, // [15:8] 43 iv_byte_2 : 8, // [23:16] 44 iv_byte_3 : 8; // [31:24] 45 uint32_t iv_byte_4 : 8, // [7:0] 46 iv_byte_5 : 8, // [15:8] 47 iv_byte_6 : 8, // [23:16] 48 iv_byte_7 : 8; // [31:24] 49 uint32_t iv_byte_8 : 8, // [7:0] 50 iv_byte_9 : 8, // [15:8] 51 iv_byte_10 : 8, // [23:16] 52 iv_byte_11 : 8; // [31:24] 53 uint32_t iv_byte_12 : 8, // [7:0] 54 iv_byte_13 : 8, // [15:8] 55 iv_byte_14 : 8, // [23:16] 56 iv_byte_15 : 8; // [31:24] 57 uint32_t iv_byte_16 : 8, // [7:0] 58 iv_byte_17 : 8, // [15:8] 59 iv_len : 5, // [20:16] 60 icv_len : 5, // [25:21] 61 vht_control_offset : 6; // [31:26] 62 uint32_t mpdu_type : 1, // [0:0] 63 transmit_bw_restriction : 1, // [1:1] 64 allowed_transmit_bw : 4, // [5:2] 65 tx_notify_frame : 3, // [8:6] 66 reserved_8a : 23; // [31:9] 67 uint32_t tlv64_padding : 32; // [31:0] 68 #else 69 uint32_t wds : 1, // [31:31] 70 retry_count : 7, // [30:24] 71 mpdu_header_length : 8, // [23:16] 72 vht_control_present : 1, // [15:15] 73 frame_not_from_tqm : 1, // [14:14] 74 mpdu_length : 14; // [13:0] 75 uint32_t pn_31_0 : 32; // [31:0] 76 uint32_t txdma_dropped_mpdu_warning : 1, // [31:31] 77 frame_type : 2, // [30:29] 78 raw_already_encrypted : 1, // [28:28] 79 mpdu_sequence_number : 12, // [27:16] 80 pn_47_32 : 16; // [15:0] 81 uint32_t iv_byte_3 : 8, // [31:24] 82 iv_byte_2 : 8, // [23:16] 83 iv_byte_1 : 8, // [15:8] 84 iv_byte_0 : 8; // [7:0] 85 uint32_t iv_byte_7 : 8, // [31:24] 86 iv_byte_6 : 8, // [23:16] 87 iv_byte_5 : 8, // [15:8] 88 iv_byte_4 : 8; // [7:0] 89 uint32_t iv_byte_11 : 8, // [31:24] 90 iv_byte_10 : 8, // [23:16] 91 iv_byte_9 : 8, // [15:8] 92 iv_byte_8 : 8; // [7:0] 93 uint32_t iv_byte_15 : 8, // [31:24] 94 iv_byte_14 : 8, // [23:16] 95 iv_byte_13 : 8, // [15:8] 96 iv_byte_12 : 8; // [7:0] 97 uint32_t vht_control_offset : 6, // [31:26] 98 icv_len : 5, // [25:21] 99 iv_len : 5, // [20:16] 100 iv_byte_17 : 8, // [15:8] 101 iv_byte_16 : 8; // [7:0] 102 uint32_t reserved_8a : 23, // [31:9] 103 tx_notify_frame : 3, // [8:6] 104 allowed_transmit_bw : 4, // [5:2] 105 transmit_bw_restriction : 1, // [1:1] 106 mpdu_type : 1; // [0:0] 107 uint32_t tlv64_padding : 32; // [31:0] 108 #endif 109 }; 110 111 112 /* Description MPDU_LENGTH 113 114 Consumer: TXOLE/CRYPTO/TXPCU 115 Producer: TXDMA 116 117 Expected Length of the entire MPDU, which includes all MSDUs 118 within the MPDU and all OLE and Crypto processing. This 119 length includes the FCS field. 120 */ 121 122 #define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 123 #define TX_MPDU_START_MPDU_LENGTH_LSB 0 124 #define TX_MPDU_START_MPDU_LENGTH_MSB 13 125 #define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff 126 127 128 /* Description FRAME_NOT_FROM_TQM 129 130 When set, TXPCU shall not take this frame into account for 131 indicating to TQM how many frames from it's queue got transmitted. 132 133 134 TXDMA gets this field from the TX_MSDU_DETAILS STRUCT (of 135 the first MSDU in the MPDU) in the MSDU link descriptor. 136 137 138 SW sets this bit (in TX_MSDU_DETAILS STRUCT) when it generates 139 a frame outside of the TQM path and that frame can be intermingled 140 with the other frames from the TQM. For example a trigger 141 frame embedded or put in front of data frames from TQM 142 within the same A-MPDU. For this SW generated frame, TXPCU 143 shall not include this frame in the transmit frame count 144 that is reported to TQM as that would result in incorrect 145 reporting to TQM. 146 147 <legal all> 148 */ 149 150 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 151 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 152 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 153 #define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 154 155 156 /* Description VHT_CONTROL_PRESENT 157 158 TXOLE sets this bit when it added 4 placeholder bytes for 159 VHT-CONTROL field in the MPDU header. 160 161 For RAW frames, OLE will set this bit and compute vht_control_offset 162 when the order bit and QoS bit in frame_control field are 163 set to 1. For RAW management frame, this bit will be set 164 if order bit is set to 1. 165 166 Used by TXPCU, to find out if it needs to overwrite the 167 HE-CONTROL field. 168 <legal all> 169 */ 170 171 #define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 172 #define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 173 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 174 #define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 175 176 177 /* Description MPDU_HEADER_LENGTH 178 179 This field is filled in by the OLE 180 Used by PCU, This prevents PCU from having to do this again 181 (in the same way)) 182 */ 183 184 #define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 185 #define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 186 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 187 #define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 188 189 190 /* Description RETRY_COUNT 191 192 Consumer: TXOLE/TXPCU 193 Producer: TXDMA 194 195 The number of times the frame is transmitted 196 <legal all> 197 */ 198 199 #define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 200 #define TX_MPDU_START_RETRY_COUNT_LSB 24 201 #define TX_MPDU_START_RETRY_COUNT_MSB 30 202 #define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 203 204 205 /* Description WDS 206 207 If set the current packet is 4-address frame. 208 209 Required because an aggregate can include some frames with 210 3 address format and other frames with 4 address format. 211 Used by the OLE during encapsulation. 212 213 TXDMA sets this when wds in the extension descriptor is 214 set. 215 216 If no extension descriptor is used for this MPDU, TXDMA 217 gets the setting for this bit from a control register in 218 TXDMA 219 <legal all> 220 */ 221 222 #define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 223 #define TX_MPDU_START_WDS_LSB 31 224 #define TX_MPDU_START_WDS_MSB 31 225 #define TX_MPDU_START_WDS_MASK 0x0000000080000000 226 227 228 /* Description PN_31_0 229 230 Consumer: TXOLE 231 Producer: TXDMA 232 233 Bits 31 - 0 for the Packet Number used by encryption 234 <legal all> 235 */ 236 237 #define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 238 #define TX_MPDU_START_PN_31_0_LSB 32 239 #define TX_MPDU_START_PN_31_0_MSB 63 240 #define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 241 242 243 /* Description PN_47_32 244 245 Consumer: TXOLE 246 Producer: TXDMA 247 248 Bits 47 - 32 for the Packet Number used by encryption 249 <legal all> 250 */ 251 252 #define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 253 #define TX_MPDU_START_PN_47_32_LSB 0 254 #define TX_MPDU_START_PN_47_32_MSB 15 255 #define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff 256 257 258 /* Description MPDU_SEQUENCE_NUMBER 259 260 Consumer: TXOLE 261 Producer: TXDMA 262 263 Sequence number assigned to this MPDU 264 <legal all> 265 */ 266 267 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 268 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 269 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 270 #define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 271 272 273 /* Description RAW_ALREADY_ENCRYPTED 274 275 Consumer: CRYPTO 276 Producer: TXDMA 277 278 If set it indicates that the RAW MPDU has already been encrypted 279 and does not require HW encryption. If clear and if the 280 frame control indicates that this is a "protected" MPDU 281 and the peer key type indicates a cipher type then the 282 HW is expected to encrypt this packet. 283 <legal all> 284 */ 285 286 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 287 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 288 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 289 #define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 290 291 292 /* Description FRAME_TYPE 293 294 Consumer: TXMON 295 Producer: TXOLE 296 297 802.11 frame type field 298 299 TXDMA fills this as zero and TXOLE overwrites it. 300 301 <legal all> 302 */ 303 304 #define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 305 #define TX_MPDU_START_FRAME_TYPE_LSB 29 306 #define TX_MPDU_START_FRAME_TYPE_MSB 30 307 #define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 308 309 310 /* Description TXDMA_DROPPED_MPDU_WARNING 311 312 Consumer: FW 313 Producer: TXDMA 314 315 Indication to TXPCU to indicate to FW a warning that Tx 316 DMA has dropped MPDUs due to SFM FIFO full condition 317 <legal all> 318 */ 319 320 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 321 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 322 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 323 #define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 324 325 326 /* Description IV_BYTE_0 327 328 Byte 0 of the IV field of the MPDU 329 Based on the Encryption type the iv_byte_0 takes the appropriate 330 meaning. For IV formats, refer to the crypto MLDR document 331 332 */ 333 334 #define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 335 #define TX_MPDU_START_IV_BYTE_0_LSB 32 336 #define TX_MPDU_START_IV_BYTE_0_MSB 39 337 #define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 338 339 340 /* Description IV_BYTE_1 341 342 Byte 1 of the IV field of the MPDU 343 Based on the Encryption type the iv_byte_1 takes the appropriate 344 meaning. For IV formats, refer to the crypto MLDR document 345 346 */ 347 348 #define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 349 #define TX_MPDU_START_IV_BYTE_1_LSB 40 350 #define TX_MPDU_START_IV_BYTE_1_MSB 47 351 #define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 352 353 354 /* Description IV_BYTE_2 355 356 Byte 2 of the IV field of the MDPU 357 Based on the Encryption type the iv_byte_2 takes the appropriate 358 meaning. For IV formats, refer to the crypto MLDR document 359 360 */ 361 362 #define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 363 #define TX_MPDU_START_IV_BYTE_2_LSB 48 364 #define TX_MPDU_START_IV_BYTE_2_MSB 55 365 #define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 366 367 368 /* Description IV_BYTE_3 369 370 Byte 3 of the IV field of the MPDU 371 Based on the Encryption type the iv_byte_3 takes the appropriate 372 meaning. For IV formats, refer to the crypto MLDR document 373 374 */ 375 376 #define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 377 #define TX_MPDU_START_IV_BYTE_3_LSB 56 378 #define TX_MPDU_START_IV_BYTE_3_MSB 63 379 #define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 380 381 382 /* Description IV_BYTE_4 383 384 Byte 4 of the IV field of the MPDU 385 Based on the Encryption type the iv_byte_4 takes the appropriate 386 meaning. For IV formats, refer to the crypto MLDR document 387 388 */ 389 390 #define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 391 #define TX_MPDU_START_IV_BYTE_4_LSB 0 392 #define TX_MPDU_START_IV_BYTE_4_MSB 7 393 #define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff 394 395 396 /* Description IV_BYTE_5 397 398 Byte 5 of the IV field of the MPDU 399 Based on the Encryption type the iv_byte_5 takes the appropriate 400 meaning. For IV formats, refer to the crypto MLDR document 401 402 */ 403 404 #define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 405 #define TX_MPDU_START_IV_BYTE_5_LSB 8 406 #define TX_MPDU_START_IV_BYTE_5_MSB 15 407 #define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 408 409 410 /* Description IV_BYTE_6 411 412 Byte 6 of the IV field of the MDPU 413 Based on the Encryption type the iv_byte_6 takes the appropriate 414 meaning. For IV formats, refer to the crypto MLDR document 415 416 */ 417 418 #define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 419 #define TX_MPDU_START_IV_BYTE_6_LSB 16 420 #define TX_MPDU_START_IV_BYTE_6_MSB 23 421 #define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 422 423 424 /* Description IV_BYTE_7 425 426 Byte 7 of the IV field of the MPDU 427 Based on the Encryption type the iv_byte_7 takes the appropriate 428 meaning. For IV formats, refer to the crypto MLDR document 429 430 */ 431 432 #define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 433 #define TX_MPDU_START_IV_BYTE_7_LSB 24 434 #define TX_MPDU_START_IV_BYTE_7_MSB 31 435 #define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 436 437 438 /* Description IV_BYTE_8 439 440 Byte 8 of the IV field of the MPDU 441 Based on the Encryption type the iv_byte_8 takes the appropriate 442 meaning. For IV formats, refer to the crypto MLDR document 443 444 */ 445 446 #define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 447 #define TX_MPDU_START_IV_BYTE_8_LSB 32 448 #define TX_MPDU_START_IV_BYTE_8_MSB 39 449 #define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 450 451 452 /* Description IV_BYTE_9 453 454 Byte 9 of the IV field of the MPDU 455 Based on the Encryption type the iv_byte_9 takes the appropriate 456 meaning. For IV formats, refer to the crypto MLDR document 457 458 */ 459 460 #define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 461 #define TX_MPDU_START_IV_BYTE_9_LSB 40 462 #define TX_MPDU_START_IV_BYTE_9_MSB 47 463 #define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 464 465 466 /* Description IV_BYTE_10 467 468 Byte 10 of the IV field of the MDPU 469 Based on the Encryption type the iv_byte_10 takes the appropriate 470 meaning. For IV formats, refer to the crypto MLDR document 471 472 */ 473 474 #define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 475 #define TX_MPDU_START_IV_BYTE_10_LSB 48 476 #define TX_MPDU_START_IV_BYTE_10_MSB 55 477 #define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 478 479 480 /* Description IV_BYTE_11 481 482 Byte 11 of the IV field of the MPDU 483 Based on the Encryption type the iv_byte_11 takes the appropriate 484 meaning. For IV formats, refer to the crypto MLDR document 485 486 */ 487 488 #define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 489 #define TX_MPDU_START_IV_BYTE_11_LSB 56 490 #define TX_MPDU_START_IV_BYTE_11_MSB 63 491 #define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 492 493 494 /* Description IV_BYTE_12 495 496 Byte 8 of the IV field of the MPDU 497 Based on the Encryption type the iv_byte_12 takes the appropriate 498 meaning. For IV formats, refer to the crypto MLDR document 499 500 */ 501 502 #define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 503 #define TX_MPDU_START_IV_BYTE_12_LSB 0 504 #define TX_MPDU_START_IV_BYTE_12_MSB 7 505 #define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff 506 507 508 /* Description IV_BYTE_13 509 510 Byte 9 of the IV field of the MPDU 511 Based on the Encryption type the iv_byte_13 takes the appropriate 512 meaning. For IV formats, refer to the crypto MLDR document 513 514 */ 515 516 #define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 517 #define TX_MPDU_START_IV_BYTE_13_LSB 8 518 #define TX_MPDU_START_IV_BYTE_13_MSB 15 519 #define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 520 521 522 /* Description IV_BYTE_14 523 524 Byte 10 of the IV field of the MDPU 525 Based on the Encryption type the iv_byte_14 takes the appropriate 526 meaning. For IV formats, refer to the crypto MLDR document 527 528 */ 529 530 #define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 531 #define TX_MPDU_START_IV_BYTE_14_LSB 16 532 #define TX_MPDU_START_IV_BYTE_14_MSB 23 533 #define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 534 535 536 /* Description IV_BYTE_15 537 538 Byte 11 of the IV field of the MPDU 539 Based on the Encryption type the iv_byte_15 takes the appropriate 540 meaning. For IV formats, refer to the crypto MLDR document 541 542 */ 543 544 #define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 545 #define TX_MPDU_START_IV_BYTE_15_LSB 24 546 #define TX_MPDU_START_IV_BYTE_15_MSB 31 547 #define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 548 549 550 /* Description IV_BYTE_16 551 552 Byte 8 of the IV field of the MPDU 553 Based on the Encryption type the iv_byte_16 takes the appropriate 554 meaning. For IV formats, refer to the crypto MLDR document 555 556 */ 557 558 #define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 559 #define TX_MPDU_START_IV_BYTE_16_LSB 32 560 #define TX_MPDU_START_IV_BYTE_16_MSB 39 561 #define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 562 563 564 /* Description IV_BYTE_17 565 566 Byte 9 of the IV field of the MPDU 567 Based on the Encryption type the iv_byte_17 takes the appropriate 568 meaning. For IV formats, refer to the crypto MLDR document 569 570 */ 571 572 #define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 573 #define TX_MPDU_START_IV_BYTE_17_LSB 40 574 #define TX_MPDU_START_IV_BYTE_17_MSB 47 575 #define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 576 577 578 /* Description IV_LEN 579 580 Length of the IV field generated by Tx OLE 581 */ 582 583 #define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 584 #define TX_MPDU_START_IV_LEN_LSB 48 585 #define TX_MPDU_START_IV_LEN_MSB 52 586 #define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 587 588 589 /* Description ICV_LEN 590 591 Length of the ICV field generated by Tx OLE. OLE will insert 592 zeros in the ICV field when it pushes a frame 593 */ 594 595 #define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 596 #define TX_MPDU_START_ICV_LEN_LSB 53 597 #define TX_MPDU_START_ICV_LEN_MSB 57 598 #define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 599 600 601 /* Description VHT_CONTROL_OFFSET 602 603 Field only valid when vht_control_present is set. 604 605 Field filled in by TXOLE, used by TXPCU 606 607 The starting byte number of the VHT control field in the 608 header 609 <legal all> 610 */ 611 612 #define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 613 #define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 614 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 615 #define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 616 617 618 /* Description MPDU_TYPE 619 620 Indicates the type of MPDU that OLE will generate: 621 622 <enum 0 mpdu_type_basic> This MPDU is not in the A-MSDU 623 format (meaning there is no A-MSDU delimeter present) if 624 there is only 1 MSDU in the MPDU. When there are multiple 625 MSDUs in the MPDU, there is no choice, and the MSDUs within 626 the MPDU shall all have A-MSDU delimiters in front of them. 627 628 <enum 1 mpdu_type_amsdu> The MSDUs within the MPDU will 629 all have to be in the A-MSDU format, even if there is just 630 a single MSDU embedded in the MPDU. In other words, there 631 is always an A-MSDU delimiter in front of the MSDU(s) in 632 the MPDU. 633 <legal all> 634 */ 635 636 #define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 637 #define TX_MPDU_START_MPDU_TYPE_LSB 0 638 #define TX_MPDU_START_MPDU_TYPE_MSB 0 639 #define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 640 641 642 /* Description TRANSMIT_BW_RESTRICTION 643 644 Consumer: TXPCU 645 Producer: TXDMA 646 647 1'b0: This is a normal frame and there are no restrictions 648 on the BW that this frame can be transmitted on. 649 650 1'b1: This MPDU is only allowed to be transmitted at certain 651 BWs. The one and only allowed BW is indicated in field 652 allowed_transmit_bw 653 When TXPCU has made a BW selection and then encounters this 654 frame, the frame will be dropped and TXPCU will continue 655 transmitting the next frame (assuming there is no BW restriction 656 on that one) 657 <legal all> 658 */ 659 660 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 661 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 662 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 663 #define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 664 665 666 /* Description ALLOWED_TRANSMIT_BW 667 668 Consumer: TXPCU 669 Producer: TXDMA 670 671 Field only valid when transmit_bw_restriction is set 672 673 TXDMA gets this from the three or four upper bits of the 674 "Sw_buffer_cookie" field from the TX_MPDU_DETAILS STRUCT 675 676 677 In case of NON punctured transmission: 678 allowed_transmit_bw[2:0] = 3'b000: 20 MHz TX only 679 allowed_transmit_bw[2:0] = 3'b001: 40 MHz TX only 680 allowed_transmit_bw[2:0] = 3'b010: 80 MHz TX only 681 allowed_transmit_bw[2:0] = 3'b011: 160 MHz TX only 682 allowed_transmit_bw[2:0] = 3'b100: 240 MHz TX only 683 allowed_transmit_bw[2:0] = 3'b101: 320 MHz TX only 684 allowed_transmit_bw[2:1] = 2'b11: reserved 685 686 In case of punctured transmission: 687 allowed_transmit_bw[3:0] = 4'b0000: pattern 0 only 688 allowed_transmit_bw[3:0] = 4'b0001: pattern 1 only 689 allowed_transmit_bw[3:0] = 4'b0010: pattern 2 only 690 allowed_transmit_bw[3:0] = 4'b0011: pattern 3 only 691 allowed_transmit_bw[3:0] = 4'b0100: pattern 4 only 692 allowed_transmit_bw[3:0] = 4'b0101: pattern 5 only 693 allowed_transmit_bw[3:0] = 4'b0110: pattern 6 only 694 allowed_transmit_bw[3:0] = 4'b0111: pattern 7 only 695 allowed_transmit_bw[3:0] = 4'b1000: pattern 8 only 696 allowed_transmit_bw[3:0] = 4'b1001: pattern 9 only 697 allowed_transmit_bw[3:0] = 4'b1010: pattern 10 only 698 allowed_transmit_bw[3:0] = 4'b1011: pattern 11 only 699 allowed_transmit_bw[3:2] = 2'b11: reserved 700 701 Note: a punctured transmission is indicated by the presence 702 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 703 704 <legal 0-11> 705 */ 706 707 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 708 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 709 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 710 #define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c 711 712 713 /* Description TX_NOTIFY_FRAME 714 715 Consumer: TQM/PDG/TXOLE 716 Producer: FW/SW 717 718 When clear, this frame does not require any special handling. 719 720 721 When set, this MPDU contains an MSDU with the 'FW_tx_notify_frame' 722 field set. 723 This means this MPDU is a special frame that requires special 724 handling in TQM. 725 726 Note that FW/SW shall always set the amsdu_not_allowed bit 727 in 'TX_MSDU_DETAILS' for any notify frame. 728 729 <enum 0 NO_TX_NOTIFY> Not a notify frame 730 <enum 1 TX_HARD_NOTIFY> 731 <enum 2 TX_SOFT_NOTIFY> 732 <enum 3 TX_SEMI_HARD_NOTIFY> 733 <enum 4 TX_SEMI_HARD_NOTIFY_CURR_RATE> Rate cannot be overridden 734 by PDG 735 <legal 0-4> 736 */ 737 738 #define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 739 #define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 740 #define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 741 #define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 742 743 744 /* Description RESERVED_8A 745 746 Bit 9: self_gen: 747 748 Field only used in the MAC-flexibility feature in TXPCU 749 and PHY microcode 750 751 0: Indicates a normal data MPDU 752 1: Indicates a self-gen MPDU 753 754 <legal 0-1> 755 */ 756 757 #define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 758 #define TX_MPDU_START_RESERVED_8A_LSB 9 759 #define TX_MPDU_START_RESERVED_8A_MSB 31 760 #define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 761 762 763 /* Description TLV64_PADDING 764 765 Automatic DWORD padding inserted while converting TLV32 766 to TLV64 for 64 bit ARCH 767 <legal 0> 768 */ 769 770 #define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 771 #define TX_MPDU_START_TLV64_PADDING_LSB 32 772 #define TX_MPDU_START_TLV64_PADDING_MSB 63 773 #define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 774 775 776 777 #endif // TX_MPDU_START 778