1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TX_PEER_ENTRY_H_ 18 #define _TX_PEER_ENTRY_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_TX_PEER_ENTRY 18 23 24 #define NUM_OF_QWORDS_TX_PEER_ENTRY 9 25 26 27 struct tx_peer_entry { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t mac_addr_a_31_0 : 32; // [31:0] 30 uint32_t mac_addr_a_47_32 : 16, // [15:0] 31 mac_addr_b_15_0 : 16; // [31:16] 32 uint32_t mac_addr_b_47_16 : 32; // [31:0] 33 uint32_t use_ad_b : 1, // [0:0] 34 strip_insert_vlan_inner : 1, // [1:1] 35 strip_insert_vlan_outer : 1, // [2:2] 36 vlan_llc_mode : 1, // [3:3] 37 key_type : 4, // [7:4] 38 a_msdu_wds_ad3_ad4 : 3, // [10:8] 39 ignore_hard_filters : 1, // [11:11] 40 ignore_soft_filters : 1, // [12:12] 41 epd_output : 1, // [13:13] 42 wds : 1, // [14:14] 43 insert_or_strip : 1, // [15:15] 44 sw_filter_id : 16; // [31:16] 45 uint32_t temporal_key_31_0 : 32; // [31:0] 46 uint32_t temporal_key_63_32 : 32; // [31:0] 47 uint32_t temporal_key_95_64 : 32; // [31:0] 48 uint32_t temporal_key_127_96 : 32; // [31:0] 49 uint32_t temporal_key_159_128 : 32; // [31:0] 50 uint32_t temporal_key_191_160 : 32; // [31:0] 51 uint32_t temporal_key_223_192 : 32; // [31:0] 52 uint32_t temporal_key_255_224 : 32; // [31:0] 53 uint32_t sta_partial_aid : 11, // [10:0] 54 transmit_vif : 4, // [14:11] 55 block_this_user : 1, // [15:15] 56 mesh_amsdu_mode : 2, // [17:16] 57 use_qos_alt_mute_mask : 1, // [18:18] 58 dl_ul_direction : 1, // [19:19] 59 reserved_12 : 12; // [31:20] 60 uint32_t insert_vlan_outer_tci : 16, // [15:0] 61 insert_vlan_inner_tci : 16; // [31:16] 62 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 63 uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] 64 multi_link_addr_ad2_15_0 : 16; // [31:16] 65 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 66 uint32_t multi_link_addr_crypto_enable : 1, // [0:0] 67 reserved_17a : 15, // [15:1] 68 sw_peer_id : 16; // [31:16] 69 #else 70 uint32_t mac_addr_a_31_0 : 32; // [31:0] 71 uint32_t mac_addr_b_15_0 : 16, // [31:16] 72 mac_addr_a_47_32 : 16; // [15:0] 73 uint32_t mac_addr_b_47_16 : 32; // [31:0] 74 uint32_t sw_filter_id : 16, // [31:16] 75 insert_or_strip : 1, // [15:15] 76 wds : 1, // [14:14] 77 epd_output : 1, // [13:13] 78 ignore_soft_filters : 1, // [12:12] 79 ignore_hard_filters : 1, // [11:11] 80 a_msdu_wds_ad3_ad4 : 3, // [10:8] 81 key_type : 4, // [7:4] 82 vlan_llc_mode : 1, // [3:3] 83 strip_insert_vlan_outer : 1, // [2:2] 84 strip_insert_vlan_inner : 1, // [1:1] 85 use_ad_b : 1; // [0:0] 86 uint32_t temporal_key_31_0 : 32; // [31:0] 87 uint32_t temporal_key_63_32 : 32; // [31:0] 88 uint32_t temporal_key_95_64 : 32; // [31:0] 89 uint32_t temporal_key_127_96 : 32; // [31:0] 90 uint32_t temporal_key_159_128 : 32; // [31:0] 91 uint32_t temporal_key_191_160 : 32; // [31:0] 92 uint32_t temporal_key_223_192 : 32; // [31:0] 93 uint32_t temporal_key_255_224 : 32; // [31:0] 94 uint32_t reserved_12 : 12, // [31:20] 95 dl_ul_direction : 1, // [19:19] 96 use_qos_alt_mute_mask : 1, // [18:18] 97 mesh_amsdu_mode : 2, // [17:16] 98 block_this_user : 1, // [15:15] 99 transmit_vif : 4, // [14:11] 100 sta_partial_aid : 11; // [10:0] 101 uint32_t insert_vlan_inner_tci : 16, // [31:16] 102 insert_vlan_outer_tci : 16; // [15:0] 103 uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] 104 uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] 105 multi_link_addr_ad1_47_32 : 16; // [15:0] 106 uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] 107 uint32_t sw_peer_id : 16, // [31:16] 108 reserved_17a : 15, // [15:1] 109 multi_link_addr_crypto_enable : 1; // [0:0] 110 #endif 111 }; 112 113 114 /* Description MAC_ADDR_A_31_0 115 116 Consumer: TX OLE 117 Producer: SW 118 119 Lower 32 bits of the MAC address A used by HW for encapsulating 120 802.11 121 <legal all> 122 */ 123 124 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 125 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 126 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 127 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff 128 129 130 /* Description MAC_ADDR_A_47_32 131 132 Consumer: TX OLE 133 Producer: SW 134 135 Upper 16 bits of the MAC address A used by HW for encapsulating 136 802.11 137 <legal all> 138 */ 139 140 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 141 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 142 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 143 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 144 145 146 /* Description MAC_ADDR_B_15_0 147 148 Consumer: TX OLE 149 Producer: SW 150 151 Lower 16 bits of the MAC address B used by HW for encapsulating 152 802.11 153 <legal all> 154 */ 155 156 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 157 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 158 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 159 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 160 161 162 /* Description MAC_ADDR_B_47_16 163 164 Consumer: TX OLE 165 Producer: SW 166 167 Upper 32 bits of the MAC address B used by HW for encapsulating 168 802.11 169 <legal all> 170 */ 171 172 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 173 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 174 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 175 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff 176 177 178 /* Description USE_AD_B 179 180 Consumer: TX OLE 181 Producer: SW 182 183 The bit is only evaluated when this MSDU is the first MSDU 184 in an MPDU. For other MSDUs this bit setting is ignored. 185 186 It is part of the sw_msdu_param coming from the QM ADD frame 187 command. 188 189 Normally in AP mode the DA address is used as the RA. This 190 is normally fine but the use_ad_b bit should be set when 191 DA is a multicast/broadcast address but we want to send 192 this packet using the destination STA address which will 193 be held in the mac_addr_b field of the peer descriptor. 194 195 <legal all> 196 */ 197 198 #define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 199 #define TX_PEER_ENTRY_USE_AD_B_LSB 32 200 #define TX_PEER_ENTRY_USE_AD_B_MSB 32 201 #define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 202 203 204 /* Description STRIP_INSERT_VLAN_INNER 205 206 Consumer: TX OLE 207 Producer: SW 208 209 Strip or insert C-VLAN during encapsulation. 210 Insert_or_strip determines whether C-VLAN is to be stripped 211 or inserted. 212 <legal all> 213 */ 214 215 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 216 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 217 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 218 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 219 220 221 /* Description STRIP_INSERT_VLAN_OUTER 222 223 Consumer: TX OLE 224 Producer: SW 225 226 Strip or insert S-VLAN during encapsulation. 227 Insert or strip determines whether S-VLAN is to be stripped 228 or inserted. 229 <legal all> 230 */ 231 232 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 233 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 234 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 235 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 236 237 238 /* Description VLAN_LLC_MODE 239 240 Consumer: TX OLE 241 Producer: SW 242 243 If set encapsulate/decapsulate using the Scorpion compatible 244 VLAN LLC format 245 */ 246 247 #define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 248 #define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 249 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 250 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 251 252 253 /* Description KEY_TYPE 254 255 Consumer: TX OLE, TX CRYPTO 256 Producer: SW 257 258 The key_type indicates the cipher suite corresponding to 259 this peer entry: 260 <enum 0 wep_40> WEP 40-bit 261 <enum 1 wep_104> WEP 104-bit 262 <enum 2 tkip_no_mic> TKIP without MIC 263 <enum 3 wep_128> WEP 128-bit 264 <enum 4 tkip_with_mic> TKIP with MIC 265 <enum 5 wapi> WAPI 266 <enum 6 aes_ccmp_128> AES CCMP 128 267 <enum 7 no_cipher> No crypto 268 <enum 8 aes_ccmp_256> AES CCMP 256 269 <enum 9 aes_gcmp_128> AES GCMP 128 270 <enum 10 aes_gcmp_256> AES GCMP 256 271 <enum 11 wapi_gcm_sm4> WAPI GCM SM4 272 273 <enum 12 wep_varied_width> DO NOT USE. This Key type ONLY 274 to be used for RX side 275 276 <legal 0-12> 277 */ 278 279 #define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 280 #define TX_PEER_ENTRY_KEY_TYPE_LSB 36 281 #define TX_PEER_ENTRY_KEY_TYPE_MSB 39 282 #define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 283 284 285 /* Description A_MSDU_WDS_AD3_AD4 286 287 Consumer: TX OLE 288 Producer: SW 289 290 Determines the selection of AD3 and AD4 for A-MSDU 4 address 291 frames (WDS): 292 <enum 0 ad3_a__ad4_a> AD3 = AD_A, AD4 = AD_A 293 <enum 1 ad3_a__ad4_b> AD3 = AD_A, AD4 = AD_B 294 <enum 2 ad3_b__ad4_a> AD3 = AD_B, AD4 = AD_A 295 <enum 3 ad3_b__ad4_b> AD3 = AD_B, AD4 = AD_B 296 <enum 4 ad3_da__ad4_sa> AD3 = DA, AD4 = SA 297 <legal 0-4> 298 */ 299 300 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 301 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 302 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 303 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 304 305 306 /* Description IGNORE_HARD_FILTERS 307 308 SW can program this bit to 0x1 to ignore HARD filter conditions 309 and HWSCH will proceed with transmission, even if the HARD 310 filter bit is set in Filter LUT. 311 Note that SOFT filter conditions will filter the command, 312 even if this bit is set and ignore_soft_filters is not set 313 314 For filtering all frames marked in the Filter LUT, both 315 ignore_soft_filters and ignore_hard_filters should be set 316 317 <legal all> 318 */ 319 320 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 321 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 322 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 323 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 324 325 326 /* Description IGNORE_SOFT_FILTERS 327 328 SW can program this bit to 0x1 to ignore SOFT filter conditions 329 and HWSCH will proceed with transmission, even if the SOFT 330 filter bit is set in Filter LUT. 331 Note that HARD filter conditions will filter the command, 332 even if this bit is set and ignore_hard_filters is not set 333 334 For filtering all frames marked in the Filter LUT, both 335 ignore_soft_filters and ignore_hard_filters should be set 336 337 338 <legal all> 339 */ 340 341 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 342 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 343 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 344 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 345 346 347 /* Description EPD_OUTPUT 348 349 Consumer: TX OLE 350 Producer: SW 351 352 If set use EPD instead of LPD 353 */ 354 355 #define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 356 #define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 357 #define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 358 #define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 359 360 361 /* Description WDS 362 363 If set all the frames in this transmission (for this user) 364 are 4-address frame. 365 366 If not all frames need to use 4 address format, SW has per 367 frame 'wds' control, by using the 'wds' flag in the MSDU_EXTENSION 368 descriptor 369 370 Used by the OLE during encapsulation. 371 <legal all> 372 */ 373 374 #define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 375 #define TX_PEER_ENTRY_WDS_LSB 46 376 #define TX_PEER_ENTRY_WDS_MSB 46 377 #define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 378 379 380 /* Description INSERT_OR_STRIP 381 382 <enum 0 TXOLE_STRIP_VLAN> TXOLE will strip inner or outer 383 VLAN (if present in the frame) based on Strip_insert_vlan_{inner, 384 outer} 385 <enum 1 TXOLE_INSERT_VLAN> TXOLE will insert inner or outer 386 VLAN (only if absent in the frame) based on Strip_insert_vlan_{inner, 387 outer} with the TCI(s) given by Insert_vlan_{inner, outer}_tci 388 389 NOTE: Strip VLAN is not supported by TCL. 390 <legal all> 391 */ 392 393 #define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 394 #define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 395 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 396 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 397 398 399 /* Description SW_FILTER_ID 400 401 Consumer: SCH 402 Producer: SW 403 404 The full STA AID. 405 Use by SCH to determine if transmission for this STA should 406 be filtered as it just went into power save state. 407 In case of MU transmission, it means only this STA needs 408 to be removed from the transmission... 409 410 <legal all> 411 */ 412 413 #define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 414 #define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 415 #define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 416 #define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 417 418 419 /* Description TEMPORAL_KEY_31_0 420 421 Consumer: TX CRYPTO 422 Producer: SW 423 424 First 32 bits of the temporal key material. The temporal 425 key for WEP 40-bit uses the first 40 bits, WEP 104-bit 426 uses the first 104 bits, WEP 128-bit uses all 128 bits, 427 TKIP with/without MIC uses 128 bits, WAPI uses all 128 bits, 428 and AES-CCM uses all 128 bits. 429 430 Note that for TKIP, the 64 MIC bits are located in fields 431 'temporal_key[255:192] 432 <legal all> 433 */ 434 435 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 436 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 437 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 438 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff 439 440 441 /* Description TEMPORAL_KEY_63_32 442 443 Consumer: TX CRYPTO 444 Producer: SW 445 446 Second 32 bits of the temporal key material. See the description 447 of temporal_key_31_0. 448 <legal all> 449 */ 450 451 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 452 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 453 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 454 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 455 456 457 /* Description TEMPORAL_KEY_95_64 458 459 Consumer: TX CRYPTO 460 Producer: SW 461 462 Third 32 bits of the temporal key material. See the description 463 of temporal_key_31_0. 464 <legal all> 465 */ 466 467 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 468 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 469 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 470 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff 471 472 473 /* Description TEMPORAL_KEY_127_96 474 475 Consumer: TX CRYPTO 476 Producer: SW 477 478 Fourth 32 bits of the temporal key material. See the description 479 of temporal_key_31_0. 480 <legal all> 481 */ 482 483 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 484 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 485 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 486 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 487 488 489 /* Description TEMPORAL_KEY_159_128 490 491 Consumer: TX CRYPTO 492 Producer: SW 493 494 Fifth 32 bits of the temporal key material. See the description 495 of temporal_key_31_0. 496 497 <legal all> 498 */ 499 500 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 501 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 502 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 503 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff 504 505 506 /* Description TEMPORAL_KEY_191_160 507 508 Consumer: TX CRYPTO 509 Producer: SW 510 511 Final 32 bits of the temporal key material. See the description 512 of temporal_key_31_0. 513 514 <legal all> 515 */ 516 517 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 518 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 519 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 520 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 521 522 523 /* Description TEMPORAL_KEY_223_192 524 525 Consumer: TX CRYPTO 526 Producer: SW 527 528 Final 32 bits of the temporal key material. See the description 529 of temporal_key_31_0. 530 531 For TKIP this is the TX MIC key[31:0]. 532 <legal all> 533 */ 534 535 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 536 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 537 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 538 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff 539 540 541 /* Description TEMPORAL_KEY_255_224 542 543 Consumer: TX CRYPTO 544 Producer: SW 545 546 Final 32 bits of the temporal key material. See the description 547 of temporal_key_31_0. 548 549 For TKIP this is the TX MIC key[63:32]. 550 <legal all> 551 */ 552 553 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 554 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 555 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 556 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 557 558 559 /* Description STA_PARTIAL_AID 560 561 This field in only used by the PDG. All other modules should 562 ignore this field. 563 564 This field is only valid in case of a transmission at VHT 565 rates or HE rates. 566 567 For VHT: 568 This field is the Partial AID to be filled in to the VHT 569 preamble. 570 571 For HE: 572 This field is the sta_aid to be filled into the SIG B field. 573 574 575 In 11ah mode of operation, this field is provided by SW 576 to populate the the ID value of the SIG preamble of the 577 PPDU 578 */ 579 580 #define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 581 #define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 582 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 583 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff 584 585 586 /* Description TRANSMIT_VIF 587 588 Consumer: TXOLE 589 Producer: SW 590 591 The VIF for this transmission. Used in MCC mode to control/overwrite 592 the PM bit settings. 593 <legal all> 594 */ 595 596 #define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 597 #define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 598 #define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 599 #define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 600 601 602 /* Description BLOCK_THIS_USER 603 604 Consumer: PDG 605 Producer: SCH 606 607 Set by SCH when a MU transmission is started and this STA 608 has (just) entered or is in power save mode. 609 Due to the MU transmission SCH shall not terminate this 610 MU transmission (as is done with SU transmission), but continue 611 with the transmissions for all other STAs. 612 613 As a result of this bit being set, PDG will at certain moment 614 generate the MPDU limit TLV with field Num_mpdu_user set 615 to 0 616 617 PDG shall treat this user as a user without any data. All 618 rules related to terminating MU transmissions when too 619 many users do not have any data shall include this user 620 as a user having zero data. 621 622 When clear, PDG can ignore this bit 623 <legal all> 624 */ 625 626 #define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 627 #define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 628 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 629 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 630 631 632 /* Description MESH_AMSDU_MODE 633 634 Consumer: TX OLE 635 Producer: SW 636 637 This field is used only when the first MSDU of any MPDU 638 that TX OLE encounters is in Native WiFi format and includes 639 a 'Mesh Control' field between the header and the LLC. 640 641 The creation of the A-MSDU 'Length' field in the MPDU (if 642 aggregating multiple MSDUs) is decided by the value of 643 this field. 644 645 <enum 0 MESH_MODE_0> DO NOT USE 646 <enum 1 MESH_MODE_Q2Q> A-MSDU 'Length' is big endian and 647 includes the length of Mesh Control. 648 <enum 2 MESH_MODE_11S_BE> A-MSDU 'Length' is big endian 649 and excludes the length of Mesh Control. 650 <enum 3 MESH_MODE_11S_LE> A-MSDU 'Length' is little endian 651 and excludes the length of Mesh Control. This is 802.11s-compliant. 652 653 654 NOTE 1: For compatibility TXOLE treats MESH_MODE_0 identically 655 to MESH_MODE_Q2Q. 656 657 NOTE 2: This e-numeration is different from other fields 658 named Mesh_sta or mesh_enable where the value zero disables 659 mesh processing. 660 <legal 0-3> 661 */ 662 663 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 664 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 665 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 666 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 667 668 669 670 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 671 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 672 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 673 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 674 675 676 /* Description DL_UL_DIRECTION 677 678 'Direction' to be inferred for raw WiFi esp. management 679 frames sent to a multi-link peer, for translating RA and/or 680 TA. 681 682 <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS> 683 <enum 1 DL_UL_FLAG_IS_UL> 684 <legal all> 685 */ 686 687 #define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 688 #define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 689 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 690 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 691 692 693 /* Description RESERVED_12 694 695 <legal 0> 696 */ 697 698 #define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 699 #define TX_PEER_ENTRY_RESERVED_12_LSB 20 700 #define TX_PEER_ENTRY_RESERVED_12_MSB 31 701 #define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 702 703 704 /* Description INSERT_VLAN_OUTER_TCI 705 706 The tag control info to use when TXOLE inserts outer VLAN 707 if enabled by Strip_insert_vlan_outer and Insert_or_strip 708 709 */ 710 711 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 712 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 713 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 714 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 715 716 717 /* Description INSERT_VLAN_INNER_TCI 718 719 The tag control info to use when TXOLE inserts inner VLAN 720 if enabled by Strip_insert_vlan_inner and Insert_or_strip 721 722 */ 723 724 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 725 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 726 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 727 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 728 729 730 /* Description MULTI_LINK_ADDR_AD1_31_0 731 732 Consumer: TX CRYPTO 733 Producer: FW 734 735 Field only valid if Multi_link_addr_crypto_enable is set 736 737 738 Multi-link receiver address (address1) for transmissions 739 matching this peer entry, bits [31:0] 740 */ 741 742 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000038 743 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB 0 744 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB 31 745 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff 746 747 748 /* Description MULTI_LINK_ADDR_AD1_47_32 749 750 Consumer: TX CRYPTO 751 Producer: FW 752 753 Field only valid if Multi_link_addr_crypto_enable is set 754 755 756 Multi-link receiver address (address1) for transmissions 757 matching this peer entry, bits [47:32] 758 */ 759 760 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000038 761 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB 32 762 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB 47 763 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 764 765 766 /* Description MULTI_LINK_ADDR_AD2_15_0 767 768 Consumer: TX CRYPTO 769 Producer: FW 770 771 Field only valid if Multi_link_addr_crypto_enable is set 772 773 774 Multi-link transmitter address (address2) for transmissions 775 matching this peer entry, bits [15:0] 776 */ 777 778 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000038 779 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB 48 780 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB 63 781 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 782 783 784 /* Description MULTI_LINK_ADDR_AD2_47_16 785 786 Consumer: TX CRYPTO 787 Producer: FW 788 789 Field only valid if Multi_link_addr_crypto_enable is set 790 791 792 Multi-link transmitter address (address2) for transmissions 793 matching this peer entry, bits [47:16] 794 */ 795 796 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000040 797 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB 0 798 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB 31 799 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff 800 801 802 /* Description MULTI_LINK_ADDR_CRYPTO_ENABLE 803 804 Consumer: TX CRYPTO 805 Producer: FW 806 807 If set, TX CRYPTO shall convert Address1, Address2 and BSSID 808 of received data frames to multi-link addresses for the 809 AAD and Nonce during encryption. 810 <legal all> 811 */ 812 813 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 814 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 815 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 816 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 817 818 819 /* Description RESERVED_17A 820 821 <legal 0> 822 */ 823 824 #define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 825 #define TX_PEER_ENTRY_RESERVED_17A_LSB 33 826 #define TX_PEER_ENTRY_RESERVED_17A_MSB 47 827 #define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 828 829 830 /* Description SW_PEER_ID 831 832 This field indicates a unique peer identifier provided by 833 FW, to be logged via TXMON to host SW. 834 835 <legal all> 836 */ 837 838 #define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 839 #define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 840 #define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 841 #define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 842 843 844 845 #endif // TX_PEER_ENTRY 846