1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 18 #define _U_SIG_EHT_SU_MU_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 23 24 25 struct u_sig_eht_su_mu_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t phy_version : 3, // [2:0] 28 transmit_bw : 3, // [5:3] 29 dl_ul_flag : 1, // [6:6] 30 bss_color_id : 6, // [12:7] 31 txop_duration : 7, // [19:13] 32 disregard_0a : 5, // [24:20] 33 validate_0b : 1, // [25:25] 34 reserved_0c : 6; // [31:26] 35 uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] 36 validate_1a : 1, // [2:2] 37 punctured_channel_information : 5, // [7:3] 38 validate_1b : 1, // [8:8] 39 mcs_of_eht_sig : 2, // [10:9] 40 num_eht_sig_symbols : 5, // [15:11] 41 crc : 4, // [19:16] 42 tail : 6, // [25:20] 43 dot11ax_su_extended : 1, // [26:26] 44 reserved_1d : 3, // [29:27] 45 rx_ndp : 1, // [30:30] 46 rx_integrity_check_passed : 1; // [31:31] 47 #else 48 uint32_t reserved_0c : 6, // [31:26] 49 validate_0b : 1, // [25:25] 50 disregard_0a : 5, // [24:20] 51 txop_duration : 7, // [19:13] 52 bss_color_id : 6, // [12:7] 53 dl_ul_flag : 1, // [6:6] 54 transmit_bw : 3, // [5:3] 55 phy_version : 3; // [2:0] 56 uint32_t rx_integrity_check_passed : 1, // [31:31] 57 rx_ndp : 1, // [30:30] 58 reserved_1d : 3, // [29:27] 59 dot11ax_su_extended : 1, // [26:26] 60 tail : 6, // [25:20] 61 crc : 4, // [19:16] 62 num_eht_sig_symbols : 5, // [15:11] 63 mcs_of_eht_sig : 2, // [10:9] 64 validate_1b : 1, // [8:8] 65 punctured_channel_information : 5, // [7:3] 66 validate_1a : 1, // [2:2] 67 eht_ppdu_sig_cmn_type : 2; // [1:0] 68 #endif 69 }; 70 71 72 /* Description PHY_VERSION 73 74 <enum 0 U_SIG_VERSION_EHT> 75 Values 1 - 7 are reserved. 76 <legal 0 77 */ 78 79 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 80 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 81 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 82 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 83 84 85 /* Description TRANSMIT_BW 86 87 Bandwidth of the PPDU 88 89 <enum 0 U_SIG_BW20> 20 MHz 90 <enum 1 U_SIG_BW40> 40 MHz 91 <enum 2 U_SIG_BW80> 80 MHz 92 <enum 3 U_SIG_BW160> 160 MHz 93 <enum 4 U_SIG_BW320> 320 MHz 94 <enum 5 U_SIG_BW320_2> DO NOT USE 95 96 Microcode remaps 'U_SIG_BW320' based on channelization. 97 98 On RX side, field used by MAC HW 99 <legal all> 100 */ 101 102 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 103 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 104 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 105 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 106 107 108 /* Description DL_UL_FLAG 109 110 Differentiates between DL and UL transmission 111 112 <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS> 113 <enum 1 DL_UL_FLAG_IS_UL> 114 <legal all> 115 */ 116 117 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 118 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 119 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 120 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 121 122 123 /* Description BSS_COLOR_ID 124 125 BSS color ID 126 127 Field used by MAC HW 128 <legal all> 129 */ 130 131 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 132 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 133 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 134 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 135 136 137 /* Description TXOP_DURATION 138 139 Indicates the remaining time in the current TXOP 140 141 Field used by MAC HW 142 <legal all> 143 */ 144 145 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 146 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 147 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 148 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 149 150 151 /* Description DISREGARD_0A 152 153 Note: spec indicates this shall be set to 1s 154 <legal 31> 155 */ 156 157 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 158 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 159 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 160 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 161 162 163 /* Description VALIDATE_0B 164 165 Note: spec indicates this shall be set to 1 166 <legal 1> 167 */ 168 169 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 170 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 171 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 172 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 173 174 175 /* Description RESERVED_0C 176 177 <legal 0> 178 */ 179 180 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 181 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 182 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 183 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 184 185 186 /* Description EHT_PPDU_SIG_CMN_TYPE 187 188 <enum 3 EHT_PPDU_SIG_rsvd> DO NOT USE 189 <enum 0 EHT_PPDU_SIG_TB_or_DL_OFDMA> Need to look at both 190 EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) 191 192 <enum 2 EHT_PPDU_SIG_DL_MU_MIMO> Need to look at both EHT-SIG 193 content channels 194 <enum 1 EHT_PPDU_SIG_SU> Need to look at only one EHT-SIG 195 content channel 196 <legal all> 197 */ 198 199 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 200 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 201 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 202 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 203 204 205 /* Description VALIDATE_1A 206 207 Note: spec indicates this shall be set to 1 208 <legal 1> 209 */ 210 211 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 212 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 213 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 214 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 215 216 217 /* Description PUNCTURED_CHANNEL_INFORMATION 218 219 For OFDMA BW 20 MHz or 40 MHz: 220 Set to all 1s, i.e. 31 221 222 For OFDMA of higher BW: 223 Bit 3 = lowest 20 MHz in the current 80 MHz 224 Bit 6 = highest 20 MHz in the current 80 MHz 225 Bit 7 = 1 226 227 Each bit indicates whether the 20 MHz is modulated or punctured 228 229 0 = punctured 230 1 = modulated 231 232 For non-OFDMA: 233 Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding' 234 elsewhere in the data structures 235 236 <legal all> 237 */ 238 239 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 240 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 241 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 242 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 243 244 245 /* Description VALIDATE_1B 246 247 Note: spec indicates this shall be set to 1 248 <legal 1> 249 */ 250 251 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 252 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 253 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 254 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 255 256 257 /* Description MCS_OF_EHT_SIG 258 259 Indicates the MCS of EHT-SIG 260 0 - 1: MCS 0 - 1 261 2: MCS 3 262 3: MCS 0 with DCM 263 <legal all> 264 */ 265 266 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 267 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 268 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 269 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 270 271 272 /* Description NUM_EHT_SIG_SYMBOLS 273 274 Number of symbols 275 276 The actual number of symbols is 1 larger than indicated 277 in this field. 278 279 <legal all> 280 */ 281 282 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 283 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 284 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 285 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 286 287 288 /* Description CRC 289 290 CRC for U-SIG contents 291 <legal all> 292 */ 293 294 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 295 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 296 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 297 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 298 299 300 /* Description TAIL 301 302 <legal 0> 303 */ 304 305 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 306 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 307 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 308 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 309 310 311 /* Description DOT11AX_SU_EXTENDED 312 313 TX side: 314 Set to 0 315 316 RX side: On RX side, evaluated by MAC HW 317 318 This is the only way for MAC RX to know that this was a 319 U_SIG_EHT_SU received in extended range format. 320 321 When set, the 11be frame is of the extended range format. 322 323 <legal all> 324 */ 325 326 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 327 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 328 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 329 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 330 331 332 /* Description RESERVED_1D 333 334 <legal 0> 335 */ 336 337 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 338 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 339 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 340 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 341 342 343 /* Description RX_NDP 344 345 TX side: 346 Set to 0 347 348 RX side: On RX side, looked at by MAC HW 349 350 When set, PHY has received an (expected) NDP frame 351 <legal all> 352 */ 353 354 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 355 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 356 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 357 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 358 359 360 /* Description RX_INTEGRITY_CHECK_PASSED 361 362 TX side: Set to 0 363 RX side: Set to 1 if PHY determines the U-SIG CRC check 364 has passed, else set to 0 365 366 <legal all> 367 */ 368 369 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 370 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 371 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 372 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 373 374 375 376 #endif // U_SIG_EHT_SU_MU_INFO 377